JP6868455B2 - 電子部品パッケージおよびその製造方法 - Google Patents
電子部品パッケージおよびその製造方法 Download PDFInfo
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- JP6868455B2 JP6868455B2 JP2017084662A JP2017084662A JP6868455B2 JP 6868455 B2 JP6868455 B2 JP 6868455B2 JP 2017084662 A JP2017084662 A JP 2017084662A JP 2017084662 A JP2017084662 A JP 2017084662A JP 6868455 B2 JP6868455 B2 JP 6868455B2
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- electronic component
- base material
- ceramic base
- die bond
- terminal electrode
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- H01L2924/1033—Gallium nitride [GaN]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Description
本願発明者らは、パッケージ技術に関し、以下の如くの課題があることを見出し、本開示に係る電子部品パッケージおよびその製造方法を案出するに至った。
また、本開示の一態様に係る電子部品パッケージの製造方法は、キャリア上にてセラミック基材と接合した金属部材をパターニング処理してダイボンド部と端子電極部とを形成する工程、前記ダイボンド部上に電子部品を配置する工程、前記電子部品を覆うように前記キャリア上に封止樹脂層を形成することにより、前記キャリア、前記セラミック基材、前記金属部材および前記電子部品を含むパッケージ前駆体を作製する工程、ならびに前記パッケージ前駆体から前記キャリアを剥離する工程を含む。。
図1に、本開示の一態様に係る電子部品パッケージ100の構成を模式的に示す。図示されるように、本開示の一態様に係る電子部品パッケージ100は、金属部材10、セラミック基材20、電子部品30および封止樹脂層40を少なくとも備える。
図4Aから図4Dに、本開示の一態様に係る製造方法の概念を示す。まず、図4Aに示すように、セラミック基材20と、金属部材10とが配置されたキャリア50を準備する。次に、図4Bに示すように、金属部材10をパターニング処理してダイボンド部12と端子電極部17とを形成した後、ダイボンド部12上に電子部品30を配置する。次に、図4Cに示すように、電子部品30を覆うようにキャリア50上に封止樹脂層40を形成することにより、キャリア50、セラミック基材20、金属部材10および電子部品30を含むパッケージ前駆体60を作製する。最後に、図4Dに示すように、パッケージ前駆体60からキャリア50を剥離する。
本開示の第1実施形態に係る製造方法について、図5Aから図5Hを用いて説明する。
(i)粘着性を有するキャリア上にセラミック基材を配置する工程、
(ii)めっき処理を実施し、セラミック基材を覆う金属部材を形成する工程、
(iii)金属部材をパターニング処理し、金属部材からダイボンド部と端子電極部とを形成する工程、
(iv)ダイボンド部上に電子部品を配置し、電子部品と端子電極部とを電気的に接続する工程、
(v)電子部品、金属部材およびセラミック基材を覆うようにキャリア上に封止樹脂層を形成し、パッケージ前駆体を形成する工程、ならびに
(vi)キャリアをパッケージ前駆体から剥離し、それによって、封止樹脂層の表面からセラミック基材、ダイボンド部および端子電極部を露出させる工程
を含むことを特徴としている。
次に、本開示の第2実施形態に係る製造方法について、図6Aから図6Gを用いて説明する。
(i)粘着性を有するキャリア上にセラミック基材および非めっき金属部を配置する工程、
(ii)めっき処理を実施してセラミック基材および非めっき金属部を覆うめっき層を形成することによって、めっき層と非めっき金属部とが組み合わされた金属部材を得る工程、
(iii)金属部材をパターニング処理し、金属部材からダイボンド部と端子電極部とを形成する工程、
(iv)ダイボンド部上に電子部品を配置し、電子部品と端子電極部とを電気的に接続する工程、
(v)電子部品、金属部材およびセラミック基材を覆うようにキャリア上に封止樹脂層を形成し、パッケージ前駆体を得る工程、ならびに
(vi)キャリアをパッケージ前駆体から剥離し、それによって、封止樹脂層の表面からセラミック基材、ダイボンド部および端子電極部を露出させる工程
を含むことを特徴としている。ここで、非めっき金属部は本開示における第一金属部に相当し、めっき層は本開示における第二金属部に相当する。
10a 第一めっき層
10b 第二めっき層
10c 非めっき金属部
12 ダイボンド部、
17 端子電極部
20 セラミック基材
30 電子部品
40 封止樹脂層
50 キャリア
52 支持基材
54 粘着層
60 パッケージ前駆体
70 金属線
100 電子部品パッケージ
120、170 凹部
200 領域
Claims (9)
- 封止樹脂層、
前記封止樹脂層に埋設され、ダイボンド部と前記ダイボンド部の外側に位置する端子電極部とを含む金属部材、
前記封止樹脂層に埋設されたセラミック基材、および
前記ダイボンド部上に配置された電子部品を備え、
平面視において、前記ダイボンド部と前記セラミック基材とが互いに部分的に重なり合って接触しており、
平面視において、前記端子電極部と前記セラミック基材とが互いに部分的に重なり合って接触しており、
前記電子部品と前記端子電極部とが電気的に接続されており、
前記金属部材が、第一めっき層と第二めっき層とを含み、
前記第一めっき層の平均結晶粒径は前記第二めっき層の平均結晶粒径よりも小さい、電子部品パッケージ。 - 前記ダイボンド部の外縁の下面と前記セラミック基材の外縁の上面とが接触している、
請求項1に記載の電子部品パッケージ。 - 前記ダイボンド部の外縁に第一凹部が設けられており、
前記第一凹部に前記セラミック基材の第一部分が配置されている、
請求項1または2に記載の電子部品パッケージ。 - 前記端子電極部の外縁の下面と前記セラミック基材の外縁の上面とが接触している、
請求項1に記載の電子部品パッケージ。 - 前記端子電極部の外縁に第二凹部が設けられており、
前記第二凹部に前記セラミック基材の第二部分が配置されている、
請求項1または2に記載の電子部品パッケージ。 - 前記ダイボンド部と前記端子電極部と前記セラミック基材とが前記電子部品パッケージの下面にて面一となっている、
請求項1から5のいずれかに記載の電子部品パッケージ。 - 前記第一めっき層において、前記ダイボンド部と前記セラミック基材とが接触し、
前記第一めっき層において、前記端子電極部と前記セラミック基材とが接触している、 請求項1から6のいずれかに記載の電子部品パッケージ。 - 前記電子部品がパワー半導体素子である、
請求項1から7のいずれかに記載の電子部品パッケージ。 - 前記パワー半導体素子がワイドギャップ半導体素子である、
請求項8に記載の電子部品パッケージ。
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