CN108630652B - 半导体装置、用于半导体装置的制造方法以及电极板 - Google Patents

半导体装置、用于半导体装置的制造方法以及电极板 Download PDF

Info

Publication number
CN108630652B
CN108630652B CN201810224113.8A CN201810224113A CN108630652B CN 108630652 B CN108630652 B CN 108630652B CN 201810224113 A CN201810224113 A CN 201810224113A CN 108630652 B CN108630652 B CN 108630652B
Authority
CN
China
Prior art keywords
solder
electrode plate
metal member
grooves
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810224113.8A
Other languages
English (en)
Other versions
CN108630652A (zh
Inventor
高萩智
舟野祥
门口卓矢
花木裕治
岩崎真悟
川岛崇功
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Publication of CN108630652A publication Critical patent/CN108630652A/zh
Application granted granted Critical
Publication of CN108630652B publication Critical patent/CN108630652B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L23/4012Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws for stacked arrangements of a plurality of semiconductor devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331Disposition
    • H01L2224/3318Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/8321Applying energy for connecting using a reflow oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/83815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明涉及半导体装置、用于半导体装置的制造方法以及电极板。半导体装置包含电极板、金属构件以及将金属构件与电极板连接的焊料。在电极板的表面上,设置了第一沟槽和第二沟槽组。第一沟槽具有第一直线部分到第四直线部分。该第二沟槽组布置在由第一沟槽包围的范围内,并且具有在与第一沟槽连接的外周侧上的端部。该第二沟槽组包含第一集合到第四集合。所述集合中的每一个包含与第一直线部分到第四直线部分连接的多个第二沟槽。当在电极板和金属构件的层压方向上看金属构件时,金属构件的与焊料连接的区域的外周边缘横穿第一集合到第四集合。

Description

半导体装置、用于半导体装置的制造方法以及电极板
技术领域
本发明涉及半导体装置、用于半导体装置的制造方法以及电极板。
背景技术
日本专利申请公报No.2016-195222(JP 2016-195222A)中所公开的半导体装置包含电极板、金属构件以及将电极板连接到金属构件的焊料。在电极板的表面上,设置了以环状延伸的多个环状沟槽。电极板的表面的中央部分由多个环状沟槽包围。金属构件通过焊料而与设置了多个环状沟槽的范围连接。
前述多个环状沟槽被设置成停止焊料的润湿和散布。通过在电极板中设置多个环状沟槽,不同大小的各种类型的金属构件可适当地焊接到电极板。例如,下文解释设置了三个环状沟槽的情况(换句话说,设置了处于最外周侧上的第一环状沟槽、设置在第一环状沟槽的内周侧上的第二环状沟槽以及设置在第二环状沟槽的内周侧上的第三环状沟槽的情况)。
当小于第三环状沟槽的金属构件被焊接到电极板时,金属构件被焊接到在第三环状沟槽的内周侧上的范围。在此情况下,从金属构件与电极板之间的位置朝向外周侧溢流的焊料朝向外周侧润湿并散布在电极板的表面上。一旦润湿且散布的焊料到达第三环状沟槽,焊料的润湿和散布便在第三环状沟槽处停止。因此,防止了焊料的不必要的润湿和散布,并且形成了具有适当形状的焊料焊脚。
当大于第三环状沟槽且小于第二环状沟槽的金属构件被焊接到金属板时,金属构件被布置在第二环状沟槽的内周侧上的范围中,以使得金属构件覆盖第三环状沟槽,并且金属构件被焊接到第二环状沟槽的内周侧上的范围。在此情况下,从金属构件与电极板之间的位置朝向外周侧溢流的焊料的润湿和散布在第二环状沟槽处停止。因此,形成了具有适当形状的焊料焊脚。
当大于第二环状沟槽且小于第一环状沟槽的金属构件被焊接到电极板时,金属构件被布置在第一环状沟槽的内周侧上的范围中,以使得金属构件覆盖第二环状沟槽和第三环状沟槽,并且金属构件被焊接到第一环状沟槽上的内周侧上的范围。在此情况下,从金属构件与电极板之间的位置朝向外周侧溢流的焊料的润湿和散布在第一环状沟槽处停止。因此,形成了具有适当形状的焊料焊脚。
如上所述,只要金属构件小于第一环状沟槽,不同大小的各种金属构件便可被焊接到电极板。
发明内容
在JP 2016-195222 A中所述的半导体装置中,存在金属构件在环状沟槽和金属构件具有特定位置关系时无法适当地焊接到电极板的情形。下文中,作为示例来解释第三环状沟槽与金属构件之间的位置关系。然而,相同情况适用于其它环状沟槽。当金属构件具有与第三环状沟槽大体上相同的大小时,金属构件的外周边缘被布置成邻近于第三环状沟槽。在此情况下,从金属构件与电极板之间的位置朝向外周侧溢流的焊料的润湿和散布可在第三环状沟槽处停止,或可横穿第三环状沟槽并到达外周侧。焊料的润湿和散布范围取决于位置而不同,并且这可导致焊料的扭曲形状。此外,当金属构件具有与第三环状沟槽大体上相同的大小时,存在金属构件的一部分由于错误从第三环状沟槽伸出到外侧的情形。此外,例如,当长方形金属构件被用于正方形第三环状沟槽时,存在金属构件的一部分从第三环状沟槽伸出到外侧的情形。当如上所述金属构件的一部分从第三环状沟槽伸出到外侧时,焊料的润湿和散布在金属构件从第三环状沟槽伸出到外侧的位置处达到第二环状沟槽,并且在金属构件不从第三环状沟槽伸出到外侧的位置处,焊料在第三环状沟槽处停止。因此,焊料变成扭曲形状。当焊料如上所述具有扭曲形状时,高应力倾向于在焊料内产生,从而降低焊料的可靠性。在批量生产时,焊料的形状不稳定,并且焊料的质量大幅变化。如上所述,根据JP 2016-195222 A中所述的技术,存在无法准确地控制焊料的润湿和散布范围的情形。
在JP 2016-195222 A中,块状金属构件焊接到电极板。然而,在其它类型的金属构件(例如,半导体芯片的表面电极等)焊接到电极板时,发生类似问题。在本说明书中,提供一种使得可以将较广泛种类的金属构件适当地焊接到电极板的技术。
本发明的第一方面包含电极板、金属构件以及将金属构件与电极板连接的焊料。在电极板的表面上,设置了第一沟槽和第二沟槽组。第一沟槽具有沿着矩形的各边延伸的第一直线部分、第二直线部分、第三直线部分和第四直线部分,并且以环状延伸。该第二沟槽组布置在由第一沟槽包围的范围内,并且在与第一沟槽连接的外周侧上具有端部。该第二沟槽组包含多个第二沟槽。该第二沟槽组包含:具有与第一直线部分连接的多个第二沟槽的第一集合、具有与第二直线部分连接的多个第二沟槽的第二集合、具有与第三直线部分连接的多个第二沟槽的第三集合,以及具有与第四直线部分连接的多个第二沟槽的第四集合。焊料连接该范围内的电极板的表面以及金属构件的表面,该金属构件的表面面对电极板的表面。当在电极板和金属构件的层压方向上看金属构件时,金属构件的区域的外周边缘被布置成横穿第一集合、第二集合、第三集合和第四集合,该区域与焊料连接。
只要第一沟槽具有其中使得沿着矩形的各边延伸的第一直线部分到第四直线部分得以设置的结构并以环状延伸,剩余部分便可呈任何形状。例如,第一沟槽可具有带有倒角的矩形。
在此半导体装置中,该第一沟槽和该第二沟槽组设置在电极板的表面中。该第二沟槽组布置在由第一沟槽包围的范围内,并且其处于外周侧上的端部与第一沟槽连接。此外,金属构件的、与焊料连接的区域的外周边缘被布置成横穿该第二沟槽组(换句话说,第一集合、第二集合、第三集合和第四集合)。因此,在焊接的同时从金属构件与电极板之间的位置溢流到外周侧的焊料容易沿着该第二沟槽组润湿并散布到外周侧,并且因此容易到达第一沟槽。一旦焊料到达第一沟槽,焊料便流动到第一沟槽中,并且焊料到第一沟槽的外周侧的润湿和散布得以抑制。在此半导体装置中,在第一沟槽的内周侧上,焊料的润湿和散布通过该第二沟槽组促进,并且焊料到第一沟槽的外侧的润湿和散布由第一沟槽抑制。因此,只要金属构件的、与焊料连接的区域的外周边缘被布置成横穿该第二沟槽组,润湿且散布的焊料就以稳定方式到达第一沟槽并且焊料在第一沟槽处停止,而无关于金属构件的大小和形状。根据此结构,较广泛种类的金属构件可适当地焊接到电极板。
在本发明的第一方面中,电极板可在该范围的中央包含平坦表面,并且平坦表面不需要具有该第二沟槽组。
在本发明的第一方面中,第二沟槽中的每一个第二沟槽可不与其它第二沟槽连接。也就是说,第一集合的第二沟槽可不与第二集合到第四集合的第二沟槽连接。焊料可被树脂覆盖。
在本发明的第一方面中,第二沟槽中的每一个第二沟槽可与第一沟槽垂直连接。
在本发明的第一方面中,半导体芯片可通过焊料而与电极板的相反侧上的金属构件的表面连接。
在本发明的第一方面中,金属构件可以是半导体芯片的表面电极。
本发明的第二方面涉及一种用于半导体装置的制造方法。本发明的第二方面包含通过焊料而将金属构件与电极板连接。在电极板的表面上,设置了第一沟槽和第二沟槽组。第一沟槽具有沿着矩形的各边延伸的第一直线部分、第二直线部分、第三直线部分和第四直线部分,并且以环状延伸。该第二沟槽组布置在由第一沟槽包围的范围内,并且在与第一沟槽连接的外周侧上具有端部。该第二沟槽组包含多个第二沟槽,并且该第二沟槽组包含:具有与第一直线部分连接的多个第二沟槽的第一集合、具有与第二直线部分连接的多个第二沟槽的第二集合、具有与第三直线部分连接的多个第二沟槽的第三集合以及具有与第四直线部分连接的多个第二沟槽的第四集合。当通过焊料而将金属构件与电极板连接时,电极板和金属构件彼此面对,并且当在电极板和金属构件的层压方向上看金属构件时,金属构件的、与焊料连接的区域的外周边缘被布置成横穿第一集合、第二集合、第三集合和第四集合,并且在此状态下,该范围和该区域通过焊料而彼此连接。
本发明的第三方面涉及一种用于连接半导体芯片的电极板。本发明的第三方面包含电极板,并且在电极板的表面上,设置了第一沟槽和第二沟槽组。第一沟槽具有沿着矩形的各边延伸的第一直线部分、第二直线部分、第三直线部分和第四直线部分,并且以环状延伸。该第二沟槽组布置在由第一沟槽包围的范围内,并且在与第一沟槽连接的外周侧上具有端部。该第二沟槽组包含多个第二沟槽,并且该第二沟槽组包含:具有与第一直线部分连接的多个第二沟槽的第一集合、具有与第二直线部分连接的多个第二沟槽的第二集合、具有与第三直线部分连接的多个第二沟槽的第三集合以及具有与第四直线部分连接的多个第二沟槽的第四集合。该范围用于接合焊料。
本说明书还提出一种用于通过经由焊料而将金属构件与具有第一沟槽和第二沟槽组的电极板连接来制造半导体装置的方法,以及一种用于该方法的电极板。
附图说明
将在下文参照附图来描述本发明的示范性实施例的特征、优点和技术与工业意义,其中相似附图标记表示相似元件,且其中:
图1是半导体装置的立体图;
图2是沿着图1和图3中的线II-II截取的半导体装置的截面图;
图3是电极板的下表面的平面图;
图4是沿着图3中的线IV-IV截取的半导体装置的截面图;
图5是半导体装置的制造过程的说明图;
图6是半导体装置的制造过程的说明图;
图7是半导体装置的制造过程的说明图;
图8是半导体装置的制造过程的说明图;
图9是半导体装置的制造过程的说明图;
图10是半导体装置的制造过程的说明图;
图11是对应于图2的截面图,并且示出根据改型的半导体装置;以及
图12是对应于图3的平面图,并且示出根据改型的电极板。
具体实施方式
根据实施例的图1中所示的半导体装置10具有充当绝缘体的树脂层60以及从树脂层60向外突出的主端子16和信号端子18。图5和图6示出半导体装置10的制造过程。如图5所示,在形成树脂层60之前,主端子16和信号端子18相互连接。下文中,将主端子16和信号端子18相互连接的部分被称为引线框12。引线框12包含散热片14a、14b。在图1中,散热片14a、14b被树脂层60覆盖。如图5中所示,绝缘栅双极晶体管(IGBT)20a和二极管22a布置在散热片14a上。金属块30a布置在IGBT 20a上。金属块32a布置在二极管22a上。如图6所示的电极板40a布置在图5所示的金属块30a、32a上。如图5所示,IGBT 20b和二极管22b布置在散热片14b上。金属块30b布置在IGBT 20b上。金属块32b布置在二极管22b上。如图6所示的电极板40b布置在图5所示的金属块30b、32b上。金属块30a、30b、32a、32b和电极板40a、40b由铜制成。在图1中,IGBT 20a、20b、二极管22a、22b、金属块30a、30b、32a、32b和电极板40a、40b被树脂层60覆盖。然而,电极板40a、40b的上表面从树脂层60暴露。IGBT 20a、20b和二极管22a、22b的主要部分分别通过焊料而与其它构件连接。IGBT 20a、20b和二极管22a、22b的连接结构大体上是相同的。因此,解释IGBT 20a的连接结构。
如图2中所示,IGBT 20a包含信号电极70、发射电极72、半导体衬底74以及集电极76。在半导体衬底74的上表面上,布置了信号电极70和发射电极72。虽然图2示出一个信号电极70,但多个信号电极70设置在半导体衬底74的上表面上。在半导体衬底74的下表面上,布置了集电极76。IGBT 20a布置在散热片14a上。集电极76通过焊料80而与散热片14a的上表面连接。多个信号端子18布置在IGBT 20a的侧面上。IGBT 20a的信号电极70中的每一个通过接合线19而与对应信号端子18连接。金属块30a布置在IGBT 20a的发射电极72上。发射电极72通过焊料82而与金属块30a的下表面连接。电极板40a布置在金属块30a上。金属块30a的上表面通过焊料84而与电极板40a的下表面连接。散热片14a的上表面、IGBT 20a、金属块30a以及电极板40a的下表面被树脂层60覆盖。
如图3中所示,以环状延伸的第一沟槽41以及线性延伸的多个第二沟槽42设置在电极板40a的下表面中。第一沟槽41沿着带有圆角的矩形延伸,并且具有四个直线部分41a到41d。多个第二沟槽42设置在由第一沟槽41包围的范围内。多个第二沟槽42从由第一沟槽41包围的范围的中央侧朝向外周侧延伸。外周侧上的第二沟槽42中的每一个第二沟槽的端部与第一沟槽41连接。多个第二沟槽42与第一沟槽41的对应直线部分41a到41d连接。下文中,与第一直线部分41a连接的多个第二沟槽42被称为第一集合,与第二直线部分41b连接的多个第二沟槽42被称为第二集合,与第三直线部分41c连接的多个第二沟槽42被称为第三集合,并且与第四直线部分41d连接的多个第二沟槽42被称为第四集合。第一集合的第二沟槽42中的每一个垂直于第一直线部分41a而延伸。第二集合的第二沟槽42中的每一个垂直于第二直线部分41b而延伸。第三集合的第二沟槽42中的每一个垂直于第三直线部分41c而延伸。第四集合的第二沟槽42中的每一个垂直于第四直线部分41d而延伸。如图2所示,第一沟槽41比第二沟槽42深。如图3所示,第二沟槽42中的每一个第二沟槽42除与第一沟槽41连接的部分之外不与其它沟槽连接。这意味,第二沟槽42中的每一个独立于其它第二沟槽42。在由第一沟槽41包围的范围的中央,设置了平坦表面44,其中没有设置第二沟槽42。
图3中的虚线示出金属块30a的位置。当在金属块30a和电极板40a的层压方向上看金属块30a时,金属块30a布置在由第一沟槽41包围的范围内。当如图3所示在层压方向上看金属块30a时,金属块30a的外周边缘被布置成横穿(交叉)第一集合到第四集合的第二沟槽42。如图2所示,焊料84结合到金属块30a的大致整个上表面。并且,焊料84在由第一沟槽41包围的大致整个范围中结合到电极板40a。焊料84结合到第一沟槽41的内表面以及第二沟槽42中的每一个的内表面。
图4是沿着图3中的线IV-IV截取的半导体装置10的截面图。图4示出焊料84的截面,其中焊料84覆盖了图3中由第一沟槽41包围的范围内的不与金属块30a重叠的范围。在图4所示的范围中,凹部和突出部沿着第二沟槽42而形成在焊料84的表面中。因为在焊料84的表面中存在凹部和突出部,所以树脂层60进入焊料84的表面中的凹入部分中。因此,树脂层60不可能与焊料84分离,并且因此树脂层60可以适当地保护IGBT 20a等。
接着,解释用于半导体装置10的制造方法。首先,如图5中所示,IGBT 20a、20b、二极管22a、22b、金属块30a、30b、32a、32b焊接到引线框12的散热片14a、14b上。更详细地说,焊料80的焊料片、IGBT 20a以及焊料82的焊料片和金属块30a按此次序层压在散热片14a上。针对IGBT 20b和二极管22a、22b,这些构件中的每一个以类似方式层压。接着,引线框12在回流焊炉中加热。接着,焊料片中的每一个熔融并接着凝固。如图2中所示,当焊料80的焊料片熔融并接着凝固时,焊料80结合到散热片14a和集电极76。因此,散热片14a和集电极76通过焊料80而相互连接。当焊料82的焊料片熔融并接着凝固时,焊料82结合到发射电极72和金属块30a。因此,发射电极72和金属块30a通过焊料82而相互连接。IGBT 20b和二极管22a、22b也以类似方式通过焊料而与构件中的每一个连接。
接着,IGBT 20a、20b的信号电极70中的每一个经由接合线19而与对应信号端子18连接。
接着,如图6中所示,电极板40a与金属块30a、32a连接,并且电极板40b与金属块30b、32b连接。因为用于连接电极板与金属块的方法大体上相同,所以解释用于连接电极板40a与金属块30a的方法。首先,如图7所示,电极板40a被布置成使得设置了第一沟槽41和第二沟槽42的侧面上的表面朝上。接着,焊料片84a布置在设置了第一沟槽41和第二沟槽42的表面上。此外,如图5所示组装的半完工部分布置在焊料片84a的顶部上。此处,金属块30a与焊料片84a的上表面接触。因此,焊料片84a夹在金属块30a与电极板40a之间。如图3所示,当在层压方向上看金属块30a时,金属块30a布置在由第一沟槽41包围的范围内,以使得金属块30a的外周边缘与第一集合到第四集合的第二沟槽42交叉。焊料片84a仅布置在紧接金属块30a之下的范围内,并且没有布置在金属块30a的外周侧上。
接着,图7中所示的层压结构在回流焊炉中被加热。接着,焊料84a熔融。熔融焊料从紧接金属块30a之下的范围朝向该范围的外周侧润湿和散布。焊料的部分流动到第二沟槽42中,如图7中的箭头所示。流动到第二沟槽42中的焊料朝向外周侧流动。此外,由第二沟槽42内的焊料引导,第二沟槽42外(换句话说,邻近于第二沟槽42的电极板40a的表面上)的焊料也朝向外周侧流动。这意味第二沟槽42促进焊料朝向外周侧的润湿和散布。一旦焊料到达第一沟槽41,焊料便流动到第一沟槽41中。这抑制焊料朝向第一沟槽41的外周侧的润湿和散布。因此,如图8所示,焊料84在由第一沟槽41包围的大致整个范围中润湿和散布。此后,一旦层压结构冷却下来,焊料84凝固。焊料84将金属块30a和电极板40a相互连接。
如图4中所示,在没有被金属块30a覆盖的范围内的焊料84的表面上,凹部和突出部沿着第二沟槽42而形成。
此外,如图8中所示,在由第一沟槽41包围(紧接金属块30a的中央部分之下)的范围的中央部分中,设置了平坦表面44,其中没有形成第二沟槽42。因此,平坦表面44与金属块30a之间的焊料84的厚度变小。焊料84的热导率小于金属块30a和电极板40a的热导率。因此,通过提供平坦表面44来减小电极板40a与金属块30a之间的焊料84的厚度,可以减小电极板40a与金属块30a之间的热阻。
即使在焊料84的量小时,第二沟槽42也促进焊料的润湿和散布。因此,焊料的润湿和散布在由第一沟槽41包围的大致整个范围中发生。此外,当焊料84的量大时,过量焊料被吸收在第一沟槽41内。因此,可以抑制过量焊料沿着金属块30a的侧表面向上爬升。如上所述,因为焊料的润湿和散布在由第一沟槽41包围的大致整个范围中适当地发生而无关于焊料84的量,所以焊料84的焊脚的形状稳定化。因此,焊料84的质量稳定化。
接着,如图9中所示,树脂层60通过注射成型而形成。树脂层60密封散热片14a、14b、IGBT 20a、20b、二极管22a、22b、金属块30a、30b、32a、32b和电极板40a、40b。此时,如图4所示,树脂层60流动到焊料84的表面中的凹入部分中。因此,树脂层60与焊料84的接触区域变大,因此使得树脂层60难以与焊料84分离。
接着,如图10中所示,通过切割树脂层60的上表面,电极板40a、40b暴露在树脂层60的上表面上。并且,虽然未示出,但通过切割树脂层60的下表面,散热片14a、14b暴露在树脂层60的下表面上。
接着,如图1中所示,通过切割引线框12的不必要的部分,主端子16和信号端子18相互分离。因此,完成了图1所示的半导体装置10。
在用于焊接金属块30a和电极板40a的上述方法中,金属块30a的整个上表面如图2中所示与焊料84连接,并且金属块30a的外周边缘(或与焊料84连接的金属块30a的上表面的外周边缘)如图3中所示被布置成横穿第一集合到第四集合的第二沟槽42。如上所述,只要金属块30的、与焊料84连接的区域的外周边缘被布置成横穿第一集合到第四集合的第二沟槽42,焊料84的润湿和散布便在由第一沟槽41包围的大致整个范围中发生。因此,即使在使用具有不同于图3所示的金属块30a的大小和形状的金属块的情况下,只要金属块30的、与焊料84连接的区域的外周边缘被布置成横穿第一集合到第四集合的第二沟槽42,便可以将焊料84适当地结合到由第一沟槽41包围的大致整个范围。这意味只要金属块的、与焊料84连接的区域的大小大于平坦表面44的大小且小于第一沟槽41的大小,便可以适当地焊接具有任何大小和形状的金属块。
此外,即使金属块30a的位置由于错误而移位,但只要金属块30的、与焊料84连接的区域的外周边缘被布置成横穿第一集合到第四集合的第二沟槽42,便可以将焊料84适当地结合到由第一沟槽41包围的大致整个范围。因此,即使在批量生产半导体装置10时存在金属块30a的安装位置的变化,焊料84的焊脚形状也稳定。因此,可以使焊料84的质量稳定化。
如上所述,根据本说明书中所公开的技术,在不同大小、形状和布置位置的金属块的情况下,可以将金属块适当地焊接到电极板40a。
根据前述实施例,第一沟槽和第二沟槽形成在金属块30a和电极板40a相互连接的区域中。然而,第一沟槽和第二沟槽可设置在其它金属构件和电极板相互连接的区域中。例如,如图11中所示,第一沟槽41和第二沟槽42可设置在集电极76(一种金属构件)和散热片14a(一种电极板)相互连接的区域(换句话说,散热片14a的表面)中。
并且,在前述实施例中,如图3中所示,第二沟槽42中的每一个是独立的。然而,例如,如图12中所示,第二沟槽42可在除第一沟槽41之外的部分中通过连接沟槽43相互连接。然而,当第二沟槽42如图12所示通过连接沟槽43而相互连接时,熔融树脂的流动容易在形成树脂层60时在由第二沟槽42和连接沟槽43包围的区域附近中断,并且这容易在树脂层60内导致空隙。因此,如图3所示,优选的是,第二沟槽相互独立。
此外,在前述实施例中,如图2中所示,金属块30a的整个上表面与焊料84连接。然而,金属块30a的上表面的一部分可与焊料84连接。在此情况下,仅需要的是,与焊料84连接的区域的外周边缘被布置成横穿第一集合、第二集合、第三集合和第四集合的第二沟槽42。在此情况下,金属块30的部分(远离焊料84的部分)的剩余部分可延伸到由第一沟槽41包围的范围的外侧。
前述实施例的部件与权利要求书的部件之间的关系被解释。实施例的金属块30a是权利要求书中的金属构件的示例。实施例中的金属块30a的上表面是权利要求书中金属构件的、与焊料连接的区域的示例。实施例中的IGBT 20a是权利要求书中的半导体芯片的示例。
下文列出本说明书书所公开的技术元素。以下技术元素相互独立地使用。
在本说明书中作为示例公开的半导体装置中,电极板可在由第一沟槽包围的范围的中央包含平坦表面,其中没有设置第二沟槽。
根据此结构,因为焊料的厚度在该范围的中央变小,所以可以减小金属构件与电极板之间的热阻。
在本说明书中作为示例公开的半导体装置中,第二沟槽中的每一个除第一沟槽以外不与其它第二沟槽连接,并且焊料可被树脂覆盖。
根据此结构,可以抑制在树脂中形成空隙。
已给出关于实施例的详细解释。然而,这仅是示例,并且不限制权利要求书的范围。权利要求书的范围中所述的技术包含上文所述的具体示例的各种改型和改变。本说明书和附图中所解释的技术元素单独或作为各种组合具有技术实用性,且不限于在申请时权利要求书中所述的组合。此外,本说明书和附图中作为示例解释的技术同时实现多个目标,并且通过实现这些目标中的一个而具有技术实用性。

Claims (7)

1.一种半导体装置,其特征在于包括:
电极板,在所述电极板的表面上,设置了具有环状的第一沟槽和第二沟槽组,所述第一沟槽具有沿着矩形的各边延伸的第一直线部分、第二直线部分、第三直线部分和第四直线部分,所述第二沟槽组被布置在由所述第一沟槽包围的范围内,并且具有与所述第一沟槽连接的外周侧上的端部,所述第二沟槽组包含多个第二沟槽,并且所述第二沟槽组包含具有与所述第一直线部分连接的所述多个第二沟槽的第一集合、具有与所述第二直线部分连接的所述多个第二沟槽的第二集合、具有与所述第三直线部分连接的所述多个第二沟槽的第三集合以及具有与所述第四直线部分连接的所述多个第二沟槽的第四集合;
金属构件;以及
焊料,所述焊料连接所述范围内的所述电极板的表面和所述金属构件的表面,所述金属构件的表面面对所述电极板的表面,其中
当在所述电极板和所述金属构件的层压方向上看所述金属构件时,所述金属构件的区域的外周边缘被布置成横穿所述第一集合、所述第二集合、所述第三集合和所述第四集合的所述多个第二沟槽中的每一个第二沟槽,所述区域与所述焊料连接。
2.根据权利要求1所述的半导体装置,其特征在于,所述电极板在所述范围的中央包含平坦表面,所述平坦表面不具有所述第二沟槽组。
3.根据权利要求1或2所述的半导体装置,其特征在于,所述第一集合的所述第二沟槽不与所述第二集合到所述第四集合的所述第二沟槽连接,并且所述焊料被树脂覆盖。
4.根据权利要求1或2所述的半导体装置,其特征在于,所述第二沟槽中的每一个第二沟槽均与所述第一沟槽垂直地连接。
5.根据权利要求1或2所述的半导体装置,其特征在于,半导体芯片通过焊料与在所述电极板的相反侧上的所述金属构件的表面连接。
6.根据权利要求1或2所述的半导体装置,其特征在于,所述金属构件是半导体芯片的表面电极。
7.一种用于半导体装置的制造方法,其特征在于包括:
通过焊料将金属构件与电极板连接,其中第一沟槽和第二沟槽组被设置在所述电极板的表面上,所述第一沟槽具有沿着矩形的各边延伸的第一直线部分、第二直线部分、第三直线部分和第四直线部分,并且以环状延伸,所述第二沟槽组被布置在由所述第一沟槽包围的范围内,并且具有与所述第一沟槽连接的外周侧上的端部,所述第二沟槽组包含多个第二沟槽,并且所述第二沟槽组包含具有与所述第一直线部分连接的所述多个第二沟槽的第一集合、具有与所述第二直线部分连接的所述多个第二沟槽的第二集合、具有与所述第三直线部分连接的所述多个第二沟槽的第三集合以及具有与所述第四直线部分连接的所述多个第二沟槽的第四集合,其中
当通过所述焊料将所述金属构件与所述电极板连接时,使所述电极板和所述金属构件彼此面对,并且,当在所述电极板和所述金属构件的层压方向上看所述金属构件时,所述金属构件的区域的外周边缘被布置成横穿所述第一集合、所述第二集合、所述第三集合和所述第四集合的所述多个第二沟槽中的每一个第二沟槽,所述区域与所述焊料连接,并且,在此状态下,所述范围和所述区域通过所述焊料彼此连接。
CN201810224113.8A 2017-03-21 2018-03-19 半导体装置、用于半导体装置的制造方法以及电极板 Active CN108630652B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017054815A JP6610590B2 (ja) 2017-03-21 2017-03-21 半導体装置とその製造方法
JP2017-054815 2017-03-21

Publications (2)

Publication Number Publication Date
CN108630652A CN108630652A (zh) 2018-10-09
CN108630652B true CN108630652B (zh) 2021-11-26

Family

ID=61691773

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810224113.8A Active CN108630652B (zh) 2017-03-21 2018-03-19 半导体装置、用于半导体装置的制造方法以及电极板

Country Status (6)

Country Link
US (1) US10475727B2 (zh)
EP (1) EP3379572B1 (zh)
JP (1) JP6610590B2 (zh)
KR (1) KR102073579B1 (zh)
CN (1) CN108630652B (zh)
TW (1) TWI676251B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6874467B2 (ja) * 2017-03-29 2021-05-19 株式会社デンソー 半導体装置とその製造方法
JP6834815B2 (ja) * 2017-07-06 2021-02-24 株式会社デンソー 半導体モジュール
US11257768B2 (en) * 2017-12-13 2022-02-22 Mitsubishi Electric Corporation Semiconductor device and power conversion device
US12062589B2 (en) * 2021-06-29 2024-08-13 Infineon Technologies Ag Semiconductor packages including recesses to contain solder
CN113707632B (zh) * 2021-08-30 2024-06-07 中国振华集团永光电子有限公司(国营第八七三厂) 一种三端整流电路模块及其制造方法
JP2023041490A (ja) * 2021-09-13 2023-03-24 株式会社東芝 半導体装置
JP7292352B2 (ja) * 2021-11-02 2023-06-16 三菱電機株式会社 樹脂封止型半導体装置及び樹脂封止型半導体装置の製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013123016A (ja) * 2011-12-12 2013-06-20 Denso Corp 半導体装置
CN105321936A (zh) * 2014-07-31 2016-02-10 富士电机株式会社 半导体装置及其制造方法
CN105814681A (zh) * 2013-11-29 2016-07-27 株式会社神户制钢所 底板以及具备底板的半导体装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100545866B1 (ko) * 2004-04-27 2006-01-24 삼성전자주식회사 커패시터 및 그 제조 방법
TWI247642B (en) * 2005-03-15 2006-01-21 Jian-Shian Li Position-actuating and controlling device for direct movement of electrode of electro-discharge machine
JP4702196B2 (ja) * 2005-09-12 2011-06-15 株式会社デンソー 半導体装置
US7661954B2 (en) * 2005-09-13 2010-02-16 Uwe Harneit Gas burner
JP5002148B2 (ja) * 2005-11-24 2012-08-15 株式会社東芝 半導体装置
JP4893303B2 (ja) * 2006-12-29 2012-03-07 株式会社デンソー 半導体装置
US8481368B2 (en) * 2008-03-31 2013-07-09 Alpha & Omega Semiconductor, Inc. Semiconductor package of a flipped MOSFET and its manufacturing method
JP2014029967A (ja) * 2012-07-31 2014-02-13 Toshiba Lighting & Technology Corp 半導体装置及びその製造方法
JP6114149B2 (ja) * 2013-09-05 2017-04-12 トヨタ自動車株式会社 半導体装置
JP6350364B2 (ja) 2015-04-01 2018-07-04 株式会社デンソー 接続構造体

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013123016A (ja) * 2011-12-12 2013-06-20 Denso Corp 半導体装置
CN105814681A (zh) * 2013-11-29 2016-07-27 株式会社神户制钢所 底板以及具备底板的半导体装置
CN105321936A (zh) * 2014-07-31 2016-02-10 富士电机株式会社 半导体装置及其制造方法

Also Published As

Publication number Publication date
JP6610590B2 (ja) 2019-11-27
TW201838122A (zh) 2018-10-16
KR102073579B1 (ko) 2020-02-05
KR20180106957A (ko) 2018-10-01
CN108630652A (zh) 2018-10-09
US10475727B2 (en) 2019-11-12
TWI676251B (zh) 2019-11-01
US20180277462A1 (en) 2018-09-27
EP3379572A1 (en) 2018-09-26
EP3379572B1 (en) 2019-12-18
JP2018157157A (ja) 2018-10-04

Similar Documents

Publication Publication Date Title
CN108630652B (zh) 半导体装置、用于半导体装置的制造方法以及电极板
US9831160B2 (en) Semiconductor device
JP6728518B2 (ja) 半導体装置および半導体モジュール
JP7156025B2 (ja) 半導体装置
JP5076549B2 (ja) 半導体装置
JP5733401B2 (ja) 半導体装置および半導体装置の製造方法
US20160204047A1 (en) Semiconductor device and method for manufacturing the same
JP5971310B2 (ja) 半導体装置の製造方法および半導体装置
JP5857361B2 (ja) 半導体装置
JP5732880B2 (ja) 半導体装置及びその製造方法
US11302670B2 (en) Semiconductor device including conductive post with offset
JP6619119B1 (ja) 半導体装置
US11552065B2 (en) Semiconductor device
JP5056105B2 (ja) 半導体装置およびその製造方法
JP7156172B2 (ja) 半導体装置
KR200478914Y1 (ko) 반도체 패키지
US20240021496A1 (en) Semiconductor device
CN116072644A (zh) 树脂密封型半导体装置以及树脂密封型半导体装置的制造方法
JP2022027162A (ja) 半導体装置
JP2023089457A (ja) 半導体装置の製造方法及び半導体装置
JP2023025936A (ja) 半導体装置の製造方法
JP2022132808A (ja) 半導体装置及び半導体装置の製造方法
JP2019153751A (ja) 半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20200413

Address after: Aichi Prefecture, Japan

Applicant after: DENSO Corp.

Address before: TOYOTA City, Aichi Prefecture, Japan

Applicant before: Toyota Motor Corp.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant