JP5733401B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP5733401B2 JP5733401B2 JP2013527923A JP2013527923A JP5733401B2 JP 5733401 B2 JP5733401 B2 JP 5733401B2 JP 2013527923 A JP2013527923 A JP 2013527923A JP 2013527923 A JP2013527923 A JP 2013527923A JP 5733401 B2 JP5733401 B2 JP 5733401B2
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- semiconductor device
- lead frame
- metal layer
- electronic component
- wire
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- 239000004065 semiconductor Substances 0.000 title claims description 82
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 48
- 239000002184 metal Substances 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 38
- 238000010586 diagram Methods 0.000 description 9
- 230000004048 modification Effects 0.000 description 9
- 238000012986 modification Methods 0.000 description 9
- 239000000919 ceramic Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000035882 stress Effects 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910016525 CuMo Inorganic materials 0.000 description 1
- 229910002549 Fe–Cu Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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Description
セラミック基板11は、その両面にそれぞれ所定形状の金属層からなる導電パターン12,13が接合形成された絶縁基板10であって、図示しないベース基材の上面に半田付けされたモジュール構造の半導体装置を構成している。ここでは、表面側の導電パターン12に、絶縁ゲート型バイポーラトランジスタ(Insulated Gate Bipolar Transistor:IGBT)を構成する半導体チップ(以下、IGBTチップという。)14とダイオードチップ15がそれぞれ半田層16,17によって所定の位置に実装され、配線部材として金属板18が配置される。この金属板18は、上述したようにIGBTチップ14、ダイオードチップ15の相互間および導電パターン12を電気的に接続するリードフレームとして、各チップ14,15からの発熱を吸収しつつ外部へ放熱するように、幅広に形成されている。
位置決め用枠体20は、導電パターン12上で、そこに搭載されたIGBTチップ14、ダイオードチップ15によって所定の位置に位置決めして配置される枠体(コマ)である。この位置決め用枠体20は、IGBTチップ14の図示左側で導電パターン12の範囲を確定する枠20a、IGBTチップ14の外周枠20b、ダイオードチップ15の外周枠20c、および外周枠20b,20cを接続する接続枠20dによって単一の閉領域を規定している。これにより、図11に示す金属板18の、導電パターン12上で配置されるべき位置(図中、想像線18iで示す。)が確定される。
(第1の実施の形態)
図1は、第1の実施の形態に係る半導体装置の一例を示す図であって、(A)は半導体装置の平面図、(B)はB−B線に沿って示す断面図である。
半田板28,29は、それぞれ電子部品23,24の電極面に対応する大きさを有し、かつ所定のスリット28s,29sが予め形成されている。そのため、スリット28s,29sを各電極面にボンディングされたワイヤ部材27の接着面と一致させることによって、半田板28,29の位置決めが可能となる。また、前述したように、これらの半田板28,29により電子部品23,24の電極面と接合されるリードフレーム22の接合部22a,22bの位置も、同様にワイヤ部材27によって決まる。
図3には、リードフレーム22の接合部22b近傍を拡大して示している。この接合部22bの下面側、すなわち電子部品24との接続面(裏面)側には、開口21の周縁に沿って下方に向かう突起部221が形成されている。この突起部221は、半田板29の厚さにほぼ等しく、かつ半田板29に形成されたスリット29s内に嵌り込む程度の大きさを有している。また、リードフレーム22の接合部22bにおける開口21は、その表面側に段部222が形成されている。ここでは、リードフレーム22の一方の接合部22bについて説明したが、他方の接合部22aにも同様の突起部221と段部222が形成されている。
同図(A)には、セラミック基板11の両面にそれぞれ所定形状の金属層からなる導電パターン12,13が接合形成された絶縁基板10と、接合材25,26により導電パターン12に接合される電子部品23,24を示している。ここで、全体を加熱炉などで加熱して接合材25,26を溶融することにより、絶縁基板10上の導電パターン12の所定位置に電子部品23,24を接合する第1の接合工程が実行される。
ここで、変形例として示すリードフレーム22Mでは、開口21がそれぞれ2つの分離して形成された長孔S1,S2に置き換えられている。一方の長孔S1は、リードフレーム22Mの接合部22aから接続部22jに繋がる起立部に跨って、他方の長孔S2は、接合部22bから接続部22jに繋がる起立部に跨って、それぞれリードフレーム22Mの長手方向に延長形成されている。その結果、2つの接合部22a,22bは、開口が形成されずに広い面積を有する接続部22jによって接続される。したがって、2つの電子部品23,24の発熱を受けたリードフレーム22Mは、広い面積の接続部22jから外部に熱を効率よく放出することが可能になる。
図6は、第2の実施の形態に係る半導体装置の一例を示す図であって、(A)は半導体装置の平面図、(B)はB−B線に沿って示す断面図である。また、図7は、第2の実施の形態に係る半導体装置の等価回路を示す図である。
図9は、第2の実施の形態に係る半導体装置に用いる位置決め用のワイヤ部材の変形例を示す断面図である。
図10は、第3の実施の形態に係る半導体装置に用いるリードフレームの一例を示す図であって、(A)はリードフレームの平面図、(B)はB−B線に沿って示す断面図、(C)は一部断面の拡大図である。
11 セラミック基板
12,13 導電パターン
21 開口
22,31,32,33,35 リードフレーム
23,24 電子部品
23a,23b IGBTチップ
24a,24b ダイオードチップ
25,26 接合材
27,341〜344,Wa1,Wc1,Wa2,Wc2 ワイヤ部材
28,29 半田板
28s,29s スリット
30a,30b 配線用ワイヤ
ha1,ha2,hb1〜hb5,hc1,hc2 段付丸孔
S1,S2,Sa1〜Sc1,Sa2〜Sc2,Sa3〜Sc3,Sa4〜Sc4 長孔
Claims (12)
- 金属層が形成された絶縁基板と、前記金属層上に搭載された電子部品とを含む半導体装置において、
前記電子部品同士、あるいは前記金属層と前記電子部品とにそれぞれボンディング位置から立ち上がるようにボンディングされたワイヤ部材と、
前記電子部品同士、あるいは前記金属層と前記電子部品との間を電気的にそれぞれ接続し、前記ワイヤ部材が挿通可能な開口が形成されたリードフレームと、
を備え、
前記ワイヤ部材は、前記ワイヤ部材の立ち上がった一部が前記開口に挿通する長さを有し、
前記開口に前記ワイヤ部材を挿通することによって前記絶縁基板上で前記リードフレームが位置決めされていることを特徴とする半導体装置。 - 前記リードフレームは、前記電子部品あるいは前記金属層と接触する少なくとも一対の接合部と、前記接合部からそれぞれ立ち上がる起立部と、前記起立部を介して前記接合部の間を接続する接続部とを有し、
前記開口は、前記接合部と前記起立部とに跨って前記リードフレームの長手方向に形成された長孔であることを特徴とする請求項1記載の半導体装置。 - 前記長孔は、前記接合部で前記リードフレームの幅方向に複数形成されていることを特徴とする請求項2記載の半導体装置。
- 前記リードフレームには、前記電子部品あるいは前記金属層と接触する接合部の下面側に、前記開口の周縁に沿って下方に向かう突起部が形成されていることを特徴とする請求項1記載の半導体装置。
- 前記ワイヤ部材は、300〜500μmの径を有するアルミニウム線あるいは銅線であることを特徴とする請求項1記載の半導体装置。
- 前記ワイヤ部材は、一端が前記電子部品あるいは前記金属層にボンディングされ、少なくとも前記開口から上方に突出するだけの長さを有していることを特徴とする請求項1記載の半導体装置。
- 前記金属層は、前記絶縁基板の両面に形成された導電パターンであることを特徴とする請求項1記載の半導体装置。
- 前記電子部品はIGBTあるいはダイオードを構成する半導体チップであって、
前記リードフレームによって前記IGBTと前記ダイオードとを互いに逆並列に接続するように構成されていることを特徴とする請求項1記載の半導体装置。 - 前記絶縁基板は、ベースの上面に半田接続され、
前記電子部品が前記ベースを介して放熱部材に熱的に接続されていることを特徴とする請求項1記載の半導体装置。 - 金属層が形成された絶縁基板と、前記金属層上に搭載された電子部品とを含む半導体装置の製造方法において、
ワイヤ部材を、前記電子部品同士、あるいは前記電子部品と前記金属層とにそれぞれボンディング位置から立ち上がるようにボンディングするワイヤボンディング工程と、
リードフレームに前記ワイヤ部材が挿通可能な開口が形成され、前記ワイヤ部材は、前記ワイヤ部材の立ち上がった一部が前記開口に挿通する長さを有し、前記開口に前記ワイヤ部材を挿通することによって、前記絶縁基板上に位置決めされた前記リードフレームにより、前記電子部品同士、あるいは前記電子部品と前記金属層との間を電気的に接続する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記ワイヤボンディング工程は、前記金属層に配線用ワイヤをボンディングする工程を含むことを特徴とする請求項10記載の半導体装置の製造方法。
- 前記リードフレームを接続する工程後に、前記電子部品、前記金属層、および前記リードフレームをエポキシ樹脂あるいはゲルによって封止する工程を含むことを特徴とする請求項10記載の半導体装置の製造方法。
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