JP2021044452A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2021044452A JP2021044452A JP2019166509A JP2019166509A JP2021044452A JP 2021044452 A JP2021044452 A JP 2021044452A JP 2019166509 A JP2019166509 A JP 2019166509A JP 2019166509 A JP2019166509 A JP 2019166509A JP 2021044452 A JP2021044452 A JP 2021044452A
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Abstract
Description
第1の実施の形態の半導体装置について図1及び図2を用いて説明する。図1は、第1の実施の形態の半導体装置を示す側面図であり、図2は、第1の実施の形態の半導体装置を示す平面図である。なお、図1は、封止部材については破線で表し、図2では、封止部材の図示を省略している。また、半導体装置50は、セラミック回路基板10等を収納するケースに関する記載を省略している。また、第1の実施の形態では、複数の回路板12、複数の半導体チップ20,21、複数のコンタクト部品30、複数のボンディングワイヤ35、複数の外部接続端子40に対して、それぞれ区別しない場合には、同じ符号を付して説明する。なお、これら以外の構成についても、複数あるものはそれぞれ区別することなく、同じ符号を付して同じ符号で説明する。
半導体装置50は、以下に示す製造工程(フローチャート)に沿って製造される。以下の各製造工程は必要に応じて人為的または製造装置により実行される。
第2の実施の形態では、第1の実施の形態のボンディングワイヤ15a〜15dの別の取り付けについて、図19及び図20を参照して説明する。図19は、第2の実施の形態の半導体装置のセラミック回路基板の要部の平面図である。図20は、第2の実施の形態の半導体装置のセラミック回路基板の要部の断面図である。なお、図19は、第1の実施の形態の半導体装置50の図15に示す箇所に対応するものである。図20は、図19における一点鎖線X−Xにおける断面図である。また、第2の実施の形態の半導体装置では、第1の実施の形態の半導体装置50と同じ構成には同じ符号を付して、それらの説明については省略する。
第3の実施の形態では、第1の実施の形態の半導体装置50におけるボンディングワイヤ15a〜15dを溝部14間にスティッチボンディングにより設ける場合について、図21を用いて説明する。図21は、第3の実施の形態の半導体装置のセラミック回路基板の要部の平面図である。なお、図21は、第1の実施の形態の半導体装置50の図15に示す箇所に対応するものである。また、図21では、広がったはんだ31の図示を省略している。また、第3の実施の形態の半導体装置では、第1の実施の形態の半導体装置50と同じ構成には同じ符号を付して、それらの説明については省略する。
11 絶縁板
12,12a,12b,12c,12d,12e 回路板
12b1 めっき膜
13 金属板
14,14a,14b,14c 溝部
15a,15b,15c,15d,15e,15f,35 ボンディングワイヤ
20,21 半導体チップ
20a,21a 配置領域
30 コンタクト部品
31 はんだ
40 外部接続端子
45 封止部材
50 半導体装置
60 基板位置決め治具
61 収納部
62 ガイドピン
70 部品位置決め治具
72,82 ガイド孔
73 素子ガイド部
74 コンタクトガイド部
80 押え治具
81 平板部
81a 主面
83 押圧部
Claims (18)
- おもて面に第1配置領域及び第2配置領域が間隙を挟んで前記間隙にそれぞれ平行に設定され、前記間隙に長手方向が前記平行の方向に沿って溝部が形成された回路板と前記回路板がおもて面に形成された絶縁板とを有する基板と、
前記第1配置領域に第1接合部材を介して設けられた第1半導体チップと、
前記第2配置領域に第2接合部材を介して設けられた第2半導体チップと、
平面視で前記間隙に前記溝部を前記長手方向に跨って設けられた塞ぎ止め部材と、
を有する半導体装置。 - 前記塞ぎ止め部材は、細線である、
請求項1に記載の半導体装置。 - 前記塞ぎ止め部材は、前記溝部の前記長手方向の長さより長い、
請求項2に記載の半導体装置。 - 前記塞ぎ止め部材は、前記溝部の幅よりも幅が細い、
請求項3に記載の半導体装置。 - 前記塞ぎ止め部材は、金属により構成されている、
請求項2乃至4のいずれかに記載の半導体装置。 - 前記塞ぎ止め部材は、前記溝部の前記長手方向を跨るように前記回路板にボンディングされている、
請求項2乃至5のいずれかに記載の半導体装置。 - 前記塞ぎ止め部材は、前記第1半導体チップ及び前記第2半導体チップのおもて面よりも下位であって、前記回路板のおもて面よりも上位に位置して設けられている、
請求項2乃至6のいずれかに記載の半導体装置。 - 前記溝部を跨ぐ前記塞ぎ止め部材が複数設けられている、
請求項2乃至7のいずれかに記載の半導体装置。 - 前記溝部は、前記長手方向が前記間隙の前記平行の方向に沿って一列に複数形成されている、
請求項2乃至8のいずれかに記載の半導体装置。 - 前記塞ぎ止め部材は、前記回路板上に前記平行の方向に沿って前記複数の溝部を跨いで設けられている、
請求項9に記載の半導体装置。 - 前記塞ぎ止め部材は、前記複数の溝部のそれぞれの間をボンディングして、それぞれの前記溝部を跨いでいる、
請求項10に記載の半導体装置。 - 前記回路板の前記第1半導体チップ及び前記第2半導体チップにそれぞれ隣接する領域のいずれかに、前記塞ぎ止め部材が形成されない流出領域が設けられている、
請求項1乃至11のいずれかに記載の半導体装置。 - 前記回路板は銅または銅合金により構成されている、
請求項1乃至12のいずれかに記載の半導体装置。 - 前記回路板は、少なくとも前記第1配置領域及び前記第2配置領域にめっき膜が形成されている、
請求項1乃至13のいずれかに記載の半導体装置。 - 前記めっき膜は、ニッケルまたはニッケル合金により構成されている、
請求項14に記載の半導体装置。 - 前記塞ぎ止め部材は、前記回路板よりはんだ濡れ性が低い金属により構成されている、
請求項1乃至15のいずれかに記載の半導体装置。 - 前記塞ぎ止め部材は、アルミニウム、ニッケル、鉄またはこれらのいずれかを含む合金により構成されている、
請求項13に記載の半導体装置。 - 前記塞ぎ止め部材は、アルミニウムまたはアルミニウム合金により構成されている、
請求項16に記載の半導体装置。
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