CN112490211A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN112490211A
CN112490211A CN202010892785.3A CN202010892785A CN112490211A CN 112490211 A CN112490211 A CN 112490211A CN 202010892785 A CN202010892785 A CN 202010892785A CN 112490211 A CN112490211 A CN 112490211A
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China
Prior art keywords
semiconductor device
circuit board
semiconductor
groove portion
solder
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Pending
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CN202010892785.3A
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English (en)
Inventor
万·阿札·宾·万·马特
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Publication of CN112490211A publication Critical patent/CN112490211A/zh
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Abstract

本发明提供一种在接近的半导体芯片的接合中，能够以不使半导体芯片错位的方式配置的半导体装置。半导体装置具有：半导体芯片(20、21)，其经由焊料(31)而设置在配置区域；以及键合线(15a～15d)，其在俯视下，在间隙(A)以沿长度方向横跨槽部(14)的方式设置。通过这样的键合线(15a～15d)，从而阻挡利用在半导体装置的制造过程中的回流焊接而熔融了的焊料(31)向配置区域的间隙(A)侧扩散。因此，防止扩散了的焊料(31)在间隙(A)结合，并且抑制半导体芯片(20、21)的错位。

Description

半导体装置
技术领域
本发明涉及一种半导体装置。
背景技术
包含IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极型晶体管)、功率MOSFET(Metal Oxide Semiconductor Field Effect Transistor：金属氧化物半导体场效应管)等半导体芯片的半导体装置例如用作功率转换装置。这样的半导体装置包括该半导体芯片、以及经由焊料而配置有半导体芯片的陶瓷电路基板。陶瓷电路基板具备绝缘板、以及形成在该绝缘板上的多个电路板。在多个电路板中的任一电路板都经由焊料而配置有半导体芯片。另外，在电路板的预定区域上经由焊料而设置有用于安装外部连接端子的筒状的触点部件。另外，有使用金属基底基板的半导体装置，该金属基底基板在熔敷有半导体芯片的位置的附近的电路板部分形成有槽部。该槽部被用作在电路板上配置半导体芯片时的定位。
现有技术文献
专利文献
专利文献1：日本特开2014-187179号公报
专利文献2：日本特开平1-293557公报
发明内容
技术问题
近年来，正在要求半导体装置的小型化、大容量化。因此，正在推进半导体芯片的装配密度的提高，缩小半导体芯片彼此的间隔。然而，存在如下情况：在接近的半导体芯片的半导体装置中，在将半导体芯片经由焊料而分别配置在隔着形成在电路板的槽部的一对配置区域并使其接合时，导致焊料扩散而从一对配置区域溢出。半导体芯片随着焊料的扩散而导致配置位置偏移。另外，也有因焊料的扩散的情形而导致半导体芯片彼此接触的情况。此外，如果已扩散的焊料遍及到槽部，则有可能在其中含有气孔。在该情况下，若导致半导体芯片一直错位到槽部上，则在半导体芯片的下部存在气孔。若存在气孔则导致半导体芯片的散热性等降低。
本发明是鉴于这点而做出的，其目的在于，提供一种在接近的半导体芯片的接合中，能够以不使半导体芯片错位的方式进行配置的半导体装置。
技术方案
根据本发明的一个观点，提供一种半导体装置，所述半导体装置具有：基板，其具有电路板以及在正面形成有所述电路板的绝缘板，所述电路板在正面隔着间隙而分别与所述间隙平行地设定有第一配置区域和第二配置区域，并且在所述间隙以长度方向沿所述平行的方向的方式形成槽部；第一半导体芯片，其经由第一接合材料而设置在所述第一配置区域；第二半导体芯片，其经由第二接合材料而设置在所述第二配置区域；以及阻挡部件，其在俯视下，在所述间隙沿所述长度方向横跨所述槽部而设置。
技术效果
根据公开的技术，能够提供抑制可靠性的降低的半导体装置，其能够抑制接合材料在邻接的半导体芯片之间的扩散，能够可靠地防止半导体芯片的错位。
附图说明
图1是示出第一实施方式的半导体装置的侧视图。
图2是示出第一实施方式的半导体装置的俯视图。
图3是示出第一实施方式的半导体装置的制造方法的流程的图。
图4是用于说明在第一实施方式的半导体装置的制造方法中所使用的陶瓷电路基板的俯视图。
图5是用于说明在第一实施方式的半导体装置的制造方法中所使用的陶瓷电路基板的截面图。
图6是用于说明第一实施方式的半导体装置的制造方法的、针对陶瓷电路基板的引线键合工序的俯视图。
图7是用于说明第一实施方式的半导体装置的制造方法的、在基板定位工具安装陶瓷电路基板的工序的俯视图。
图8是用于说明第一实施方式的半导体装置的制造方法的、在基板定位工具安装陶瓷电路基板的工序的截面图。
图9是用于说明第一实施方式的半导体装置的制造方法的、安装部件定位工具的工序的俯视图。
图10是用于说明第一实施方式的半导体装置的制造方法的、安装部件定位工具的工序的截面图。
图11是用于说明第一实施方式的半导体装置的制造方法的、利用部件定位工具而安装触点部件的工序的俯视图。
图12是用于说明第一实施方式的半导体装置的制造方法的、利用部件定位工具而安装触点部件的工序的截面图。
图13是用于说明第一实施方式的半导体装置的制造方法的、安装按压工具的工序的俯视图。
图14是用于说明第一实施方式的半导体装置的制造方法的、安装按压工具的工序的截面图。
图15是第一实施方式的半导体装置的陶瓷电路基板的主要部分的俯视图。
图16是第一实施方式的半导体装置的陶瓷电路基板的主要部分的截面图。
图17是参考例的半导体装置的陶瓷电路基板的主要部分的俯视图。
图18是第一实施方式的半导体装置的其他的陶瓷电路基板的主要部分的俯视图。
图19是第二实施方式的半导体装置的陶瓷电路基板的主要部分的俯视图。
图20是第二实施方式的半导体装置的陶瓷电路基板的主要部分的截面图。
图21是第二实施方式的半导体装置的其他的陶瓷电路基板的主要部分的俯视图。
图22是第三实施方式的半导体装置的陶瓷电路基板的主要部分的俯视图。
符号说明
10 陶瓷电路基板
11 绝缘板
12、12a、12b、12c、12d、12e 电路板
12b1 镀膜
13 金属板
14、14a、14b、14c 槽部
15a、15b、15c、15d、15e、15f、35 键合线
20、21 半导体芯片
20a、21a 配置区域
30 触点部件
31 焊料
40 外部连接端子
45 密封部件
50 半导体装置
60 基板定位工具
61 收纳部
62 导柱
70 部件定位工具
72、82 导孔
73 元件引导部
74 接头引导部
80 按压工具
81 平板部
81a 主面
83 按压部
具体实施方式
以下，参照附图，对实施方式进行说明。应予说明，在以下的说明中，“正面”和“上表面”是表示在图1的半导体装置50中，朝向上侧的面。同样地，“上”是表示在图1的半导体装置50中，上侧的方向。“背面”和“下表面”是表示在图1的半导体装置50中，朝向下侧的面。同样地，“下”是表示在图1的半导体装置50中，下侧的方向。根据需要，其他附图也表示同样的方向性。“正面”、“上表面”、“上”、“背面”、“下表面”、“下”、“侧面”仅仅是确定相对的位置关系的方便表达而已，并不限定本发明的技术思想。例如，“上”和“下”不一定表示相对于底面的铅直方向。即，“上”和“下”的方向不限于重力方向。
[第一实施方式]
利用图1和图2对第一实施方式的半导体装置进行说明。图1是示出第一实施方式的半导体装置的侧视图，图2是示出第一实施方式的半导体装置的俯视图。应予说明，利用虚线来表示密封部件，在图2中，省略密封部件的图示。另外，半导体装置50省略与收纳陶瓷电路基板10等的壳体相关的记载。另外，在第一实施方式中，针对多个电路板12、多个半导体芯片20、多个半导体芯片21、多个触点部件30、多个键合线35、以及多个外部连接端子40，在不分别进行区别的情况下，标注相同的符号而进行说明。应予说明，针对除此以外的构成，在具有多个并且不分别进行区别的情况下，标注相同符号而利用相同符号进行说明。
如图1和图2所示，半导体装置50具有陶瓷电路基板10(基板)、以及与陶瓷电路基板10的正面接合的半导体芯片20、21。半导体装置50具有与陶瓷电路基板10的正面接合的触点部件30。半导体芯片20、21和触点部件30经由焊料等接合材料(省略图示)而接合在陶瓷电路基板10的正面。另外，半导体装置50具有键合线35，该键合线35将陶瓷电路基板10的正面与半导体芯片20、21的主电极电连接。另外，在触点部件30压入而安装有外部连接端子40。此外，半导体装置50以使安装于触点部件30的外部连接端子40的前端部突出的方式，与陶瓷电路基板10的正面的半导体芯片20、21一起被密封部件45密封。
陶瓷电路基板10具有绝缘板11、形成在绝缘板11的正面的多个电路板12、以及形成在绝缘板11的背面的金属板13。绝缘板11由导热性优良的氧化铝、氮化铝、氮化硅等高导热性的陶瓷构成。多个电路板12(包括电路板12a～12e)由导电性优良的材质构成。作为这样的材质，例如，由铜或铜合金等构成。而且，为了提高耐腐蚀性，例如，可以对电路板12的表面进行利用镍或镍合金等的电镀处理等。作为镍合金，优选镍-磷合金、镍-硼合金等。金属板13由导热性优良的铝、铁、银、铜、或至少包括其中一种的合金等金属构成。另外，在金属板13的背面可以形成有散热板和/或冷却器(省略图示)。应予说明，绝缘板11在俯视下成为例如矩形。另外，金属板13在俯视下，成为面积比绝缘板11小且总面积比电路板12大的矩形。因此，陶瓷电路基板10成为例如矩形。
在电路板12适当地形成有槽部14。槽部14在电路板12的配置有半导体芯片20、21的配置区域的间隙具有长度方向与半导体芯片20、21(配置区域)平行地延伸而形成的半导体芯片20、21之间的槽部14a。另外，槽部14具有槽部14b，该槽部14b形成在配置有半导体芯片20、21的配置区域与配置有触点部件30等端子和/或电容器、电阻等电子部件的区域之间。此外，槽部14具有槽部14c，该槽部14c形成在配置有半导体芯片20、21的配置区域与接合有键合线35的区域之间。在俯视下，这样的(将槽部14a、14b、14c进行统称)槽部14在不与电路板12的端边接触的情况下独立地形成在电路板12的面内。另外，槽部14沿电路板12的厚度方向贯通电路板12而形成。这样的槽部14的宽度方向的长度是例如100μm以上且1.0mm以下，优选是400μm以上且500μm以下。应予说明，槽部14的长度方向的长度根据需要而任意地形成。后面会对槽部14进行详细说明。
此外，针对电路板12a～12e的槽部14，设置有键合线15a～15f作为阻挡部件。在半导体芯片20、21之间的槽部14a分别设置有阻挡部件。虽然在其他的槽部14b、14c也可以设置有阻挡部件，但是优选不设置。例如，若在槽部14b设置阻挡部件，则对触点部件30进行焊料接合时的焊接工具不能顺畅地配置。另外，若在槽部14c设置阻挡部件，则有可能导致在键合电气布线用的键合线35时干涉而成为阻碍。应予说明，在第一实施方式中示出针对两个半导体芯片20、21之间的槽部14a设置阻挡部件的情况。不限于该情况，也能够针对三个以上的半导体芯片之间分别设置槽部，并且能够针对各槽部与本实施方式同样地设置阻挡部件。
这样的键合线15a～15f是例如直径为125μm以上且400μm以下的细线。键合线15a～15f由例如铝、镍、铁或至少包括其中一种的合金等构成。特别地，键合线15a～15f优选的是焊料润湿性比电路板12a～12e的表面低的金属。例如，在电路板12a～12e的表面为铜或铜合金的情况下，键合线15a～15f可以由铝、镍、铁或至少包括其中一种的合金等构成。另外，例如，在电路板12a～12e的表面形成有镍或镍合金的情况下，键合线15a～15f可以由例如铝或铝合金等构成。应予说明，后面会对键合线15a～15f进行详细说明。
作为具有这样的构成的陶瓷电路基板10，能够使用例如DCB(Direct CopperBonding：直接铜键合衬底)基板、AMB(Active Metal Brazed：活性金属钎焊)基板。另外，也能够在陶瓷电路基板10的金属板13经由混入有金属氧化物的填料的硅等导热膏而安装如上所述的冷却器(省略图示)来提高散热性。该情况下的冷却器由例如导热性优良的铝、铁、银、铜或至少包括其中一种的合金等构成。另外，作为冷却器，能够适用散热片、或由多个散热片构成的散热器以及利用水冷的冷却装置等。
半导体芯片20包括由硅或碳化硅构成的例如IGBT、功率MOSFET等开关元件。这样的半导体芯片20例如在背面具备漏电极(或集电极)作为主电极，并且在正面具备栅电极以及源电极(或发射极)作为主电极。另外，半导体芯片21包括SBD(Schottky Barrier Diode：肖特基二极管)、以及FWD(Free Wheeling Diode：续流二极管)等二极管。这样的半导体芯片21在背面具备阴电极作为主电极，在正面具备阳电极作为主电极。上述的半导体芯片20、21的背面侧接合在预定的电路板(省略图示)上。应予说明，半导体芯片20、21经由焊料(省略图示)而接合在电路板12上。后面会对焊料进行说明。另外，虽然省略图示，但是可以使用同时具有IGBT与FWD的功能的RC(Reverse-Conducting：反向导通)-IGBT来代替半导体芯片20、21。另外，能够根据需要，配置例如引线框架、外部连接端子(销端子、触点部件等)、电子部件(热敏电阻、电流传感器)等来代替半导体芯片20、21。应予说明，这样的半导体芯片20、21的厚度是例如180μm以上且220μm以下，平均为200μm左右。
键合线35适当地电连接在半导体芯片20、21与电路板12之间、或多个半导体芯片20、21之间。这样的键合线35由导电性优良的材质构成。作为这样的材质，由例如金、银、铜、铝或至少包括其中一种的合金等构成。另外，键合线35的直径是例如110μm以上且200μm以下。其他的键合线35的直径是例如350μm以上且500μm以下。
密封部件45可以是例如硅胶。另外，密封部件45包括例如环氧树脂、酚醛树脂、马来酰亚胺树脂等热固化性树脂、以及含有热固化性树脂的填充材料。作为这样的密封部件45的一例，包括环氧树脂、以及作为填料而含于环氧树脂中的二氧化硅、氧化铝、氮化硼或氮化铝等填充材料。
接下来，利用表示各工序和各工具的图4～图14，按照图3所示的流程，对这样的半导体装置50的制造方法进行说明。图3是示出第一实施方式的半导体装置的制造方法的流程的图。图4是用于说明在第一实施方式的半导体装置的制造方法中所使用的陶瓷电路基板的俯视图。图5是用于说明在第一实施方式的半导体装置的制造方法中所使用的陶瓷电路基板的截面图。
图6是用于说明第一实施方式的半导体装置的制造方法的、针对陶瓷电路基板的引线键合工序的俯视图。图7是用于说明第一实施方式的半导体装置的制造方法的、在基板定位工具安装陶瓷电路基板的工序的俯视图。图8是用于说明第一实施方式的半导体装置的制造方法的、在基板定位工具安装陶瓷电路基板的工序的截面图。
图9是用于说明第一实施方式的半导体装置的制造方法的、安装部件定位工具的工序的俯视图。图10是用于说明第一实施方式的半导体装置的制造方法的、安装部件定位工具的工序的截面图。图11是用于说明第一实施方式的半导体装置的制造方法的、利用部件定位工具来安装触点部件的工序的俯视图。图12是用于说明第一实施方式的半导体装置的制造方法的、利用部件定位工具来安装触点部件的工序的截面图。图13是用于说明第一实施方式的半导体装置的制造方法的、安装按压工具的工序的俯视图。图14是用于说明第一实施方式的半导体装置的制造方法的、安装按压工具的工序的截面图。应予说明，图5、8、10、12、14是图4、7、9、11、13中的单点划线X-X的截面图。
半导体装置50按照以下所示的制造工序(流程)而制造。以下的各制造工序根据需要而被人为地执行或被制造装置执行。
[步骤S10]准备半导体芯片20、21、陶瓷电路基板10、以及触点部件30。不限于这些部件，预先准备在半导体装置50的制造中所需的部件等。应予说明，如图4和图5所示，陶瓷电路基板10具有绝缘板11、形成在绝缘板11的正面的多个电路板12、以及形成在绝缘板11的背面的金属板13。应予说明，在图4中，标注于多个电路板12的矩形的虚线表示之后的半导体芯片20、21的配置区域。针对这样的配置区域而形成有槽部14。例如，在电路板12a～12d，隔着间隙而与该间隙平行地分别设定有一对配置区域20a、21a。在这样的间隙形成有长度方向与间隙平行的槽部14。槽部14作为之后在配置区域20a、21a涂覆焊料时的校准位置而起作用。
[步骤S11]如图6所示，在俯视下，在陶瓷电路基板10的电路板12中的电路板12a～12d，将槽部14形成在配置区域20a、21a的间隙，并且横跨槽部14的长度方向而分别设置键合线15a～15d。应予说明，如上所述，在半导体芯片20、21之间的槽部14分别设置有键合线15a～15d。另外，此时，在电路板12e，也将槽部14a形成在半导体芯片20的配置区域20a的间隙，并且横跨槽部14a的长度方向而分别设置键合线15e、15f。虽然在其他的槽部14b、14c也可以设置有键合线，但是优选不设置键合线。
[步骤S12]在陶瓷电路基板10的电路板12上的半导体芯片20、21和触点部件30的设置区域分别涂覆焊料31(参照图7)。应予说明，这样的陶瓷电路基板10的电路板12的焊料31例如能够通过分液器来涂覆。也可以将焊片(省略图示)配置在各个设置区域。应予说明，图7所示的焊料31以四边形来表示与半导体芯片20、21对应的焊料，以圆形来表示与触点部件30对应的焊料。
另外，上述焊料31由无铅焊料构成，该无铅焊料例如以由锡-银-铜形成的合金、由锡-锌-铋形成的合金、由锡-铜形成的合金、由锡-银-铟-铋形成的合金中的至少任一合金为主要成分。除此之外，焊料31包括具有去除电路板12上的氧化物的作用的焊剂。焊剂能够含有例如环氧树脂、羧酸、松香树脂、活性剂、以及溶剂，而且能够根据需要而含有其他成分。此外，这样的焊料31可以包括镍、锗、钴或硅等添加物。
应予说明，可以切换步骤S11与步骤S12的工序的执行顺序。若首先进行步骤S12，则能够无妨碍地将焊料31涂覆在键合线15a～15f。此时的焊料31的涂覆能够通过例如丝网印刷而进行。
[步骤S13]如图7和图8所示，如此地设置键合线15a～15f，将涂覆了焊料31的陶瓷电路基板10安装于基板定位工具60。基板定位工具60在俯视下成为矩形，并且在中心部形成有收纳部61，该收纳部61构成为收纳陶瓷电路基板10的凹状。另外，基板定位工具60在上表面的四角分别形成有导柱62。另外，基板定位工具60由复合陶瓷材料、炭等耐热性优良的材质构成。陶瓷电路基板10以使电路板12为正面的方式载置在这样的基板定位工具60的收纳部61。
而且，如图9和图10所示，针对基板定位工具60而安装部件定位工具70。另外，部件定位工具70也由复合陶瓷材料、炭等耐热性优良的材质构成。部件定位工具70成为俯视为矩形的板状。部件定位工具70在四角分别形成有导孔72。将各导孔72插通基板定位工具60的各导柱62，从而将部件定位工具70安装于基板定位工具60。另外，部件定位工具70以元件引导部73和接头引导部74敞开的方式构成。如上所述，若部件定位工具70安装于基板定位工具60，则元件引导部73和接头引导部74与陶瓷电路基板10的触点部件30和半导体芯片20、21各自的设置区域(被涂覆的焊料31)分别对置。应予说明，元件引导部73和接头引导部74比半导体芯片20、21和触点部件30的大小大一圈而形成。
[步骤S14]如图11和图12所示，在部件定位工具70的元件引导部73和接头引导部74，在步骤S12中涂覆的焊料31上，利用装配装置而分别安装半导体芯片20、21和触点部件30。
[步骤S15]如图13和图14所示，在部件定位工具70上安装按压工具80。另外，按压工具80也由复合陶瓷材料、炭等耐热性优良的材质构成。按压工具80具备平板部81、导孔82、以及按压部83。如图13所示，平板部81在俯视下成为与部件定位工具70相对应的形状。导孔82形成在平板部81的四角。按压部83以与部件定位工具70的接头引导部74对应的方式形成在平板部81的靠部件定位工具70侧的主面81a。若将导孔82插通在导柱62而将这样的按压工具80安装在部件定位工具70上，则按压部83进入部件定位工具70的接头引导部74，并与触点部件30抵接。
[步骤S16]在步骤S15中安装了按压工具80的状态下将陶瓷电路基板10搬入到回流炉，对炉内进行减压而以回流处理温度进行加热处理(回流焊接工序)。回流处理温度是例如250℃以上且300℃以下。由此，焊料31各自熔融而将各电路板12与半导体芯片20、21和触点部件30电连接或机械连接。然后，通过使熔融的焊料31凝固，从而将半导体芯片20、21和触点部件30接合在各电路板12。应予说明，后面会对如此地接合到陶瓷电路基板10的电路板12的半导体芯片20、21和焊料31的状态进行说明。
[步骤S17]依次拆下按压工具80和部件定位工具70，并从基板定位工具60拆下在各电路板12接合有半导体芯片20、21和触点部件30的陶瓷电路基板10。然后，利用未图示的超声波键合工具，通过键合线将陶瓷电路基板10的各电路板12的预定区域与半导体芯片20、21电连接。另外，在如此地连接键合线35后，将外部连接端子(省略图示)压入各触点部件30。
[步骤S18]将在各电路板12接合有半导体芯片20、21和触点部件30并且利用键合线35进行了电连接的陶瓷电路基板10安装于壳体，并利用密封部件45进行密封。由此，制造出图1和图2所示的半导体装置50。
接下来，利用图15和图16对上述半导体装置50的制造方法的步骤S16的利用回流焊接进行的陶瓷电路基板10的电路板12上的半导体芯片20、21和焊料31进行说明。图15是第一实施方式的半导体装置的陶瓷电路基板的主要部分的俯视图，图16是第一实施方式的半导体装置的陶瓷电路基板的主要部分的截面图。应予说明，图16的(A)示出图15的单点划线Y-Y的截面图，图16的(B)示出图15的单点划线X-X的截面图。另外，在图15和图16中，示出陶瓷电路基板10的电路板12a～12d以及其周边。
在电路板12a～12d经由焊料31配置半导体芯片20、21，从而进行回流焊接(步骤S16)。于是，焊料31熔融而开始扩散到半导体芯片20、21的配置区域的外部。例如，如图15所示，在电路板12b，配置有半导体芯片20、21的焊料31熔融，而向半导体芯片20、21的间隙A侧流出。此时，在半导体芯片20、21的间隙A设置有键合线15b。因此，即使配置有半导体芯片20、21的焊料31熔融而向半导体芯片20、21的间隙A侧流出，该流动也被键合线15b阻挡。具体而言，如图16的(A)所示，在形成有镀膜12b1的电路板12b的、不形成槽部14的位置，半导体芯片20、21的正下方的熔融的焊料31被键合线15b阻挡。因此，防止半导体芯片20、21的焊料31彼此结合。此外，此时，伴随着如此地抑制了在不形成槽部14的部位处的焊料31的结合，在形成有电路板12b的槽部14的部位，如图16的(B)所示，能够抑制焊料31向槽部14流入。当然，在除电路板12b以外的电路板12a、12c～12d也能够利用键合线15a、15c、15d而同样地抑制焊料31的结合等。通过使如此熔融的焊料31固化，从而使半导体芯片20、21分别与电路板12a～12d接合。应予说明，此时的焊料31的厚度是100μm以上且200μm以下。
另外，为了在槽部14的宽度方向上，利用直径为125μm以上且400μm以下的键合线15a～15d可靠地阻挡焊料31的扩散，优选键合线15a～15d位于比半导体芯片20、21的正面更靠下方的位置，且位于比电路板12a～12d的正面更靠上方的位置。
在陶瓷电路基板10的电路板12a～12d，在半导体芯片20、21的间隙A，键合线15a～15d沿该槽部14的长度方向横跨槽部14而设置。另一方面，在分别与电路板12a～12d的半导体芯片20、21邻接的区域，优选都设置不形成键合线15a～15d的流出区域B(图15中的虚线的区域)。如上所述，熔融而扩散的焊料31若被键合线15a～15d阻挡，则会扩散到不设置键合线15a～15d的其他区域。假设，若在半导体芯片20、21的四个方向设置键合线，则导致熔融了的焊料31的所有扩散目的地都被阻挡。因此，也有因熔融了的焊料31会越过设置在半导体芯片20、21的四个方向的键合线中的任一键合线而导致产生焊料31的结合的情况。因此，有必要在分别与电路板12a～12d的半导体芯片20、21邻接的区域都设置不形成键合线15a～15d的流出区域B。由此，键合线15a～15d是阻挡熔融了的焊料31的扩散的部件。因此，只要是能够阻挡的部件，也能够使用例如引线框架等其他部件来代替键合线15a～15d。
在此，利用图17，对不形成键合线15a～15d的情况下的半导体装置进行说明。图17是参考例的半导体装置的陶瓷电路基板的主要部分的俯视图。应予说明，参考例的半导体装置成为除键合线15a～15d以外都与半导体装置50相同的构成，标注相同的符号，并省略其说明。另外，图17是对应于在图15中不设置键合线15a～15d的情况的图示。根据图17，由于不设置键合线15a～15d，所以若进行图3的回流焊接(步骤S16)，则焊料31向半导体芯片20、21的四个方向扩散。因此，例如，电路板12a的(正中间)半导体芯片20和电路板12c的半导体芯片20因已扩散的焊料31而在其位置旋转，或产生错位。旋转后的半导体芯片20的一部分经由焊料31而位于槽部14上。在焊料31填充于槽部14内的情况下，有可能在槽部14内产生气孔。若如此地产生气孔则导致对半导体芯片20的散热性降低。另外，在电路板12a(左侧和右侧)、12b，导致焊料31在间隙A结合。在这样的情况下，会导致产生导电不良。
上述半导体装置50具有陶瓷电路基板10，该陶瓷电路基板10具有：电路板12a～12d，其在正面隔着间隙A而分别与间隙A平行地设定有配置区域20a、21a，并且在间隙A沿平行于间隙A的长度方向的方向形成有槽部14；以及绝缘板11，其在正面形成有电路板12a～12d。另外，半导体装置50具有：半导体芯片20、21，其经由焊料31而设置在配置区域20a、21a；以及键合线15a～15d，其在俯视下，在间隙A沿长度方向横跨槽部14而设置。通过这样的键合线15a～15d，从而阻挡利用半导体装置50的制造过程中的回流焊接而熔融的焊料31向配置区域20a、21a的间隙A侧的扩散。因此，防止已扩散的焊料31在间隙A结合，并且抑制半导体芯片20、21的错位。随此，抑制半导体芯片20、21的散热性的降低以及导电不良的产生，抑制半导体装置50的可靠性降低。
应予说明，在第一实施方式中，举例说明相对于配置区域20a、21a的间隙A而形成两个槽部14的情况。槽部14不限于两个，也可以是一个，或者根据间隙A的空间也可以是三个以上。在此，利用图18，对形成一个槽部14的情况进行说明。图18是第一实施方式的半导体装置的其他的陶瓷电路基板的主要部分的俯视图。在图18中示出在半导体装置50中，在每个配置区域20a、21a的间隙A，沿间隙A的长度方向仅设置了一个槽部14的情况。应予说明，在图18中，省略了已扩散的焊料31的图示。根据图18，在同一电路板12a，键合线15a横跨三个槽部14而设置。另外，在同一电路板12b～12d中，键合线15b～15d分别横跨槽部14而设置。在该情况下，也起到与半导体装置50同样的效果。
[第二实施方式]
在第二实施方式中，参照图19～图21，对第一实施方式的键合线15a～15d的其他安装进行说明。图19是第二实施方式的半导体装置的陶瓷电路基板的主要部分的俯视图。图20是第二实施方式的半导体装置的陶瓷电路基板的主要部分的截面图。图21是第二实施方式的半导体装置的其他的陶瓷电路基板的主要部分的俯视图。应予说明，图19是对应于第一实施方式的半导体装置50的图15所示的部位的图示。图20是图19中的单点划线X-X的截面图。图21是对应于第一实施方式的半导体装置50在图18所示的部位的图。另外，在第二实施方式的半导体装置中，对与第一实施方式的半导体装置50相同的构成标注相同的符号，并省略这些说明。
如图19和图20所示，在第二实施方式的半导体装置中，横跨槽部14的键合线15a～15d不是一条而是两条。应予说明，根据间隙A的空间，也可以是三条以上。另外，例如，如图20所示，在俯视下，横跨电路板12b的槽部14而配置的一对键合线15b与槽部14和电路板12b之间的边界相同，或从边界进入到电路板12b侧。此时，进入的宽度小于键合线15b的直径的50％。通过如此地使多条键合线15b横跨槽部14，从而能够更加可靠地阻挡熔融了的焊料31的扩散。另外，如图21所示，也可以利用多个(在图21中为两条)键合线15b～15d横跨一个槽部14。在该情况下，键合线15b～15d与图19和图20同样地横跨槽部14，也能够更加可靠地阻挡熔融了的焊料31的扩散。因此，不限于图15和图18的情况，也可以如图19那样地利用多个键合线15a～15d横跨多个槽部14。另外，也可以如图21那样地利用多个键合线15b～15d横跨各个槽部14。
[第三实施方式]
在第三实施方式中，利用图22，对在槽部14间通过自动点焊设置第一实施方式的半导体装置50中的键合线15a～15d的情况进行说明。图22是第三实施方式的半导体装置的陶瓷电路基板的主要部分的俯视图。应予说明，图22是对应于第一实施方式的半导体装置50的图15所示的部位的图示。另外，在图22中，省略已扩散的焊料31的图示。另外，在第三实施方式的半导体装置中，对与第一实施方式的半导体装置50相同的构成标注相同的符号，并省略这些说明。
如图22所示，在第三实施方式的半导体装置中，键合线15a～15d相对于电路板12a～12d在多个槽部14各自之间自动点焊，横跨各槽部14而设置。通过如此地在多个槽部14之间将键合线15a～15d进行自动点焊而横跨槽部14，从而能够更加可靠地阻挡熔融了的焊料31的扩散。

Claims (18)

1.一种半导体装置，其特征在于，具有：
基板，其具有电路板以及在正面形成有所述电路板的绝缘板，所述电路板在正面隔着间隙而分别与所述间隙平行地设定有第一配置区域和第二配置区域，并且在所述间隙以长度方向沿所述平行的方向的方式形成有槽部；
第一半导体芯片，其经由第一接合材料而设置在所述第一配置区域；
第二半导体芯片，其经由第二接合材料而设置在所述第二配置区域；以及
阻挡部件，其在俯视下，在所述间隙以沿所述长度方向横跨所述槽部的方式设置。
2.根据权利要求1所述的半导体装置，其特征在于，
所述阻挡部件是细线。
3.根据权利要求2所述的半导体装置，其特征在于，
所述阻挡部件的长度比所述槽部的所述长度方向的长度长。
4.根据权利要求3所述的半导体装置，其特征在于，
所述阻挡部件的宽度比所述槽部的宽度小。
5.根据权利要求2至4中任一项所述的半导体装置，其特征在于，
所述阻挡部件由金属构成。
6.根据权利要求2所述的半导体装置，其特征在于，
所述阻挡部件以横跨所述槽部的所述长度方向的方式键合在所述电路板。
7.根据权利要求2所述的半导体装置，其特征在于，
所述阻挡部件被设置为，位于比所述第一半导体芯片和所述第二半导体芯片的正面更靠下方的位置，并且位于比所述电路板的正面更靠上方的位置。
8.根据权利要求2所述的半导体装置，其特征在于，
设置多个横跨所述槽部的所述阻挡部件。
9.根据权利要求2所述的半导体装置，其特征在于，
所述槽部以使所述长度方向沿所述间隙的所述平行的方向的方式沿一列而形成有多个。
10.根据权利要求9所述的半导体装置，其特征在于，
所述阻挡部件在所述电路板上，以沿所述平行的方向横跨所述多个槽部的方式设置。
11.根据权利要求10所述的半导体装置，其特征在于，
所述阻挡部件键合在所述多个槽部的彼此之间，并且横跨各个所述槽部。
12.根据权利要求1所述的半导体装置，其特征在于，
在与所述电路板的所述第一半导体芯片和所述第二半导体芯片分别邻接的区域，都设置有不形成所述阻挡部件的流出区域。
13.根据权利要求1所述的半导体装置，其特征在于，
所述电路板由铜或铜合金构成。
14.根据权利要求1所述的半导体装置，其特征在于，
所述电路板至少在所述第一配置区域和所述第二配置区域形成有镀膜。
15.根据权利要求14所述的半导体装置，其特征在于，
所述镀膜由镍或镍合金构成。
16.根据权利要求1所述的半导体装置，其特征在于，
所述阻挡部件由焊料润湿性比所述电路板低的金属构成。
17.根据权利要求13所述的半导体装置，其特征在于，
所述阻挡部件由铝、镍、铁或包括这些金属中的任意金属的合金构成。
18.根据权利要求16所述的半导体装置，其特征在于，
所述阻挡部件由铝或铝合金构成。
CN202010892785.3A 2019-09-12 2020-08-31 半导体装置 Pending CN112490211A (zh)

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JPH07120680B2 (ja) 1988-05-20 1995-12-20 三菱電機株式会社 半導体装置
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