WO2013021726A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2013021726A1
WO2013021726A1 PCT/JP2012/065224 JP2012065224W WO2013021726A1 WO 2013021726 A1 WO2013021726 A1 WO 2013021726A1 JP 2012065224 W JP2012065224 W JP 2012065224W WO 2013021726 A1 WO2013021726 A1 WO 2013021726A1
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Prior art keywords
lead frame
semiconductor device
conductive pattern
wire
insulating substrate
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PCT/JP2012/065224
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English (en)
French (fr)
Inventor
伸 征矢野
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富士電機株式会社
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Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to US14/118,112 priority Critical patent/US9076782B2/en
Priority to CN201280023267.1A priority patent/CN103534796B/zh
Priority to EP12822675.0A priority patent/EP2698817B1/en
Priority to JP2013527923A priority patent/JP5733401B2/ja
Publication of WO2013021726A1 publication Critical patent/WO2013021726A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • solder layer When the solder layer extends to the end of the metal layer, a large stress is applied to the insulating substrate near the end of the metal layer when the entire semiconductor device is heated by the heat generated by the electronic component. Therefore, cracks may occur from the periphery of the solder layer, and the electrical connection may be impaired. Further, if the solder layer expands to the position where other electronic components are arranged, the bonding state of the other electronic components may be affected.
  • FIG. 11A and 11B are diagrams illustrating an example of a conventional semiconductor device, in which FIG. 11A is a plan view of the semiconductor device, and FIG. 11B is a cross-sectional view taken along line BB.
  • the ceramic substrate 11 is an insulating substrate 10 having conductive patterns 12 and 13 made of metal layers each having a predetermined shape bonded on both surfaces thereof, and is a semiconductor device having a module structure soldered to the upper surface of a base substrate (not shown). Is configured.
  • a semiconductor chip (hereinafter referred to as an IGBT chip) 14 and a diode chip 15 constituting an insulated gate bipolar transistor (IGBT) are formed on the conductive pattern 12 on the surface side by solder layers 16 and 17, respectively.
  • IGBT chip semiconductor chip
  • IGBT insulated gate bipolar transistor
  • the present invention has been made in view of the above points, and assures the life of the solder joining the lead frame having a large current capacity and the heat dissipation from the lead frame, and at the same time, reliability and assembly associated with downsizing.
  • An object of the present invention is to provide a semiconductor device with improved performance and a method for manufacturing the same.
  • FIG. 5A is a plan view of the semiconductor device
  • FIG. 5B is a cross-sectional view taken along line BB.
  • FIG. 5A is a plan view of the semiconductor device
  • FIG. 5B is a cross-sectional view taken along line BB.
  • FIG. 5A is a plan view of the lead frame
  • FIG. 5B is a cross-sectional view taken along line BB.
  • FIG. 5A is a plan view of the lead frame
  • FIG. 5B is a cross-sectional view taken along line BB.
  • FIG. 5A is a plan view of the lead frame
  • FIG. 5B is a cross-sectional view taken along line BB.
  • a rectangular lead frame 22 having an opening 21 In this semiconductor device, electronic components 23 and 24 on an insulating substrate (not shown) on which a metal layer to be a conductive pattern 12 is formed are electrically connected by a rectangular lead frame 22 having an opening 21. It is comprised as follows.
  • the lead frame 22 includes joint portions 22a and 22b having a size corresponding to the electrode surfaces of the electronic components 23 and 24 at the left and right ends. As shown in FIG.
  • the electronic components 23 and 24 are electrically connected to each other via upright portions each having a predetermined height.
  • the opening 21 of the lead frame 22 is formed through the lead frame 22 as a long hole having a predetermined length in a length direction from one joining portion 22a to the other joining portion 22b. ing.
  • the lead frame 22 can be positioned in a state in which the protrusions 221 are in direct contact with the electrode surfaces of the electronic components 23 and 24, respectively. Therefore, the lead frame 22 of the semiconductor device can be positioned not only in the front-rear and left-right directions by the wire member 27 but also reliably in the horizontal direction (up-down direction). Therefore, the thickness of the bonding layer formed by the solder plates 28 and 29 is made uniform, and the heat generated by the electronic components 23 and 24 can be efficiently discharged to the outside.
  • FIG. 4 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment.
  • the insulating substrate 10 in which conductive patterns 12 and 13 made of metal layers of a predetermined shape are bonded to both surfaces of the ceramic substrate 11 and bonded to the conductive pattern 12 by bonding materials 25 and 26, respectively.
  • Electronic components 23 and 24 are shown.
  • the first bonding step is performed in which the electronic components 23 and 24 are bonded to predetermined positions of the conductive pattern 12 on the insulating substrate 10 by melting the bonding materials 25 and 26 by heating the whole with a heating furnace or the like. Is done.
  • the wire member 27 is ultrasonically bonded.
  • each end of the positioning wire member 27 having a predetermined diameter and length is bonded to a predetermined position on the main surface of the electronic components 23 and 24 to which the lead frame 22 is bonded.
  • the insulating substrate 10 is fixed in the base, and the electronic components 23 and 24, the conductive pattern 12 and the lead frame 22 are sealed with epoxy resin or gel to complete the semiconductor device.
  • FIG. 6A and 6B are diagrams illustrating an example of a semiconductor device according to the second embodiment, in which FIG. 6A is a plan view of the semiconductor device and FIG. 6B is a cross-sectional view taken along line BB.
  • FIG. 7 is a diagram showing an equivalent circuit of the semiconductor device according to the second embodiment.
  • conductive patterns 12a to 12e divided into five are arranged on the ceramic substrate 11.
  • the IGBT chip 23a and the diode chip 24a mounted on the conductive pattern 12a constitute an IGBT 41a and a diode 42a connected to the positive side (P) DC terminal 43 shown in FIG.
  • the gate terminal G1 of the IGBT 41a is connected to the conductive pattern 12b from the IGBT chip 23a by the wiring wire 30a.
  • the surface electrodes of the IGBT chip 23 a and the diode chip 24 a are electrically connected to the conductive pattern 12 c constituting the output terminal (U terminal) 45 by the first lead frame 31.
  • the IGBT chip 23b and the diode chip 24b constituting the IGBT 41b and the diode 42b are mounted, and the surface electrodes thereof are the conductive pattern 12e constituting the negative (N) DC terminal 44 and the second lead. It is electrically connected by the frame 32.
  • the gate terminal G2 of the IGBT 41b is connected to the conductive pattern 12d by the wiring wire 30b from the IGBT chip 23b.
  • the lead frame 31 has three joint portions 31a, 31b, and 31c as shown in FIG. Further, in each of the joint portions 31a, 31b, and 31c, three elongated holes Sa1 to Sc1, Sa2 to Sc2, Sa3 to Sc3, and Sa4 to Sc4 are respectively suspended in parallel with the width direction of the lead frame 31. They are arranged at equal intervals. Of these long holes Sa1 to Sc1, Sa2 to Sc2, Sa3 to Sc3, and Sa4 to Sc4, positioning for connecting the respective surface electrodes of the diode chip 24a and the IGBT chip 23a is performed at each outer position. Wire members Wa1, Wc1 and positioning wire members Wa2, Wc2 for connecting the surface electrode of the IGBT chip 23a and the conductive pattern 12c are bonded. The same applies to the lead frame 32.
  • each of the wire members 341 to 344 is bonded to a predetermined position of the diode chip 24a, the IGBT chip 23a, and the conductive pattern 12c.
  • the wire members 341 to 344 may be formed on the insulating substrate 10 of the lead frame 33. Therefore, there is an advantage that the wire member itself can be used without waste.
  • stepped round holes ha1, ha2, hb1 to hb5, and hc1, hc2 are formed through the joint portions 35a to 35c in place of the long holes of the lead frame 3 shown in FIG. .
  • a protruding portion 351 directed downward is formed on the back side (joining surface side) of the stepped circular hole ha2.
  • a step portion 352 is formed on the front side of the stepped round hole ha2.
  • the height H of the protrusion 351 corresponds to the thickness of a solder plate used as a bonding material.
  • SYMBOLS 10 Insulating substrate 11 Ceramic substrate 12, 13 Conductive pattern 21 Opening 22, 31, 32, 33, 35 Lead frame 23, 24 Electronic component 23a, 23b IGBT chip 24a, 24b Diode chip 25, 26 Bonding material 27, 341 to 344 Wa1, Wc1, Wa2, Wc2 Wire member 28, 29 Solder plate 28s, 29s Slit 30a, 30b Wire for wiring ha1, ha2, hb1 to hb5, hc1, hc2 Stepped round hole S1, S2, Sa1 to Sc1, Sa2 to Sc2 , Sa3 to Sc3, Sa4 to Sc4 long hole

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

　大電流容量のリードフレームを接合している半田の寿命やリードフレームからの放熱性を確保し、小型化にともなう信頼性と組み立て性を向上した半導体装置である。　半導体装置は矩形形状のリードフレーム（２２）により導電パターン（１２）となる金属層が形成された絶縁基板上の電子部品（２３，２４）の間が電気的に接続される。その際、リードフレーム（２２）を貫通して形成された開口（２１）に電子部品（２３，２４）に跨って配置されたワイヤ部材（２７）を挿通することによって、リードフレーム（２２）を正確に位置決めすることができる。各電子部品（２３，２４）の電極面とリードフレーム（２２）の接合部（２２ａ，２２ｂ）との間には、それぞれ半田板（２８，２９）が挟み込まれ、後のリフロー工程で溶融される。半田板（２８，２９）には、リードフレーム（２２）の開口（２１）の幅に対応する大きさのスリット（２８ｓ，２９ｓ）が形成されている。

Description

半導体装置および半導体装置の製造方法
　本発明は、金属層を形成した絶縁基板上に複数の電子部品を搭載したモジュール構造の半導体装置および半導体装置の製造方法に関し、とくに絶縁基板の上に半導体チップなどの電子部品同士あるいは金属層と電子部品との間を電気的に接続することにより構成される半導体装置および半導体装置の製造方法に関する。
　小型で大電流の電子部品を搭載した構造の半導体装置には、絶縁基板上の金属層（導電パターン）に半田層を介して半導体チップが固着されるものがある。この半導体装置では、絶縁基板に形成された金属層に電子部品を搭載する際に、半田層が金属層上で周辺に向けて流動して金属層の端部まで拡がってしまうおそれがあり、さらに金属層に搭載されている他の電子部品の配置位置まで拡がることもあった。
　半田層が金属層の端部まで拡がると、電子部品の発熱によって半導体装置全体が加熱されたときに、金属層の端部付近の絶縁基板に大きな応力がかかる。そのため、半田層の周辺からクラックが発生して、電気的接続が損なわれるおそれがあった。また、半田層が他の電子部品の配置位置まで拡がると、他の電子部品の接合状態にも影響を与えるおそれがある。
　そこで、小型で大電流の電子部品を搭載した半導体装置では、配線部材として従来のアルミニウム線や銅線によるワイヤボンディングなどに代えて、金属板によるリードフレームを使用することで、電流容量を確保するとともに、電子部品の発熱を吸収しつつ外部への放熱性を高める冷却構造を実現できる。リードフレームは、たとえばその両端側で電子部品、たとえば半導体チップの電極と絶縁基板上に形成された導電パターンとにそれぞれ半田付けによって接続される。これにより、半導体チップ相互間や導電パターンとの電気的な接続が確保されると同時に、リードフレーム自体が半導体チップからの熱を外部に放熱する機能を有することになる。こうしたリードフレームは、一般に銅板、あるいは銅合金（Ｃｕ－Ｆｅ－Ｃｕ、ＡＬ－Ｆｅ、ＣｕＭｏ）などによって構成される。
　図１１は、従来の半導体装置の一例を示す図であって、（Ａ）は半導体装置の平面図、（Ｂ）はＢ－Ｂ線に沿って示す断面図である。
　セラミック基板１１は、その両面にそれぞれ所定形状の金属層からなる導電パターン１２，１３が接合形成された絶縁基板１０であって、図示しないベース基材の上面に半田付けされたモジュール構造の半導体装置を構成している。ここでは、表面側の導電パターン１２に、絶縁ゲート型バイポーラトランジスタ（Insulated Gate Bipolar Transistor：ＩＧＢＴ）を構成する半導体チップ（以下、ＩＧＢＴチップという。）１４とダイオードチップ１５がそれぞれ半田層１６，１７によって所定の位置に実装され、配線部材として金属板１８が配置される。この金属板１８は、上述したようにＩＧＢＴチップ１４、ダイオードチップ１５の相互間および導電パターン１２を電気的に接続するリードフレームとして、各チップ１４，１５からの発熱を吸収しつつ外部へ放熱するように、幅広に形成されている。
　こうしたリードフレームを構成する金属板１８は、絶縁基板１０上で所定の大きさの半田板１９ａ，１９ｂ，１９ｃを介在させて位置決めされ、１回のリフロー工程で半田板１９ａ，１９ｂ，１９ｃを溶融して絶縁基板１０に接合される。そのため、リフロー工程に先だって、金属板１８の各接合面１８ａ，１８ｂ，１８ｃは、それぞれ半田板１９ａ，１９ｂ，１９ｃとともに絶縁基板１０上で所定の位置に配置されていなくてはならない。とりわけ、小型で大電流構造の半導体装置を組み立てる場合には、金属板１８が正確に位置決めされていることが要求される。
　図１２は、従来の半導体装置におけるリードフレームの位置決めに用いられる位置決め用枠体を示す平面図である。
　位置決め用枠体２０は、導電パターン１２上で、そこに搭載されたＩＧＢＴチップ１４、ダイオードチップ１５によって所定の位置に位置決めして配置される枠体（コマ）である。この位置決め用枠体２０は、ＩＧＢＴチップ１４の図示左側で導電パターン１２の範囲を確定する枠２０ａ、ＩＧＢＴチップ１４の外周枠２０ｂ、ダイオードチップ１５の外周枠２０ｃ、および外周枠２０ｂ，２０ｃを接続する接続枠２０ｄによって単一の閉領域を規定している。これにより、図１１に示す金属板１８の、導電パターン１２上で配置されるべき位置（図中、想像線１８ｉで示す。）が確定される。
特開２００９－１７０５４３号公報 特開２００９－２５３１３１号公報
　こうした従来の半導体装置では、通常使用されているリードフレームを各チップ１４，１５上で半田付けする際に、半田板１９ｂ，１９ｃが前後左右方向で位置ずれを生じることが多い。そのため、ＩＧＢＴチップ１４やダイオードチップ１５の電極位置に対して半田板１９ｂ，１９ｃを正確に位置決めすることが困難であった。また、半田板１９ａ，１９ｂ，１９ｃを１回のリフロー工程で溶融させて、金属板１８を絶縁基板１０に接合するそれぞれの半田層を均一な厚さに仕上げることが難しい。とくに、金属板１８と各チップ１４，１５とで熱膨張係数の差が大きい場合には、各半田層の厚さが不均一となり、あるいは半田フィレットの面積が不十分なものとなれば、熱応力によって半田接合部の長期信頼性が十分に確保できないという問題も生じる。
　さらに、半導体装置自体の小型化に伴って、従来の位置決め用枠体２０を使用しても金属板１８と半田板１９ａ，１９ｂ，１９ｃとを同時に正確に位置決めすることが困難となり、チップ１４，１５からの発熱をいかに外部へ効率よく放出するかが課題となっている。このように、従来の半導体装置のリードフレームを組立てるうえで、絶縁基板１０上での位置決めが容易ではなく、接合位置が安定しないという問題があった。
　本発明はこのような点に鑑みてなされたものであり、大電流容量のリードフレームを接合している半田の寿命やリードフレームからの放熱性を確保すると同時に、小型化にともなう信頼性と組み立て性とを向上した半導体装置およびその製造方法を提供することを目的とする。
　本発明では、上記問題を解決するために、金属層を形成した絶縁基板上に複数の電子部品が搭載され、前記電子部品同士あるいは前記金属層と前記電子部品との間を電気的に接続することにより構成された半導体装置が提供される。この半導体装置は、所定の径と長さを有し、前記複数の電子部品あるいは前記金属層にそれぞれボンディングされた位置決め用のワイヤ部材と、前記複数の電子部品の相互間、あるいは前記金属層と前記電子部品との間に跨って配置され、それぞれを電気的に接続しているリードフレームと、前記電子部品あるいは前記金属層に対してその所定位置で前記リードフレームが接合するように、前記ワイヤ部材が挿通可能な大きさで前記リードフレームを貫通して形成された開口と、を備え、前記開口に前記ワイヤ部材を挿通することによって前記絶縁基板上で前記リードフレームが位置決めされている。
　また、本発明の半導体装置の製造方法は、導電パターンを形成した絶縁基板上に搭載された複数の半導体チップの相互間、あるいは前記半導体チップと前記導電パターンとの間をリードフレームによって電気的に接続する半導体装置の製造方法において、前記絶縁基板上の前記導電パターンに接合材により前記半導体チップを接合する第１の接合工程と、所定の径と長さを有する位置決め用のワイヤを、前記半導体チップあるいは前記導電パターンの主面であって、前記リードフレームが接合される位置にそれぞれボンディングするワイヤボンディング工程と、前記位置決め用のワイヤが挿入可能な大きさの開口部を有する前記リードフレームを用意し、前記絶縁基板上で前記複数の半導体チップの相互間、あるいは前記半導体チップと前記導電パターンとの間を接続する際に、前記リードフレームを前記位置決め用のワイヤによって位置決めする位置決め工程と、前記リードフレームの接合部を前記半導体チップ、あるいは前記導電パターン上の所定位置で半田層を介して接合する第２の接合工程とを含む。
　本発明によれば、従来の位置決め用枠体を使用することなく、簡単かつ確実にリードフレームと半田板とを同時に正確に位置決めすることができる。また、リードフレームを絶縁基板上に接合している半田層の寿命を低下させることなく、リードフレームからの放熱性が確保される。したがって、大電流小型化に伴う半導体装置の信頼性と組み立て性が向上できる。
　本発明の上記および他の目的、特徴および利点は本発明の例として好ましい実施の形態を表す添付の図面と関連した以下の説明により明らかになるであろう。
第１の実施の形態に係る半導体装置の一例を示す図であって、（Ａ）は半導体装置の平面図、（Ｂ）はＢ－Ｂ線に沿って示す断面図である。 リードフレームを接合するための半田板の形状を示す平面図である。 リードフレームの接合部の下面側に形成された突起部を示す図である。 第１の実施の形態に係る半導体装置の製造工程を示す図である。 第１の実施の形態に係る半導体装置に用いるリードフレームの変形例を示す平面図である。 第２の実施の形態に係る半導体装置の一例を示す図であって、（Ａ）は半導体装置の平面図、（Ｂ）はＢ－Ｂ線に沿って示す断面図である。 第２の実施の形態に係る半導体装置の等価回路を示す図である。 第２の実施の形態に係る半導体装置に用いるリードフレームの変形例を示す図であって、（Ａ）はリードフレームの平面図、（Ｂ）はＢ－Ｂ線に沿って示す断面図である。 第２の実施の形態に係る半導体装置に用いる位置決め用のワイヤ部材の変形例を示す断面図である。 第３の実施の形態に係る半導体装置に用いるリードフレームの一例を示す図であって、（Ａ）はリードフレームの平面図、（Ｂ）はＢ－Ｂ線に沿って示す断面図、（Ｃ）は一部断面の拡大図である。 従来の半導体装置の一例を示す図であって、（Ａ）は半導体装置の平面図、（Ｂ）はＢ－Ｂ線に沿って示す断面図である。 従来の半導体装置におけるリードフレームの位置決めに用いられる位置決め用枠体を示す平面図である。
　以下、図面を参照してこの発明の実施の形態について説明する。
　（第１の実施の形態）
　図１は、第１の実施の形態に係る半導体装置の一例を示す図であって、（Ａ）は半導体装置の平面図、（Ｂ）はＢ－Ｂ線に沿って示す断面図である。
　この半導体装置は、開口２１を有する矩形形状のリードフレーム２２により、導電パターン１２となる金属層が形成された絶縁基板（図示せず）上の電子部品２３，２４の間を電気的に接続するように構成されたものである。リードフレーム２２は、左右の端部に電子部品２３，２４の電極面に対応する大きさの接合部２２ａ，２２ｂを備え、図１（Ｂ）に示すように、これらの接合部２２ａ，２２ｂがそれぞれ所定の高さの起立部を介して、電子部品２３，２４の間を電気的に接続する。また、リードフレーム２２の開口２１は、その長手方向に一方の接合部２２ａから他方の接合部２２ｂに至る長さで、かつ所定の幅を有する長孔として、リードフレーム２２を貫通して形成されている。
　電子部品２３，２４は、図１（Ｂ）に示すように、それぞれ導電パターン１２上で所定の位置に予め接合材２５，２６によって接合され、かつアルミニウム線あるいは銅線のワイヤ部材２７が、２つの電子部品２３，２４の電極面で各端部がそれぞれボンディングされている。このワイヤ部材２７は、リードフレーム２２の開口２１の幅に対応する径（たとえば３００～５００μｍ）を有し、かつ電子部品２３，２４の電極面であって、それらの中央部の間を直線的に接続するように配置されている。
　ここで、リードフレーム２２を貫通して形成された開口２１に、２つの電子部品２３，２４に跨って配置されたワイヤ部材２７を挿通することによって、リードフレーム２２を正確に位置決めすることができる。このとき、各電子部品２３，２４の電極面とリードフレーム２２の接合部２２ａ，２２ｂとの間には、それぞれ半田板２８，２９が挟み込まれて、後のリフロー工程で溶融される。これらの半田板２８，２９には、後に図２に示すように、リードフレーム２２の開口２１の幅に対応する大きさのスリット２８ｓ，２９ｓが形成されている。
　図２は、リードフレームを接合するための半田板の形状を示す平面図である。
　半田板２８，２９は、それぞれ電子部品２３，２４の電極面に対応する大きさを有し、かつ所定のスリット２８ｓ，２９ｓが予め形成されている。そのため、スリット２８ｓ，２９ｓを各電極面にボンディングされたワイヤ部材２７の接着面と一致させることによって、半田板２８，２９の位置決めが可能となる。また、前述したように、これらの半田板２８，２９により電子部品２３，２４の電極面と接合されるリードフレーム２２の接合部２２ａ，２２ｂの位置も、同様にワイヤ部材２７によって決まる。
　したがって、従来の位置決め用枠体（図１２）のようなものを使用することなしに、簡単かつ確実にリードフレーム２２と半田板２８，２９とを同時に、導電パターン１２上で正確に位置決めすることができる。また、リードフレーム２２の接合部２２ａ，２２ｂに設けられた開口２１により、リフロー工程で溶融される半田板２８，２９は、そのスリット２８ｓ，２９ｓに対応する形状に沿って十分に大きな面積もしくは長さでフィレットが形成されることになる。そのため、それぞれリードフレーム２２の接合部２２ａ，２２ｂには、熱応力の経年変化に起因する外周部からのクラックが入りにくくなって、半導体装置の信頼性が高くなる。
　図３は、リードフレームの接合部の下面側に形成された突起部を示す図である。
　図３には、リードフレーム２２の接合部２２ｂ近傍を拡大して示している。この接合部２２ｂの下面側、すなわち電子部品２４との接続面（裏面）側には、開口２１の周縁に沿って下方に向かう突起部２２１が形成されている。この突起部２２１は、半田板２９の厚さにほぼ等しく、かつ半田板２９に形成されたスリット２９ｓ内に嵌り込む程度の大きさを有している。また、リードフレーム２２の接合部２２ｂにおける開口２１は、その表面側に段部２２２が形成されている。ここでは、リードフレーム２２の一方の接合部２２ｂについて説明したが、他方の接合部２２ａにも同様の突起部２２１と段部２２２が形成されている。
　こうして、リードフレーム２２はそれぞれ突起部２２１が電子部品２３，２４の電極面と直接に接触する状態で位置決めすることができる。したがって、半導体装置のリードフレーム２２は、ワイヤ部材２７によって前後左右方向について位置決めされるだけでなく、水平方向（上下方向）についても確実に位置決めできる。そのため、半田板２８，２９による接合層の厚みが均一化することになり、電子部品２３，２４の発熱を効率よく外部へ放出することができる。
　図４は、第１の実施の形態に係る半導体装置の製造工程を示す図である。
　同図（Ａ）には、セラミック基板１１の両面にそれぞれ所定形状の金属層からなる導電パターン１２，１３が接合形成された絶縁基板１０と、接合材２５，２６により導電パターン１２に接合される電子部品２３，２４を示している。ここで、全体を加熱炉などで加熱して接合材２５，２６を溶融することにより、絶縁基板１０上の導電パターン１２の所定位置に電子部品２３，２４を接合する第１の接合工程が実行される。
　図４（Ｂ）の工程では、ワイヤ部材２７が超音波ボンディングされる。ここでは、所定の径と長さを有する位置決め用のワイヤ部材２７の各端部が、リードフレーム２２が接合される電子部品２３，２４の主面の所定位置にそれぞれボンディングされる。このとき、他のボンディングワイヤを使って、他の電極と外部端子との間などを同時にボンディングすることが可能である。
　図４（Ｃ）では、リードフレーム２２と半田板２８，２９とを同時に、導電パターン１２上で位置決めする工程を示している。ここで使用するリードフレーム２２には、位置決め用のワイヤ部材２７を挿入可能な大きさで開口２１が予め形成されており、また半田板２８，２９にも、前述した図２に示すような所定のスリット２８ｓ，２９ｓが予め形成されている。その後、絶縁基板１０上に位置決めされたリードフレーム２２と半田板２８，２９を加熱炉などで加熱して溶融することにより、電子部品２３，２４の間にリードフレーム２２が固着され、第２の接合工程が完了する。
　最後に、絶縁基板１０をベース内に固定し、電子部品２３，２４、導電パターン１２およびリードフレーム２２をエポキシ樹脂あるいはゲルによって封止して、半導体装置として完成させる。
　なお、ここでは導電パターン１２上に電子部品２３，２４を接合する第１の接合工程を前提として、リードフレーム２２を固着する第２の接合工程を実施している。しかし、電子部品と導電パターンとの間をリードフレームによって接続する場合などでは、第１の接合工程と第２の接合工程とを同時に行うことも可能である。
　図５は、第１の実施の形態に係る半導体装置に用いるリードフレームの変形例を示す平面図である。
　ここで、変形例として示すリードフレーム２２Ｍでは、開口２１がそれぞれ２つの分離して形成された長孔Ｓ１，Ｓ２に置き換えられている。一方の長孔Ｓ１は、リードフレーム２２Ｍの接合部２２ａから接続部２２ｊに繋がる起立部に跨って、他方の長孔Ｓ２は、接合部２２ｂから接続部２２ｊに繋がる起立部に跨って、それぞれリードフレーム２２Ｍの長手方向に延長形成されている。その結果、２つの接合部２２ａ，２２ｂは、開口が形成されずに広い面積を有する接続部２２ｊによって接続される。したがって、２つの電子部品２３，２４の発熱を受けたリードフレーム２２Ｍは、広い面積の接続部２２ｊから外部に熱を効率よく放出することが可能になる。
　（第２の実施の形態）
　図６は、第２の実施の形態に係る半導体装置の一例を示す図であって、（Ａ）は半導体装置の平面図、（Ｂ）はＢ－Ｂ線に沿って示す断面図である。また、図７は、第２の実施の形態に係る半導体装置の等価回路を示す図である。
　図示した半導体装置には、板厚が数ミリの金属ベース板を基体とし、当該金属ベース板上に、錫（Ｓｎ）－銀（Ａｇ）系の鉛フリー半田層（図示せず）を介してセラミック基板１１で構成された絶縁基板が接合・搭載されている。そして、セラミック基板１１の上に、パワー半導体素子であるＩＧＢＴチップ２３ａ，２３ｂ、ダイオードチップ２４ａ，２４ｂなどが実装されている。この半導体装置には、上記パワー半導体素子、絶縁基板などを樹脂ケースにパッケージングして、汎用ＩＧＢＴモジュールが構成される。電力半導体素子モジュールは通常、上下アーム２素子分を１組とするか、または６素子分を１組としており、インバータ構成とするときは２素子構成のモジュールを通常、３並列接続するか、または６素子構成のものがそのまま用いられる。
　ここには、２つのＩＧＢＴチップ２３ａ，２３ｂと２つのダイオードチップ２４ａ，２４ｂがインバータ回路一相分の半導体モジュール（パワーモジュール）を構成する電子部品として配置された半導体装置が示されている。
　セラミック基板１１上には、５つに区分された導電パターン１２ａ～１２ｅが配置されている。導電パターン１２ａ上に搭載されたＩＧＢＴチップ２３ａとダイオードチップ２４ａは、図７に示す正側（Ｐ）の直流端子４３に接続されるＩＧＢＴ４１ａとダイオード４２ａを構成する。ＩＧＢＴ４１ａのゲート端子Ｇ１は、ＩＧＢＴチップ２３ａから配線用ワイヤ３０ａによって導電パターン１２ｂに接続される。
　また、ＩＧＢＴチップ２３ａとダイオードチップ２４ａの表面電極は、第１のリードフレーム３１によって出力端子（Ｕ端子）４５を構成する導電パターン１２ｃと電気的に接続される。導電パターン１２ｃ上には、ＩＧＢＴ４１ｂとダイオード４２ｂを構成するＩＧＢＴチップ２３ｂとダイオードチップ２４ｂが搭載され、それらの表面電極は負側（Ｎ）の直流端子４４を構成する導電パターン１２ｅと第２のリードフレーム３２によって電気的に接続される。ＩＧＢＴ４１ｂのゲート端子Ｇ２は、ＩＧＢＴチップ２３ｂから配線用ワイヤ３０ｂによって導電パターン１２ｄに接続される。
　この半導体装置では２つのリードフレーム３１，３２が使用されている。たとえばリードフレーム３１は、図６（Ｂ）に示すように、３つの接合部３１ａ，３１ｂ，３１ｃを有している。また、各接合部３１ａ，３１ｂ，３１ｃには、リードフレーム３１の幅方向に並列に３本の長孔Ｓａ１～Ｓｃ１，Ｓａ２～Ｓｃ２，Ｓａ３～Ｓｃ３，Ｓａ４～Ｓｃ４がそれぞれ起立部に懸かるように等間隔で配置されている。そして、これらの長孔Ｓａ１～Ｓｃ１，Ｓａ２～Ｓｃ２，Ｓａ３～Ｓｃ３，Ｓａ４～Ｓｃ４のうち、各外側の位置に対しては、ダイオードチップ２４ａとＩＧＢＴチップ２３ａの各表面電極を接続する位置決め用のワイヤ部材Ｗａ１，Ｗｃ１、およびＩＧＢＴチップ２３ａの表面電極と導電パターン１２ｃを接続する位置決め用のワイヤ部材Ｗａ２，Ｗｃ２がボンディングされている。なお、リードフレーム３２についても同様である。
　したがって、インバータ回路一相分の半導体モジュールを構成する半導体装置において、簡単かつ確実に２つのリードフレーム３１，３２を位置決めして、図７に示す等価回路に相当する配線を形成することができる。
　図８は、第２の実施の形態に係る半導体装置に用いるリードフレームの変形例を示す図であって、（Ａ）はリードフレームの平面図、（Ｂ）はＢ－Ｂ線に沿って示す断面図である。
　このリードフレーム３３は、図６に示すリードフレーム３１に対応するものであるが、その幅方向に並列に３本の長孔Ｓａ１～Ｓｃ１，Ｓａ２～Ｓｃ２，Ｓａ３～Ｓｃ３，Ｓａ４～Ｓｃ４の長さを短く形成した点で異なっている。たとえば長孔Ｓａ１～Ｓｃ１については、図６（Ａ）のものと比較して、ダイオードチップ２４ａとの接合部３３ａでの長さが短くなっている。また、ＩＧＢＴチップ２３ａとの接合部３３ｂで貫通する長孔Ｓａ２～Ｓｃ２，Ｓａ３～Ｓｃ３も、図６（Ａ）のものと比較して短くなっている。さらに、導電パターン１２ｃとの接合部３３ｃには、リードフレーム３３の起立部に掛からない長さで、Ｕ字形状の長孔Ｓａ４～Ｓｃ４が形成されている。
　したがって、ダイオードチップ２４ａおよびＩＧＢＴチップ２３ａからの発熱をリードフレーム３１に伝導して、効率よく外部へ放出することができる。
　図９は、第２の実施の形態に係る半導体装置に用いる位置決め用のワイヤ部材の変形例を示す断面図である。
　ワイヤ部材３４１～３４４は、一端がダイオードチップ２４ａとＩＧＢＴチップ２３ａ、および導電パターン１２ｃの所定位置にボンディングされている。これらのワイヤ部材３４１～３４４は、少なくともリードフレーム３３を貫通して形成された各長孔Ｓａ１～Ｓａ４の上方に突出するだけの長さを有していれば、リードフレーム３３の絶縁基板１０上での位置決めは十分に可能であり、ワイヤ部材自体を無駄に使用しないで済むという利点がある。
　なお、リードフレーム３３の金属板は各チップ２３ａ，２４ａの半導体と比較して熱膨張係数が大きい。そのため、リードフレーム３３の起立部を貫通するように長孔Ｓａ１～Ｓａ３を形成することによって、金属板のたわみを吸収することが可能になる。
　（第３の実施の形態）
　図１０は、第３の実施の形態に係る半導体装置に用いるリードフレームの一例を示す図であって、（Ａ）はリードフレームの平面図、（Ｂ）はＢ－Ｂ線に沿って示す断面図、（Ｃ）は一部断面の拡大図である。
　このリードフレーム３５は、図８に示すリードフレーム３の長孔に代えて、接合部３５ａ～３５ｃにそれぞれ段付丸孔ｈａ１，ｈａ２、ｈｂ１～ｈｂ５、およびｈｃ１，ｈｃ２を貫通形成したものである。図１０（Ｃ）に拡大断面を示すように、段付丸孔ｈａ２の裏側（接合面側）には、下方に向かう突起部３５１が形成されている。また、段付丸孔ｈａ２の表側に段部３５２が形成されている。なお、突起部３５１の高さＨは、接合材として使用される半田板の厚さに相当する。
　この場合でも、第２の実施の形態における変形例として説明した位置決め用のワイヤ部材（図９）によって絶縁基板上でのリードフレーム３５の位置決めを容易に行うことができる。また、リードフレーム３５を接合する際の接合層の厚みを均一化することが容易であり、電子部品２３，２４での発熱を効率よく外部へ放出することができる。
　上記については単に本発明の原理を示すものである。さらに、多数の変形、変更が当業者にとって可能であり、本発明は上記に示し、説明した正確な構成および応用例に限定されるものではなく、対応するすべての変形例および均等物は、添付の請求項およびその均等物による本発明の範囲とみなされる。
　１０　絶縁基板
　１１　セラミック基板
　１２，１３　導電パターン
　２１　開口
　２２，３１，３２，３３，３５　リードフレーム
　２３，２４　電子部品
　２３ａ，２３ｂ　ＩＧＢＴチップ
　２４ａ，２４ｂ　ダイオードチップ
　２５，２６　接合材
　２７，３４１～３４４，Ｗａ１，Ｗｃ１，Ｗａ２，Ｗｃ２　ワイヤ部材
　２８，２９　半田板
　２８ｓ，２９ｓ　スリット
　３０ａ，３０ｂ　配線用ワイヤ
　ｈａ１，ｈａ２，ｈｂ１～ｈｂ５，ｈｃ１，ｈｃ２　段付丸孔
　Ｓ１，Ｓ２，Ｓａ１～Ｓｃ１，Ｓａ２～Ｓｃ２，Ｓａ３～Ｓｃ３，Ｓａ４～Ｓｃ４　長孔

Claims (12)

  1. 　金属層を形成した絶縁基板上に複数の電子部品が搭載され、前記電子部品同士あるいは前記金属層と前記電子部品との間を電気的に接続することにより構成された半導体装置において、
    　所定の径と長さを有し、前記複数の電子部品あるいは前記金属層にそれぞれボンディングされた位置決め用のワイヤ部材と、
    　前記複数の電子部品の相互間、あるいは前記金属層と前記電子部品との間に跨って配置され、それぞれを電気的に接続しているリードフレームと、
    　前記電子部品あるいは前記金属層に対してその所定位置で前記リードフレームが接合するように、前記ワイヤ部材が挿通可能な大きさで前記リードフレームを貫通して形成された開口と、
    　を備え、
    　前記開口に前記ワイヤ部材を挿通することによって前記絶縁基板上で前記リードフレームが位置決めされていることを特徴とする半導体装置。
  2. 　前記リードフレームは、前記電子部品あるいは前記金属層と接触する少なくとも一対の接合部と、前記一対の接合部からそれぞれ立ち上がる起立部と、前記起立部を介して前記一対の接合部の間を接続する接続部とを有し、
    　前記開口は、前記接合部と前記起立部とに跨って前記リードフレームの長手方向に延長形成された長孔であることを特徴とする請求の範囲第１項記載の半導体装置。
  3. 　前記長孔は、前記一対の接合部で前記リードフレームの幅方向に複数本並べて形成されていることを特徴とする請求の範囲第２項記載の半導体装置。
  4. 　前記リードフレームには、前記電子部品あるいは前記金属層と接触する接合部の下面側に、前記開口の周縁に沿って下方に向かう突起部が形成されていることを特徴とする請求の範囲第１項記載の半導体装置。
  5. 　前記ワイヤ部材は、３００～５００μｍの径を有するアルミニウム線あるいは銅線であることを特徴とする請求の範囲第１項記載の半導体装置。
  6. 　前記ワイヤ部材は、一端が前記複数の電子部品あるいは前記金属層の所定位置にボンディングされ、少なくとも前記リードフレームを貫通して形成された開口から上方に突出するだけの長さを有していることを特徴とする請求の範囲第１項記載の半導体装置。
  7. 　前記金属層は、前記絶縁基板の両面に形成された導電パターンであることを特徴とする請求の範囲第１項記載の半導体装置。
  8. 　前記電子部品はＩＧＢＴあるいはダイオードを構成する半導体チップであって、
    　前記リードフレームによって前記ＩＧＢＴと前記ダイオードを互いに逆並列に接続するように構成されていることを特徴とする請求の範囲第１項記載の半導体装置。
  9. 　前記絶縁基板は、ベースの上面に半田接続され、
    　前記電子部品が前記ベースを介して放熱部材に熱的に接続されていることを特徴とする請求の範囲第１項記載の半導体装置。
  10. 　導電パターンを形成した絶縁基板上に搭載された複数の半導体チップの相互間、あるいは前記半導体チップと前記導電パターンとの間をリードフレームによって電気的に接続する半導体装置の製造方法において、
    　前記絶縁基板上の前記導電パターンに接合材により前記半導体チップを接合する第１の接合工程と、
    　所定の径と長さを有する位置決め用のワイヤを、前記半導体チップあるいは前記導電パターンの主面であって、前記リードフレームが接合される位置にそれぞれボンディングするワイヤボンディング工程と、
    　前記位置決め用のワイヤが挿入可能な大きさの開口部を有する前記リードフレームを用意し、前記絶縁基板上で前記複数の半導体チップの相互間、あるいは前記半導体チップと前記導電パターンとの間を接続する際に、前記リードフレームを前記位置決め用のワイヤによって位置決めする位置決め工程と、
    　前記リードフレームの接合部を前記半導体チップ、あるいは前記導電パターン上の所定位置で半田層を介して接合する第２の接合工程と、
    　を含むことを特徴とする半導体装置の製造方法。
  11. 　前記ワイヤボンディング工程は、前記導電パターンに配線用ワイヤをボンディングする工程と同時に実施することを特徴とする請求の範囲第１０項記載の半導体装置の製造方法。
  12. 　前記第２の接合工程の後に、前記半導体チップ、前記導電パターン、および前記リードフレームをエポキシ樹脂あるいはゲルによって封止するようにしたことを特徴とする請求の範囲第１０項記載の半導体装置の製造方法。
PCT/JP2012/065224 2011-08-10 2012-06-14 半導体装置および半導体装置の製造方法 WO2013021726A1 (ja)

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