JP4946959B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4946959B2 JP4946959B2 JP2008101133A JP2008101133A JP4946959B2 JP 4946959 B2 JP4946959 B2 JP 4946959B2 JP 2008101133 A JP2008101133 A JP 2008101133A JP 2008101133 A JP2008101133 A JP 2008101133A JP 4946959 B2 JP4946959 B2 JP 4946959B2
- Authority
- JP
- Japan
- Prior art keywords
- metal plate
- wire
- solder
- igbt
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
図1は、本発明の第1実施形態に係る半導体装置100の概略構成を示す図であり、(a)は概略断面図、(b)は同半導体装置100における第1の金属板30の一面31上の構成を示す概略平面図、(c)は(b)の側方図、(d)は本実施形態のガイド部としてのガイドワイヤ200の概略断面図である。
図3(a)は、本発明の第2実施形態に係る半導体装置の製造方法の要部を示す概略平面図であり、本実施形態の半導体装置における第1の金属板30の一面31上の構成を示しており、図3(b)は(a)の概略断面図である。本実施形態は、上記第1実施形態とはガイド部を変更したものであり、この点を中心に述べることとする。
図4は、本発明の第3実施形態に係る半導体装置の製造方法の要部を示す概略平面図であり、本実施形態の半導体装置における第1の金属板30の一面31上の構成を示している。本実施形態は、上記第1実施形態とはガイド部を変更したものであり、この点を中心に述べることとする。
図5は、本発明の第4実施形態に係る半導体装置の製造方法の要部を示す概略平面図であり、本実施形態の半導体装置における第1の金属板30の一面31上の構成を示している。本実施形態も、上記第1実施形態とはガイド部を変更したものであり、この点を中心に述べることとする。
なお、両金属板30、40に挟まれる半導体素子としては、上記したIGBT10に限定されるものではなく、その一面にボンディングワイヤ20が接続されるものであるならば、MOSトランジスタやマイコンなどのICチップなどでもよい。さらに、当該半導体素子は2個以上でもよい。
11 ワイヤ接続部
20 ボンディングワイヤ
30 第1の金属板
31 第1の金属板の一面
40 第2の金属板
41 第2の金属板の一面
50 第1のはんだ
60 第2のはんだ
200 ガイド部としてのガイドワイヤ
201 ガイド部としての凹部
202 ガイド部としてのパターン
203 ガイド部としてのフィルム
R 素子搭載領域
Claims (2)
- 一面側にワイヤ(20)が接続されるワイヤ接続部(11)を有する半導体素子(10)を備え、
前記半導体素子(10)の前記一面とは反対側の他面に、第1のはんだ(50)を介して第1の金属板(30)の一面(31)を接合し、
前記半導体素子(10)の前記一面のうち前記ワイヤ接続部(11)以外の部位に、第2のはんだ(60)を介して第2の金属板(40)の一面(41)を接合するとともに、前記ワイヤ接続部(11)を前記第2の金属板(40)より露出させ、
前記ワイヤ接続部(11)に前記ワイヤ(20)を接続してなる半導体装置を製造する半導体装置の製造方法であって、
前記半導体素子(10)の前記一面、前記他面に、それぞれ前記第1のはんだ(50)、前記第2のはんだ(60)を介して前記第1の金属板(30)、前記第2の金属板(40)を配置する配置工程と、
続いて、前記第1のはんだ(50)および前記第2のはんだ(60)を同時にリフローさせることにより、前記半導体素子(10)と前記両金属板(30、40)とをはんだ接合するリフロー工程と、
しかる後、前記ワイヤ接続部(11)に前記ワイヤ(20)を接続するワイヤ接続工程とを備え、
前記配置工程の前に、予め、前記第1の金属板(30)の前記一面(31)のうち前記半導体素子(10)が搭載される領域である素子搭載領域(R)の外側に、当該素子搭載領域(R)の外形に沿った形状をなすガイド部(200〜203)を設けておくガイド部設置工程を行い、
前記配置工程では、前記ガイド部(200〜203)を位置決めの目印として前記第1の金属板(30)の前記一面(31)に、前記第1のはんだ(50)、前記半導体素子(10)および前記第2のはんだ(60)を搭載するものであり、
前記ガイド部設置工程では、前記第1の金属板(30)の前記一面(31)に対してボンディングワイヤ(200)を接続するとともに、当該ボンディングワイヤ(200)を前記半導体素子(10)の外形に沿った形状をなすものし、当該ボンディングワイヤ(200)により前記ガイド部を構成することを特徴とする半導体装置の製造方法。 - 前記第1の金属板(30)の前記一面(31)に対してボンディングワイヤ(200)を接続した後に、当該ボンディングワイヤ(200)の表面を電気絶縁性材料でコーティングし、このコーティング後の前記ボンディングワイヤ(200)により前記ガイド部を構成することを特徴とする請求項1に記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008101133A JP4946959B2 (ja) | 2008-04-09 | 2008-04-09 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008101133A JP4946959B2 (ja) | 2008-04-09 | 2008-04-09 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009253131A JP2009253131A (ja) | 2009-10-29 |
JP4946959B2 true JP4946959B2 (ja) | 2012-06-06 |
Family
ID=41313525
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008101133A Expired - Fee Related JP4946959B2 (ja) | 2008-04-09 | 2008-04-09 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4946959B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9076782B2 (en) | 2011-08-10 | 2015-07-07 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing same |
CN110770883B (zh) * | 2017-06-22 | 2023-08-22 | 三菱电机株式会社 | 半导体装置、电力变换装置及半导体装置的制造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56139245A (en) * | 1980-03-14 | 1981-10-30 | Hirata Press Kogyo Kk | Production of rim |
JP3596388B2 (ja) * | 1999-11-24 | 2004-12-02 | 株式会社デンソー | 半導体装置 |
JP2001298033A (ja) * | 2000-04-12 | 2001-10-26 | Hitachi Ltd | 半導体装置 |
JP4019993B2 (ja) * | 2003-03-31 | 2007-12-12 | 株式会社デンソー | 半導体装置 |
-
2008
- 2008-04-09 JP JP2008101133A patent/JP4946959B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2009253131A (ja) | 2009-10-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4969113B2 (ja) | 回路装置の製造方法 | |
KR100440416B1 (ko) | 반도체 디바이스 | |
KR100374241B1 (ko) | 반도체 장치 및 그 제조 방법 | |
JP2005203497A (ja) | 半導体装置およびその製造方法 | |
JP5270614B2 (ja) | 半導体装置 | |
JP4420001B2 (ja) | パワー半導体モジュール | |
JP5733401B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP5589950B2 (ja) | 電子装置 | |
JP4888085B2 (ja) | 半導体装置の製造方法 | |
JP2007150045A (ja) | 半導体装置 | |
JP4946959B2 (ja) | 半導体装置の製造方法 | |
JP3695458B2 (ja) | 半導体装置、回路基板並びに電子機器 | |
JP4577686B2 (ja) | 半導体装置及びその製造方法 | |
JP2010050288A (ja) | 樹脂封止型半導体装置およびその製造方法 | |
JP4038021B2 (ja) | 半導体装置の製造方法 | |
JP2009224529A (ja) | 半導体装置およびその製造方法 | |
JP5217014B2 (ja) | 電力変換装置およびその製造方法 | |
JP6063835B2 (ja) | 半導体チップの実装方法、半導体装置、及び実装治具 | |
JP3778761B2 (ja) | 半導体レーザ装置 | |
KR100246367B1 (ko) | 반도체 패키지 및 그 제조방법 | |
JP4853276B2 (ja) | 半導体装置の製造方法 | |
WO2021020456A1 (ja) | 半導体パッケージおよび半導体装置 | |
JP4957649B2 (ja) | はんだ接合体およびその製造方法 | |
JP4561670B2 (ja) | 電子装置の実装構造および電子装置の実装方法 | |
JP4175339B2 (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100618 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110725 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110802 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110919 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120207 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120220 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150316 Year of fee payment: 3 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 4946959 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150316 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |