TWI447876B - 利用引導框及晶片之半導體晶粒封裝及其製造方法 - Google Patents

利用引導框及晶片之半導體晶粒封裝及其製造方法 Download PDF

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Publication number
TWI447876B
TWI447876B TW095140735A TW95140735A TWI447876B TW I447876 B TWI447876 B TW I447876B TW 095140735 A TW095140735 A TW 095140735A TW 95140735 A TW95140735 A TW 95140735A TW I447876 B TWI447876 B TW I447876B
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Taiwan
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semiconductor die
clip
package
clip structure
leadframe
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TW095140735A
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English (en)
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TW200729442A (en
Inventor
Erwin Victor R Cruz
Elsie Cabahug
Ti Ching Shian
Venkat Iyer
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Fairchild Semiconductor
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Publication of TW200729442A publication Critical patent/TW200729442A/zh
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Publication of TWI447876B publication Critical patent/TWI447876B/zh

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Description

利用引導框及晶片之半導體晶粒封裝及其製造方法
本發明係為一種利用引導框及晶片之半導體晶粒封裝及其製造方法。
 發明背景
多數的半導體晶粒封裝使用線夾取代焊線，用以構成對外部終端的外部連接。該等半導體晶粒封裝有時係視為”無線(wireless)”封裝。典型的無線封裝包括一附裝至一半導體晶粒的線夾。與使用線基電連接(wire-based electrical connection)相較，無線封裝一般而言具有較佳的電氣及熱性能。
典型地，傳統式無線封裝需經設計進入消費者電路板，因為電路板具獨有的據用空間(footprint)及引腳分配(pin assignment)。提供具有與傳統式封裝據用面積及引腳分配相符合的據用面積及引腳分配，同時仍具有良好電氣及熱性能的半導體晶粒封裝係為所需的。
同時，當生產無線封裝時，通常難以產生具有一深凹壓(deep downset)的一線夾(例如，一源極線夾(source clip))。線夾之”凹壓”係與線夾之一主要部分與線夾之引線部分之間的垂直距離相一致。提供具有較傳統式線夾更深的凹壓的一線夾亦係為所需的，因此能夠生產不同型式的封裝。
線夾與半導體晶粒存在的另一問題在於線夾與半導體 晶粒之間不一致或是不均勻地施加焊料量的問題。當在一晶粒與一線夾之間使用不一致或是不均勻的焊料量時，所完成的封裝性能不良。
除了上述提及的問題之外，有利地提供一能夠用以快速且可靠地產生一半導體晶粒封裝的方法。該方法亦較佳地與無鉛加工(Pb-free processing)相容。
本發明之具體實施例能夠解決上述以及其他問題。
 發明概要
本發明之具體實施例係針對線夾結構，半導體晶粒封裝包括線夾結構，以及製造包括線夾結構的半導體晶粒封裝的方法。
本發明之一具體實施例係針對半導體封裝所用的一線夾結構，該線夾結構包含：一主要部分；至少一自該主要部分延伸的台座；一凹壓部分；以及一引線部分，其中凹壓部分係介於引線部分與主要部分之間。
本發明之另一具體實施例係針對半導體封裝所用的一線夾結構，該線夾結構包含：一主要部分；一具有階梯狀構形的凹壓部分；以及一引線部分，其中凹壓部分係介於引線部分與主要部分之間。
本發明之其他具體實施例係針對半導體晶粒封裝，包括上述線夾結構，以及使用線夾結構的製造半導體晶粒封裝的方法。
本發明之另一具體實施例係針對半導體晶粒封裝，其 包含：一線夾結構其包括一主要部分；至少一自該主要部分延伸的台座；一凹壓部分；以及一引線部分，其中凹壓部分係介於引線部分與主要部分之間，以及具有一階梯狀構形；一導線架結構；以及一半導體晶粒，其中半導體晶粒係介於導線架結構與線夾結構之間。
本發明之另一具體實施例係針對製造半導體晶粒封裝的方法，該方法包含：獲得一線夾總成；獲得一導線架結構其包含至少一對準結構，其中在半導體晶粒封裝之裝配期間該對準結構將線夾總成與導線架結構對準；將半導體晶粒之一第二表面黏合至導線架結構；以及將半導體晶粒之一第一表面黏合至線夾總成。
以下將進一步地詳述本發明之該等及其他具體實施例。
圖式簡單說明
第1圖係為本發明之一具體實施例的一晶粒封裝的一側橫截面視圖。
第2圖係為本發明之一具體實施例的一線夾結構中的一台座之一側橫截面視圖。
第3圖係為本發明之一具體實施例的一半導體晶粒封裝的一透視圖。
第4圖係為本發明之一具體實施例的一半導體晶粒封裝的一概略俯視圖。
第5圖係為本發明之一具體實施例的一半導體晶粒封裝的一側視圖。
第6圖係為本發明之一具體實施例的一導線架結構的一仰視圖。
第7圖係為本發明之一具體實施例的一線夾總成的一俯視圖。
第8圖係為本發明之一具體實施例的一線夾結構的一側橫截面視圖。
第9圖係為本發明之一具體實施例的一台座的一側橫截面視圖。
第10圖係為包括一金屬氧化半導體場效電晶體(MOSFET)晶粒及一肖特基二極體晶粒(Schottky diode die)的一半導體晶粒封裝之一概略俯視圖。
第11圖係為包括二金屬氧化半導體場效電晶體(MOSFET)晶粒的一半導體晶粒封裝之一概略俯視圖。
第12圖係為本發明之另一具體實施例的一半導體晶粒封裝。於此具體實施例中，線夾結構及導線架結構二者之表面係通過一模塑材料而暴露。
第13(A)至13(D)圖係顯示當所有結構皆裝配於半導體晶粒封裝中時該等結構的側橫截面視圖。
 較佳實施例之詳細說明
本發明之具體實施例包括無線封裝。本發明之一具體實施例之無線封裝未使用焊線連接至一半導體晶粒中一電氣裝置的輸入及/或輸出終端。於其他具體實施例中，半導體晶粒封裝並不需為無線。例如，如以下說明，本發明之 具體實施例包括具有特定構形的獨特源極線夾結構。該等源極線夾結構能夠利用一閘極打線接合於一半導體晶粒封裝中使用。然而，無線半導體晶粒封裝係為較佳的，一般而言與使用焊線而終端連接的半導體晶粒封裝相較具有較佳的熱及電氣特性。
於一半導體晶粒封裝具體實施例中，半導體晶粒封裝包含一線夾結構其包括一主要部分，至少一自該主要部分延伸的台座，一凹壓部分以及一引線部分。凹壓部分係介於引線部分與主要部分之間，並能夠具有一階梯狀構形。一半導體晶粒係夾合於其間並係黏合至線夾結構及一導線架結構。
於本發明之具體實施例中，一第一焊接材料能夠用以機械及電氣方式將半導體晶粒與導線架結構耦合。一第二焊接材料能夠用以機械及電氣方式將半導體晶粒與線夾結構耦合。第一及第二焊接材料可為相同或為不同。該等材料較佳地係為相同的材料並可包含無鉛焊接材料。
第1圖係為本發明之一具體實施例的一半導體晶粒封裝的一側橫截面視圖。半導體晶粒封裝100包括一半導體晶粒16，其係配置位在一源極線夾結構14與一導線架結構18之間。一模塑材料20至少部分地覆蓋半導體晶粒16、線夾結構14及導線架結構18。模塑材料20可為一環氧樹脂模塑材料或是任一適合的市售模塑材料。
如第1圖中所示，半導體晶粒封裝100亦包括一第一側表面100(a)及一第二側表面100(b)，以及一頂部表面100(c) 及一底部表面(d)。
即使最終半導體晶粒封裝100已內嵌引線，但半導體晶粒封裝100能夠視為一”無引線(leadless)”式封裝，因為引線未延伸通過模塑材料20之側表面。亦能夠為一塊件的形式，並且於一些具體實施例中半導體晶粒封裝100亦可視為一微型導線架封裝(MLP)型式之封裝。儘管於此說明書中詳細說明一無引線晶粒封裝，但應瞭解的是線夾結構14可任擇地能夠於一引線晶粒封裝中使用。
焊接24係介於半導體晶粒16之一第一表面16(a)與線夾結構14之間。焊接90亦係存在於半導體晶粒16之一第二表面16(b)與導線架結構18之間。
焊接24及焊接90可使用任一適合的焊接材料。例如，焊接24及焊接90可使用鉛-錫焊料。較佳地，焊接24及焊接90包含一無鉛焊接材料，諸如銦-錫基焊料。可任擇地，可使用一傳導性聚合物黏著劑(例如，一傳導性環氧樹脂黏著劑)取代焊接。
半導體晶粒16可包括任一適合的半導體裝置。適合的半導體裝置可包含一諸如矽的半導體材料，並可包括垂直或水平裝置。垂直裝置在晶粒的一側邊至少具有一輸入部分，以及在晶粒的另一側邊至少具有一輸出部分，因此電流能夠垂直地流經晶粒。水平裝置在晶粒的一側邊至少包括一輸入部分，以及在晶粒的相同側邊至少具有一輸出部分，因此電流能夠水平地流經晶粒。半導體晶粒16中的半導體裝置較佳地係為一垂直功率電晶體。
垂直功率電晶體包括功率垂直雙擴散金屬氧化物半導體(VDMOS)電晶體及垂直雙極電晶體。VDMOS電晶體係為一MOSFET，具有二或更多藉由擴散構成的半導體區域。其具有一源極區域、一汲極區域及一閘極。裝置為垂直式其中源極區域及汲極區域係位在半導體晶粒之相對表面。閘極可為一槽溝閘極結構或是一平面閘極結構，並係構成位在與源極區域相同的表面。槽溝閘極結構係為較佳的，因為槽溝閘極結構與平面閘極結構相較係較窄並據用較少空間。於作業期間，於一VDMOS裝置中自源極區域流動至汲極區域的電流，實質上係與晶粒表面垂直。
於此實例中，半導體晶粒16包含一垂直MOSFET。垂直MOSFET包括位在半導體晶粒16之第一表面16(a)的一源極區域及一閘極區域，以及半導體晶粒16之第二表面16(b)的一汲極區域。源極區域具有一源極金屬(例如，一可焊接頂部金屬或是焊接凸塊)，並可與線夾結構14(其可為一源極線夾結構)電耦合。閘極區域可與一相符合的閘極線夾結構(未顯示)電耦合，同時位在第二表面16(b)的汲極區域可與導線架18電耦合。
導線架結構18包括一第一表面18(a)以及一第二表面18(b)。導線架結構18亦包括一藉由蝕刻製程構成的部分18(c)，以及一墊部分18(e)以及一引線部分18(d)。墊部分18(e)構成導線架結構18之晶粒黏結墊(DAP)。
如第1圖中所示，引線部分18(d)未延伸通過模塑材料20，並且實質上係與模塑材料20之一底部外表面20(a)共平 面。半導體晶粒封裝100之第一側表面100(a)係與模塑材料20之一側表面及引線部分18(d)之一側表面相一致。半導體晶粒封裝100之底部表面100(d)係與導線架結構18之一底部表面及模塑材料20之一底部外表面相一致。
導線架結構18之底部係通過模塑材料20而露出。導線架結構18之暴露底部表面係提供作為一附加的汲極連接部分，以及供半導體晶粒封裝100所用的一附加冷卻路徑。
導線架結構18可包含任一適合的材料。例如，導線架結構18包含銅、銅合金或是任何其他適合的傳導性材料。如為所需，其亦可以一可焊接金屬電鍍。
線夾結構14可具有任一適合的構形。於此實例中，線夾結構14包括一主要部分14(a)、一引線部分14(c)以及一凹壓部分14(b)。凹壓部分14(b)係配置位在主要部分14(a)與引線部分14(c)之間。其包括一階梯狀或Z字形結構。儘管於第1圖中顯示一”階梯”，但於其他具體實施例中，線夾結構14可包括多重階梯。
線夾結構14可包含任一適合的材料。例如，傳導性材料，諸如銅、鋁、以及貴重金屬(及其之合金)，可於線夾結構14中使用。如為所需，線夾結構14亦可以可焊接層電鍍。
線夾結構14之階梯狀凹壓部分14(b)提供複數之優點。例如，階梯狀結構考量引線部分14(c)之一底部表面與導線架結構18之一底部表面間較佳的對準公差。由於將凹壓部分14(b)彎曲，所以較一非階梯狀凹壓部分更具”撓曲性”。如此容許引線部分14(c)更易於與導線架結構18之底部表面 對準。同時，階梯狀凹壓部分14(b)亦容許線夾結構14具有一較傳統線夾結構為深的凹壓。
於線夾結構14中，複數之分離台座14(a)-1向下地延伸並與線夾結構14之主要部分14(a)的水平表面垂直。第2圖中更為清楚地顯示台座14(a)-1。如所顯示，台座14(a)-1之端部能夠接觸半導體晶粒16之第一表面16(a)，以及焊接24環繞台座。與台座14(a)-1相對的線夾結構14之表面係稍微為凹面的。此凹面結構及對應的台座14(a)-1能夠藉由一諸如沖壓(stamping)的製程而構成。儘管敘述一沖壓製程，但本發明之具體實施例的台座能夠以熟知此技藝之人士所熟知的任一其他適合的方法構成。例如，能夠藉由蝕刻線夾結構而在一平面線夾結構上構成台座，因此構成合適的突出部分。可任擇地，藉由在線夾結構之一平坦表面上電鍍或配置傳導性柱狀物而構成突出部分。
線夾結構14中之台座14(a)-1提供複數之優點。例如，其於源極線夾結構14之主要部分14(a)的底部表面與半導體晶粒16之第一表面16(a)之間提供一致的間隔。由於線夾結構14之主要部分14(a)與半導體晶粒16之第一表面16(a)之間具有一致的間隔，所以於其間總是存在著一致的焊料量。若有的話，過多的焊料會自線夾結構14與半導體晶粒16之間擠出。除了提供更為一致的焊料沉積之外，台座14(a)-1亦提供供線夾結構14所用的一較大黏結表面積，從而在源極線夾結構14與半導體晶粒16之間提供較佳的黏合及較佳的電氣連接。台座14(a)-1亦防止線夾結構14發生非 所欲的”傾斜”。假若台座14(a)-1未存在，則線夾會”傾斜”，從而造成不均地施加焊料至半導體晶粒16之頂部表面。
第3圖係為本發明之一具體實施例的一半導體晶粒封裝的一透視圖。於此圖式中，並未顯示模塑材料。如第3圖中所示，半導體晶粒封裝可包括一源極線夾結構14以及一閘極線夾結構28。閘極線夾結構28及源極線夾結構14係相互地非電耦合。如以下更為詳細地說明，源極線夾結構14以及閘極線夾結構28可源自於一線夾總成。於第3圖中，如第1圖，半導體晶粒16係夾合在源極線夾結構14與導線架結構18之間。同時，如第3圖中所示，半導體晶粒16亦夾合在閘極線夾結構28與導線架結構18之間。與源極線夾結構14相同，閘極線夾結構28亦可包括一或更多台座(未顯示)，提供一致的焊料沉積。
第4圖係為一封裝總成中的一半導體晶粒封裝的一俯視圖。藉由代表符號40所標示的點線係顯示總成將利用一鋸或相似物進行切割之處。進行切割之前，閘極線夾結構18與源極線夾結構14係藉由一橋接結構52結合。橋接結構52係與閘極線夾結構18與源極線夾結構14之引線作電氣及機械方面連接。此外，進行切割之前，導線架結構18係為一導線架總成的一部分，包括一對準軌道結構70。對準軌道結構70包括二對準端部結構70(a)。於此實例中，對準端部結構70(a)係為金屬正方形之形式，但於本發明之其他具體實施例中可為其他形狀。對準端部結構70(a)限制橋接結構52，因此線夾總成102係正確地與半導體晶粒16之終端對 準。具體地，源極線夾結構14及源極線夾結構台座14(a)-1係自動地對準，因此其係與半導體晶粒16之MOSFET中的源極終端電耦合。同時，閘極線夾結構18及閘極台座18(a)-1係自動地對準，因此其係與半導體晶粒16之MOSFET中的閘極終端電耦合。以一步驟進行此對準製程，從而節省加工時間及成本。
一旦使用焊接將線夾總成102及導線架結構18黏結至半導體晶粒16，最終總成接受一回焊製程(reflow process)於封裝中同時地將所有焊料回焊。接著於一囊封製程中將一模塑材料構成環繞著晶粒。接著，沿著代表符號40所顯示的點線切割總成。如此將橋接結構52自所構成的封裝分離，並使與閘極引線結構18及源極引線結構16非電耦合。由於僅需一回焊製程用以構成最終封裝，所以能夠快速並有效地構成封裝。同時，僅執行一回焊製程降低於焊料中構成金屬間化合物(intermetallic compound)的機會。重複加熱更可能形成金屬間化合物。金屬間化合物亦能夠造成易碎的焊接接頭並增加具缺陷焊接接頭的可能性。
第5圖係為第4圖中總成的一側視圖。如第5圖中所示，導線架結構18與引線部分14(c)係為相互共平面，並係配置位在一暫時基板34上。暫時基板34能夠以任一適合的材料構成。例如，暫時基板34可以捲帶構成。在構成封裝之後，可將暫時基板34去除。
第6圖係為本發明之一具體實施例的一導線架總成的一仰視圖。導線架總成包括一導線架結構18，其包括複數 之汲極引線18(a)以及一蝕刻部分18(c)。蝕刻部分18(c)可構成供半導體晶粒封裝所用的一汲極墊18(b)，並且最終地可焊接至一電路板(未顯示)。連接軌道20可將導線架結構18連接至一框架74。框架74可包括先前說明的軌道結構70及對準端部結構70(a)，並可界定一孔60。於封裝裝配期間，源極線夾結構(未顯示)之引線可存在於孔60中。
第7圖係顯示在切割之前的一線夾總成102。如第7圖中所示，一橋接結構52將源極線夾結構14之引線及閘極線夾結構18之引線耦合。如上述說明，橋接結構52係與閘極線夾結構18及源極線夾結構14分離，並且在構成的半導體晶粒封裝中其相互間非電耦合。第7圖中之其他元件已於先前加以說明。
第8圖係為本發明之一具體實施例的一線夾結構14的一側視圖。如第8圖中所示，台座14(a)-1類似一平頂山結構(mesa structure)。然而，於其他具體實施例中，台座可為圓錐狀、圓筒狀、或可具有任一其他突出的形狀。同時，介於主要部分14(a)之一底部表面與引線部分14(c)之底部表面之間的凹壓高度可以高度D代表。於較佳的具體實施例中，凹壓高度約為導線架結構18之厚度或是線夾結構14之厚度的2倍(或更多)。於一些具體實施例中，導線架結構18及/或線夾結構14之厚度能夠大於約100微米。
如第9圖中所示，台座14(a)-1之高度可約為50微米，同時台座之寬度可約為150微米。當然，於本發明之其他具體實施例中其他台座的尺寸可為不同。
第10圖係為包括一金屬氧化半導體場效電晶體(MOSFET)晶粒82及一肖特基二極體晶粒(Schottky diode die)84的一半導體晶粒封裝202。線夾總成102包括於MOSFET晶粒82中與源極之終端連接及閘極連接，以及對肖特基二極體晶粒84的輸入及/或輸出部分。如先前具體實施例中，線夾總成102可包括一橋接結構52，其係於對準結構70(a)之間對準。
第11圖顯示包括二金屬氧化半導體場效電晶體(MOSFET)晶粒82的一半導體晶粒封裝204。線夾總成102可包括於MOSFET晶粒82中與源極之終端連接及閘極連接。如先前具體實施例中，線夾總成102可包括一橋接結構52，其係於對準結構70(a)之間對準。
第12圖顯示本發明之另一具體實施例的一半導體晶粒封裝。此具體實施例係與第1圖中所示的具體實施例相似，不同之處在於位在封裝之頂部部分處的模塑材料20露出線夾結構14之上表面。如為所需，可將一散熱器(未顯示)附裝至線夾結構14之頂部表面14(f)。暴露的線夾結構表面14(f)實質上與模塑材料20之一外部表面20(b)共平面。暴露的線夾表面14(f)考量較佳的熱散逸，並亦導致一較薄的半導體晶粒封裝。暴露的線夾表面14(f)能夠藉由以捲帶或一成型鑄模，或是熟知此技藝之人士所熟知的任一其他適合的方法覆蓋表面，接著環繞半導體晶粒16將模塑材料20模塑而構成。第12圖中的其他特徵已於先前說明。
第13(A)-13(D)圖顯示如何裝配本發明之具體實施例之 半導體晶粒封裝。
第13(A)圖顯示半導體晶粒16黏合在導線架結構34上。導線架結構34可為導線架結構陣列或是導線架結構”群”。該導線架結構群可為一藉由軌道或相似元件連接在一起的2或1維的導線架結構陣列。如先前所說明，可使用焊料(例如，無鉛焊料)將半導體晶粒16黏合至導線架結構18。於製程中的此位置處，導線架結構18可配置在諸如捲帶的一暫時基板34上。如此進行用以覆蓋導線架結構18之底部表面，因此其未以一模塑材料覆蓋。於此，用以將導線架結構18黏合至半導體晶粒16所用的焊料尚未回焊。
第13(B)圖顯示安置位在半導體晶粒16上的線夾結構14。線夾結構14之凹壓部分並未顯示為階梯狀。然而，應瞭解的是，於其他具體實施例中，可使用具有階梯狀凹壓部分的線夾結構14。如於其他具體實施例中，線夾結構14可具有台座14(a)-1，自半導體晶粒16上的頂部表面隔開線夾結構14的主要部分。
於一些具體實施例中，焊料可沉積在半導體晶粒16之頂部表面上以及線夾結構14黏合於其上。可任擇地或附加地，焊料可沉積在線夾結構14上以及塗佈焊料的線夾結構可黏合至半導體晶粒16之頂部表面。
如以上提及，用以將半導體晶粒16黏合至導線架結構18的焊接材料，可與用以將線夾結構14黏合至半導體晶粒16的焊接材料相同或為不同。在將線夾結構14黏合至半導體晶粒16之後，用以將該等組件黏合在一起的焊接材料係 同時地回焊。適合的回焊加工狀況係為熟知此技藝之人士所熟知的。
第13(C)圖顯示執行一模塑製程之後的總成。可使用市售的模塑工具用以執行模塑製程。可使用諸如環氧樹脂模塑材料的模塑材料。
第13(D)圖顯示切單製程。於一切單製程中，結合在一起的半導體晶粒封裝100係相互隔開。為此目的可使用任一適合的切割工具。例如，可使用水噴柱、雷射、鋸等將半導體晶粒封裝相互分開。
本發明之具體實施例提供複數之優點。例如，本發明之具體實施例具有與其他型式之傳統式封裝相同的據用面積及引腳分配，同時亦顯現良好的電氣及熱性能。此外，本發明之具體實施例的方法可使用對準結構用以將半導體晶粒之頂部上的線夾結構與半導體晶粒之底部處的導線架結構對準。如此產生更為有效的加工作業，並且於本發明之具體實施例中不需執行覆晶黏合製程(flip chip attachment process)。同時，本發明之具體實施例係為堅固耐用的。於一些具體實施例中，半導體晶粒並未暴露至外在環境。
同時，於本發明之具體實施例中，能夠使用相同型式的焊膏或是傳導性黏著劑將導線架結構黏合至半導體晶粒之底部表面，以及將一或更多線夾結構黏合至半導體晶粒之頂部表面。針對晶粒黏合及線夾黏合二作業可執行一次焊膏回焊製程(one-time solder-paste reflow process)。由於在 此實例中僅需一回焊製程，所以能夠將焊接接頭中形成過多量之金屬間化合物的機會降至最低或是防止發生。同時，由於在此實例中僅需執行一回焊製程，所以不需具有不同熔點的二類型之無鉛焊料。
於傳統式加工作業中，晶粒係使用焊料黏合至導線架結構，並且焊料係經回焊。此外，線夾結構係黏合至半導體晶粒並亦係經回焊。介於晶粒與導線架結構之間的焊料係接受二加熱製程。如此增加加熱作業，因而增加形成金屬間化合物的機會。
上述說明係為說明性的並且不具限制性。熟知此技藝之人士一經檢閱揭示內容，本發明之複數變化形式將為顯而易見的。因此，不應相關於上述說明而確定本發明之範疇，取而代之地應相關於尚在申請中的申請專利範圍連同其之完整範疇或等效者而確定。再者，一或更多具體實施例的任一或更多特性能夠與任一其他具體實施例之一或更多特性結合，而不致背離本發明之範疇。例如，第10及11圖之具體實施例中的特性能夠與任一其他圖式中的任一其他具體實施例之特性結合，而不致背離本發明之範疇。
任何的參考位置，諸如”頂部”、”底部”、”上”、”下”等係參考圖式並係方便使用。其並不意欲與絕對位置相關。例如，儘管第1圖顯示一半導體晶粒封裝的一”底部”表面，但應瞭解的是能夠從旁邊、顛倒、放正地黏合半導體晶粒封裝，並仍涵蓋於申請專利範圍之範疇。
除非特別地另有相反之意，否則所列舉之”a”、”an” 或”the”係欲意指”一或更多”。
上述所有的專利、專利申請案、公開案及說明內容於此針對多用途以全文引用方式併入本案以為參考資料。無一者被認可為先前技術。
D‧‧‧凹壓高度
14‧‧‧源極線夾結構
14(a)‧‧‧主要部分
14(a)-1‧‧‧台座
14(b)‧‧‧凹壓部分
14(c)‧‧‧引線部分
14(f)‧‧‧頂部表面
16‧‧‧半導體晶粒
16(a)‧‧‧第一表面
16(b)‧‧‧第二表面
18‧‧‧導線架結構
18(a)-1‧‧‧閘極台座
18(a)‧‧‧第一表面/汲極引線
18(b)‧‧‧第二表面/汲極墊
18(c)‧‧‧部分/蝕刻部分
18(d)‧‧‧引線部分
18(e)‧‧‧墊部分
20‧‧‧模塑材料
20(a)‧‧‧底部外表面
20(b)‧‧‧外部表面
24‧‧‧焊接
28‧‧‧閘極線夾結構
34‧‧‧暫時基板/導線架結構
40‧‧‧點線
52‧‧‧橋接結構
60‧‧‧孔
70‧‧‧對準軌道結構
70(a)‧‧‧對準端部結構
74‧‧‧框架
82‧‧‧金屬氧化半導體場效電晶體(MOSFET)晶粒
84‧‧‧肖特基二極體晶粒
90‧‧‧焊接
100‧‧‧半導體晶粒封裝
100(a)‧‧‧第一側表面
100(b)‧‧‧第二側表面
100(c)‧‧‧頂部表面
100(d)‧‧‧底部表面
102‧‧‧線夾總成
202,204‧‧‧半導體晶粒封裝
第1圖係為本發明之一具體實施例的一晶粒封裝的一側橫截面視圖。
第2圖係為本發明之一具體實施例的一線夾結構中的一台座之一側橫截面視圖。
第3圖係為本發明之一具體實施例的一半導體晶粒封裝的一透視圖。
第4圖係為本發明之一具體實施例的一半導體晶粒封裝的一概略俯視圖。
第5圖係為本發明之一具體實施例的一半導體晶粒封裝的一側視圖。
第6圖係為本發明之一具體實施例的一導線架結構的一仰視圖。
第7圖係為本發明之一具體實施例的一線夾總成的一俯視圖。
第8圖係為本發明之一具體實施例的一線夾結構的一側橫截面視圖。
第9圖係為本發明之一具體實施例的一台座的一側橫截面視圖。
第10圖係為包括一金屬氧化半導體場效電晶體 (MOSFET)晶粒及一肖特基二極體晶粒(Schottky diode die)的一半導體晶粒封裝之一概略俯視圖。
第11圖係為包括二金屬氧化半導體場效電晶體(MOSFET)晶粒的一半導體晶粒封裝之一概略俯視圖。
第12圖係為本發明之另一具體實施例的一半導體晶粒封裝。於此具體實施例中，線夾結構及導線架結構二者之表面係通過一模塑材料而暴露。
第13(A)至13(D)圖係顯示當所有結構皆裝配於半導體晶粒封裝中時該等結構的側橫截面視圖。
14‧‧‧源極線夾結構
14(a)‧‧‧主要部分
14(a)-1‧‧‧台座
14(b)‧‧‧凹壓部分
14(c)‧‧‧引線部分
16‧‧‧半導體晶粒
16(a)‧‧‧第一表面
16(b)‧‧‧第二表面
18‧‧‧導線架結構
18(a)‧‧‧第一表面/汲極引線
18(b)‧‧‧第二表面/汲極墊
18(c)‧‧‧部分/蝕刻部分
18(d)‧‧‧引線部分
18(e)‧‧‧墊部分
20‧‧‧模塑材料
20(a)‧‧‧底部外表面
24‧‧‧焊接
90‧‧‧焊接
100‧‧‧半導體晶粒封裝
100(a)‧‧‧第一側表面
100(b)‧‧‧第二側表面
100(c)‧‧‧頂部表面
100(d)‧‧‧底部表面

Claims (42)

  1. 一種供用於半導體封裝的線夾結構(clip sturcture)，該線夾結構包含：一主要部分，包含一水平表面、複數個自該主要部分之水平表面延伸的台座、一相對於該等台座的凹表面；一凹壓部分；以及一引線部分，其中該凹壓部分係介於該引線部分與該主要部分之間。
  2. 如請求項1之線夾結構，其中該線夾結構係為一源極線夾結構或是一閘極線夾結構。
  3. 如請求項1之線夾結構，其中該凹壓部分包括一階梯狀構形。
  4. 一種半導體晶粒封裝，其包含：如申請專利範圍第1項所述之線夾結構；一半導體晶粒，其係與該線夾結構耦合；以及一模塑材料，其至少部分地覆蓋該線夾結構及該半導體晶粒。
  5. 如請求項4之半導體晶粒封裝，其進一步包含一導線架結構，其中該半導體晶粒係介於該導線架結構與該線夾結構之間。
  6. 如請求項4之半導體晶粒封裝，其中該半導體晶粒包含一垂直功率金屬氧化半導體場效電晶體(MOSFET)。
  7. 一種半導體晶粒封裝，其包含：一線夾結構，其包括一主要部分，該主要部分包含一水平表面、複數個自該主要部分之水平表面延伸的台座、一相對於該等台座的凹表面，一凹壓部分，以及一引線部分，其中該凹壓部分係介於該引線部分與該主要部分之間並且具有一階梯狀構形；一導線架結構；以及一半導體晶粒；其中半導體晶粒係介於該導線架結構與該線夾結構之間。
  8. 如請求項7之半導體晶粒封裝，進一步包含一模塑材料，其覆蓋該線夾結構、該導線架結構及該半導體晶粒的至少一部分。
  9. 一種半導體晶粒封裝，其包含：一線夾結構，其包括一主要部分，複數個自該主要部分延伸的台座，一相對於該等台座的凹表面，一凹壓部分，以及一引線部分，其中該凹壓部分係介於該引線部分與該主要部分之間並且具有一階梯狀構形；一導線架結構；以及一半導體晶粒；其中該半導體晶粒係介於該導線架結構及該線夾結構之間，其中該半導體晶粒封裝係為一微型導線架封裝(MLP)並且包含一功率金屬氧化半導體場效電晶體MOSFET。
  10. 如請求項5之半導體晶粒封裝，其中該線夾結構進一步包含一外部線夾結構表面，其中該外部線夾結構表面係經由該模塑材料而暴露並且實質上與一外部模塑材料表面共平面。
  11. 如請求項10之半導體晶粒封裝，其中該外部模塑材料表面係一第一外部模塑材料表面，且其中該導線架結構具有一導線架表面，該導線架表面與一第二外部模塑材料表面實質上共平面。
  12. 如請求項10之半導體晶粒封裝，其中該半導體晶粒係一第一半導體晶粒，且其中該半導體晶粒封裝更包含一耦合至該模塑材料的第二半導體晶粒。
  13. 如請求項12之半導體晶粒封裝，其中該模塑材料包含環氧樹脂模塑材料。
  14. 如請求項13之半導體晶粒封裝，其中該封裝更包含焊接件，且其中該焊接件接觸該半導體晶粒及該水平表面，並且也圍繞該台座。
  15. 如請求項5之半導體晶粒封裝，其中該封裝更包含焊接件，且該焊接件接觸該半導體晶粒及該水平表面，並且也圍繞該台座。
  16. 如請求項7之半導體晶粒封裝，其中該封裝更包含焊接件，且其中該焊接件接觸該半導體晶粒及該水平表面，並且也圍繞該台座。
  17. 如請求項16之半導體晶粒封裝，其中該晶粒包含一垂 直功率金屬氧化半導體場效電晶體(MOSFET)，其包含一槽溝閘極結構。
  18. 如請求項17之半導體晶粒封裝，其中該導線架結構包含銅。
  19. 如請求項5之半導體晶粒封裝，係更包含焊接件，其設置於環繞該等台座之至少一者並且接觸該水平表面及該晶粒，且其中該晶粒接觸該等台座。
  20. 如請求項7之半導體晶粒封裝，係更包含焊接件，其設置於環繞該等台座之至少一者並且接觸該水平表面及該晶粒，且其中該晶粒接觸該等台座。
  21. 一種形成半導體晶粒封裝的方法，該方法包含：獲得一線夾結構，該線夾結構包含一主要部分，複數台座，各個台座自該主要部分延伸，一相對於該等台座之凹表面，一凹壓部分以及一引線部分，其中該凹壓部分係介於該引線部分與該主要部分之間，其中該凹表面及各個台座係經由沖壓而形成；獲得一半導體晶粒；以及將該線夾結構接合至該半導體晶粒，其中該複數台座係面對該半導體晶粒。
  22. 如請求項21之方法，更包含將該半導體晶粒接合至一導線架結構，及將一模塑材料模塑於圍繞該半導體晶粒。
  23. 如請求項22之方法，其中該半導體晶粒封裝係在模塑之後而形成，且其中該半導體晶粒封裝係一無引線封 裝。
  24. 如請求項21之方法，其中該凹壓部分包含一階梯狀構形。
  25. 如請求項24之方法，其中該半導體晶粒包含一功率金屬氧化半導體場效電晶體(MOSFET)，其包含一槽溝閘極結構。
  26. 如請求項24之方法，其中該半導體晶粒係一第一半導體晶粒，該線夾結構係一第一線夾結構，且其中該方法更包含將一第二線夾結構接合至一第二半導體晶粒，以及接著將一模塑材料模塑於圍繞該第一半導體晶粒及該第二半導體晶粒。
  27. 如請求項24之方法，其中該半導體晶粒係一包含MOSFET的第一半導體晶粒，該線夾結構係一第一線夾結構，其中該方法係更包含將一第二線夾結構接合至一包含肖特基二極體的第二半導體晶粒，以及接著將一模塑材料模塑於圍繞該第一半導體晶粒及該第二半導體晶粒。
  28. 如請求項24之方法，包含將該半導體晶粒接合至一導線架結構，及將一模塑材料模塑於圍繞該半導體晶粒。
  29. 如請求項28之方法，其中該半導體晶粒封裝係在模塑之後而形成，且其中該半導體晶粒封裝係一無引線封裝。
  30. 如請求項28之方法，其中該導線架結構之厚度係大於約100微米。
  31. 如請求項30之方法，其中該線夾結構之厚度係大於約100微米。
  32. 如請求項21之方法，其中該等台座係為錐形。
  33. 一種製造半導體晶粒封裝的方法，該方法包含：獲得一線夾總成，該線夾總成包含一線夾結構包含一主要部分，複數台座，一相對於該等台座之凹表面，一凹壓部分以及一引線部分，其中該凹壓部分係介於該引線部分與該主要部分之間，且其中該凹表面及單一台座係經由沖壓而形成；獲得一結合至少一對準結構的導線架結構，其中在半導體晶粒封裝之裝配期間該對準結構將該線夾總成與該導線架結構對準；將一半導體晶粒之一第二表面接合至該導線架結構；以及將該半導體晶粒之一第一表面接合至該線夾結構，其中該半導體晶粒係一第一半導體晶粒，該線夾結構係一第一線夾結構；且其中該方法更包含將一第二線夾結構接合至一第二半導體晶粒，以及接著將一模塑材料模塑於圍繞該第一半導體晶粒及該第二半導體晶粒。
  34. 如請求項33之方法，其中該線夾總成及該導線架結構係為數組導線架結構及線夾總成的形式。
  35. 如請求項33之方法，其中該導線架結構包含二對準結構以及其中該線夾總成之一軌道係介於該二對準結構之間。
  36. 如請求項34之方法，其中該線夾總成及該導線架結構包含銅。
  37. 如請求項34之方法，其中該第一半導體晶粒包含一垂直功率MOSFET。
  38. 如請求項33之方法，其中將該第一半導體晶粒之第二表面接合至該導線架結構係包含使用一第一焊接材料，以及，將該線夾總成接合至該第一半導體晶粒之第一表面係包含使用一第二焊接材料，並且其中該方法更包含：於一單一回填製程中使該第一及第二焊接材料回填。
  39. 如請求項33之方法，更包含將該對準結構與該導線架結構分開。
  40. 如請求項21之方法，其中該第一半導體晶粒包含一槽溝閘極結構。
  41. 如請求項33之方法，其中該第一半導體晶粒包含一槽溝閘極結構。
  42. 如請求項33之方法，其中該第一半導體晶粒包含一MOSFET，並且該第二半導體晶粒包含一肖特基二極體。
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JP2009516389A (ja) 2009-04-16
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KR20080070068A (ko) 2008-07-29
WO2007061558A3 (en) 2009-04-23
JP2011223016A (ja) 2011-11-04
US8058107B2 (en) 2011-11-15
KR101410514B1 (ko) 2014-07-02
WO2007061558A2 (en) 2007-05-31
CN101495014B (zh) 2012-11-28
US20080044946A1 (en) 2008-02-21
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DE112006003036T5 (de) 2008-10-23
US20070114352A1 (en) 2007-05-24

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