CN101495014A - 使用引线框和夹片的半导体管芯封装及制造方法 - Google Patents

使用引线框和夹片的半导体管芯封装及制造方法 Download PDF

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Publication number
CN101495014A
CN101495014A CNA2006800430747A CN200680043074A CN101495014A CN 101495014 A CN101495014 A CN 101495014A CN A2006800430747 A CNA2006800430747 A CN A2006800430747A CN 200680043074 A CN200680043074 A CN 200680043074A CN 101495014 A CN101495014 A CN 101495014A
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Prior art keywords
clamping piece
semiconductor element
lead frame
piece structure
die package
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CN101495014B (zh
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E·V·R·克鲁兹
E·卡巴霍格
T·C·塞
V·艾耶
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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Abstract

公开了一种用于半导体封装的夹片结构。该夹片结构包括主要部分、至少一个从该主要部分延伸出来的基座、下移设置部分、以及引线部分。该下移设置部分在引线部分与主要部分之间。该夹片结构可用于MLP(微引线框封装)。

Description

使用引线框和夹片的半导体管芯封装及制造方法
背景技术
许多半导体管芯封装使用夹片代替导线形成与外部终端的外部连接。这种半导体管芯封装有时被称为“无线”封装。典型的无线封装包括附着于半导体管芯的夹片。无线封装通常具有比使用基于导线电连接的封装更佳的电性能和热性能。
通常，需要将常规的无线封装设计到消费者的电路板中，因为该电路板具有独特的覆盖区域和引线分配。提供具有能与常规的封装覆盖区域和引线分配对应的封装覆盖区域和引线分配，然而依然具有优良的电性能和热性能的半导体管芯是合乎需要的。
此外，当制造无线封装时，创造具有深下移设置(downset)的夹片(例如，源极夹片)经常是困难的。夹片的“下移设置”可以与该夹片的主要部分到该夹片的引线部分之间的垂直距离对应。提供具有比常规夹片更深的下移设置的夹片以便可以制造不同类型的封装也是合乎需要的。
另一存在的问题是在夹片与半导体管芯之间涂敷不一致的或不均匀量的焊料的问题。当在管芯和夹片之间使用不一致的或不均匀量的焊料时，所得封装可能显示出较差的性能。
除上述提到问题之外，提供可用来快速和可靠地制造半导体管芯封装的方法将是有益的。该方法也优选地与无铅工艺兼容。
本发明的各个实施方式解决上述问题及其它问题。
发明概要
本发明各个实施方式涉及夹片结构、包括该夹片结构的半导体管芯封装、以及制造包括夹片结构的半导体管芯封装的方法。
本发明的一个实施方式涉及用于半导体封装的夹片结构，该夹片结构包括：主要部分、至少一个从该主要部分延伸出来的基座、下移设置部分、以及引线部分，其中该下移设置部分在引线部分和主要部分之间。
本发明的另一实施方式涉及用于半导体封装的夹片结构，该夹片结构包括：主要部分、具有阶梯式构造的下移设置部分、以及引线部分，其中该下移设置部分在引线部分和主要部分之间。
本发明其它实施方式涉及包括上述夹片结构的半导体管芯封装，以及使用该夹片结构制造半导体管芯封装的方法。
本发明的又一实施方式涉及一种半导体管芯封装，包括：夹片结构，该夹片结构包括主要部分、至少一个从该主要部分延伸出来的基座、下移设置部分、以及引线部分，其中该下移设置部分在引线部分和主要部分之间，且具有阶梯式构造；引线框结构；以及半导体管芯，其中该半导体管芯在引线框结构和夹片结构之间。
本发明的又一实施方式涉及制造半导体管芯封装的方法，该方法包括：获得夹片组件；获得包括至少一个对准结构的引线框结构，其中该对准结构在半导体管芯封装的组装期间将夹片组件与引线框结构对准；将半导体管芯的第二表面附着到引线框结构；以及将该半导体管芯的第一表面附着到夹片组件。
以下对本发明的这些及其它实施方式进行进一步详细描述。
附图简要说明
图1示出根据本发明一实施方式的管芯封装的横截面侧视图。
图2示出根据本发明一实施方式的夹片结构中的基座的横截面侧视图。
图3示出根据本发明一实施方式的半导体管芯封装的透视图。
图4是示出根据本发明一实施方式的半导体管芯封装的示意性俯视图。
图5是根据本发明一实施方式的半导体管芯封装的侧视图。
图6示出根据本发明一实施方式的引线框结构的仰视图。
图7示出根据本发明一实施方式的夹片组件的俯视图。
图8示出根据本发明一实施方式的夹片结构的横截面侧视图。
图9示出根据本发明一实施方式的基座的横截面侧视图。
图10示出包括金属氧化物半导体场效应晶体管(MOSFET)管芯和肖特基二极管管芯的半导体管芯封装的示意性俯视图。
图11示出包括两个MOSFET管芯的半导体管芯封装的示意性俯视图。
图12示出根据本发明另一实施方式的半导体管芯封装。在此实施方式中，夹片结构的表面和引线框结构的表面都通过铸模材料暴露。
图13(a)到13(d)示出结构在都被装配到半导体管芯封装时的横截面侧视图。
详细描述
本发明实施方式可包括无线封装。根据本发明一实施方式的无线封装不使用导线来连接到半导体管芯中的电气器件的输入和/或输出端子。在其它实施方式中，该半导体管芯封装不需是无线的。例如，如下所示，本发明各个实施方式包括具有特定构造的独特的源极夹片结构。这种源极夹片结构可用在具有栅极线焊的半导体管芯封装。然而，无线半导体管芯封装是较佳的，因为它们通常具有比将导线用于端子连接的半导体管芯封装更佳的热性能和电性能。
在一个半导体管芯封装实施方式中，该半导体管芯封装包括夹片结构，该夹片结构包括主要部分、至少一个从该主要部分延伸的基座、“下移设置”部分、及引线部分。该“下移设置”部分在引线部分和主要部分之间，且可具有阶梯式构造。半导体管芯夹在夹片结构和引线框结构之间并附着到这两个结构。
在本发明各个实施方式中，第一焊料可用来将半导体管芯机械地和电气地连接到引线框结构。第二焊料可用来将半导体管芯机械地和电气地连接到夹片结构。该第一和第二焊料可以是相同的或不同的。它们优选地是相同的材料且可以包括无铅焊料。
图1示出根据本发明一实施方式的半导体管芯封装的横截面侧视图。该半导体管芯封装100包括半导体管芯16，该半导体管芯置于源极夹片结构14和引线框结构18之间。铸模材料20至少部分地覆盖半导体管芯16、夹片结构14、及引线框结构18。该铸模材料20可以是环氧铸模材料或任何其它适合的商业化可用的铸模材料。
如图1所示，该半导体管芯封装100还包括第一侧面100(a)和第二侧面100(b)，以及顶面100(c)和底面100(d)。
即使该所得半导体管芯封装100具有嵌入式引线，该半导体管芯封装100就引线不伸出该铸模材料20的侧面的意义而言可称作“无引线”封装。它还可以用块的形式，且该半导体管芯封装100在一些实施方式中还可以称作MLP(微引线框封装)类型封装。虽然在本申请中对无引线管芯封装进行了详细描述，但可以理解该夹片结构14还可以用于有引线管芯封装。
焊料24在半导体管芯16的第一表面16(a)与夹片结构14之间。焊料90也在半导体管芯16的第二表面16(b)与引线框结构18之间存在。
任何适合的焊料可以用作焊料24和焊料90。例如，铅锡焊料可用作焊料24和焊料90。优选地，焊料24和焊料90包括无铅焊料，诸如基于铟锡的焊料。此外，导电聚合物粘合剂(例如，导电环氧粘合剂)可代替焊料使用。
半导体管芯16可包括任何适合的半导体器件。适合的半导体器件可以包含半导体材料例如硅，且可以包括垂直的或水平的器件。垂直的器件至少在管芯一侧具有输入且在管芯另一侧具有输出使得电流可以垂直地流经管芯。水平的器件在管芯的一侧至少包括一个输入且在管芯的同一侧至少包括一个输出使得电流水平地流经管芯。该半导体管芯16的半导体器件优选地是垂直功率晶体管。
垂直功率晶体管包括垂直双扩散金属氧化物半导体(VDMOS)晶体管和垂直双极晶体管。VDMOS晶体管是具有两个或更多个由扩散形成的半导体区的MOSFET。它具有源极区、漏极区和栅极。该器件是垂直的，因为源极区和漏极区位于半导体管芯的相反表面。栅极可以是沟槽栅极结构或平面栅极结构，且与源极区在同一表面形成。沟槽栅极结构是优选的，因为沟槽栅极结构比平面栅极结构更窄且占据更少空间。在运行期间，在VDMOS器件中从源极区流向漏极区的电流与该管芯表面基本垂直。
在本示例中，该半导体管芯16包括垂直MOSFET。该垂直MOSFET包括在第一表面16(a)上的源极区和栅极区，以及在半导体管芯16的第二表面16(b)上的漏极区。该源极区可以具有源极金属(例如，可软焊顶层金属或焊料凸块)，且可以与夹片结构14(可以是源极夹片结构)电耦合。该栅极区可以与相应的栅极夹片结构(未示出)电耦合，而在该第二表面16(b)上的漏极区可以与引线框18电耦合。
该引线框结构18包括第一表面18(a)及第二表面18(b)。该引线框结构18还包括由蚀刻工艺形成的部分18(c)，以及焊盘部分18(e)和引线部分18(d)。该焊盘部分18(e)可以形成该引线框结构18的管芯附着焊盘(DAP)。
如图1所示，该引线部分18(d)不延伸超过铸模材料20，且与该铸模材料20的底部外表面20(a)基本共面。该半导体管芯封装100的第一侧面100(a)与铸模材料20的一个侧面和引线部分18(d)的一个侧面重合。该半导体管芯封装100的底面100(d)与引线框结构18的底面和铸模材料20的底部外表面重合。
引线框结构18的底部由铸模材料20暴露。该经暴露的引线框结构18的底面提供其它漏极连接以及其它用于半导体管芯封装100的冷却路径。
引线框结构18可以包含任何适合的材料。例如，引线框结构34可以包含铜、铜合金、或任何其它适合的导电材料。如需要，它还可以用可软焊金属电镀。
该夹片结构14可以具有任何适合的构造。在本示例中，该夹片结构14包括主要部分14(a)、引线部分14(c)，及“下移设置”部分14(b)。该“下移设置”部分14(b)被置于主要部分14(a)和引线部分14(c)之间。它包括阶梯式或Z字形结构。虽然在图1中示出一个“阶梯”，但在其它实施方式中，该夹片结构14可以包括多个阶梯。
夹片结构14可以包括任何适合的材料。例如，诸如铜、铝及贵金属(及其合金)的导电材料可用于该夹片结构14。如需要，该夹片结构14还可以用可软焊层电镀。
该夹片结构14的阶梯式下移设置部分14(b)提供许多优点。例如，该阶梯式结构容许引线部分14(c)的底面与引线框结构18的底面之间有更佳的对准容差。因为该下移设置部分14(b)被弯曲，所以它可以比非阶梯式下移设置部分弯曲得更多。这允许引线部分14(c)与引线框结构18的底面更容易对准。此外，该阶梯式下移设置部分14(b)还允许夹片结构14具有比常规的夹片结构更深的下移设置。
在该夹片结构14中，多个分立基座14(a)-1向下延伸且与该夹片结构14的主要部分14(a)的水平表面垂直。基座14(a)-1在图2中更清楚地示出。如图所示，该基座14(a)-1的端部可以与半导体管芯16的第一表面16(a)，及围绕该基座的焊料24接触。与该基座14(a)-1相反的夹片结构14的表面微凹。此凹结构和该对应基座14(a)-1可由例如冲压工艺形成。虽然对冲压工艺进行了描述，但根据本发明实施方式的基座可通过本技术领域普通技术人员所知的任一适合方法形成。例如，基座可通过对该夹片结构进行刻蚀使得适当突起形成来在平面夹片结构上形成。此外，突起可通过在夹片结构的平面上电镀或放置导电柱形成。
夹片结构14中的基座14(a)-1提供许多优点。例如，它们在源极夹片结构14的主要部分14(a)的底面与半导体管芯16的第一表面16(a)之间提供一致的间隔。因为在夹片结构14的主要部分14(a)与半导体管芯的第一表面16(a)之间有一致的间隔，所以在它们之间总是存在一致量的焊料。过剩的焊料(如果有的话)可以从夹片结构14与半导体管芯16之间挤出。除了提供更一致的焊料沉积之外，基座14(a)-1还为夹片结构14提供更大的附着表面积，从而在源极夹片结构14与半导体管芯16之间提供更好的接合及更好的电连接。基座14(a)-1还防止夹片结构14产生不期望有的“倾斜”。如果基座14(a)-1不存在，则夹片会“倾斜”，从而导致焊料在半导体管芯16顶面上不均匀的涂敷。
图3示出根据本发明一实施方式的半导体管芯封装的透视图。在此附图中，铸模材料未示出。如图3所示，该半导体管芯封装可以包括源极夹片结构14和栅极夹片结构28。栅极夹片结构28与源极夹片结构14相互电解耦合。如下将非常详细地进行解释，源极夹片结构14和栅极夹片结构28可以从夹片组件中获得。在图3中，与图1中一样，半导体管芯16夹在源极夹片结构14和引线框结构18中间。此外，如图3所示，半导体管芯16还夹在栅极夹片结构28与引线框结构18之间。与源极夹片结构14类似，栅极夹片结构28还可以包括一个或多个基座(未示出)以提供一致的焊料沉积。
图4示出封装组件中的半导体管芯封装的俯视图。参考标记40指示的虚线示出该组件的何处将用锯或类似物进行切削。在切削之前，栅极夹片结构18和源极夹片结构14由桥结构52连接。桥结构52将栅极夹片结构18和源极夹片结构14的引线进行电连接和机械性连接。另外，在切削之前，引线框结构18是包括对准导轨结构70的引线框组件的一部分。对准导轨结构70包括两个对准端部结构70(a)。在此示例中，对准端部结构70(a)是金属方块形式，但是在本发明的其它实施方式中可以具有其它形状。对准端部结构70(a)限制桥结构52以使得夹片组件102与半导体管芯16的端子完全对准。具体地，源极夹片结构14和源极夹片结构基座14(a)-1自动对准使得它们与半导体管芯16中的MOSFET的源极端子电耦合。同时，栅极夹片结构18和栅极基座18(a)-1自动对准使得它们与半导体管芯16中的MOSFET的栅极端子电耦合。此对准工艺使用一个步骤，从而节省工艺时间和成本。
一旦夹片组件102和引线框结构18使用焊料附着到半导体管芯，所得组件就可以经受回流工艺以使封装中的所有焊料同时回流。然后铸模材料可以在密封工艺中在管芯周围形成。然后，组件可以沿参考标记40示出的虚线切削。这将桥结构52从成形封装中分离且将栅引线结构18与源极引线结构16电解耦合。既然形成所得封装只需一次回流工艺，那么封装可以快速且有效地形成。此外，只执行一次回流工艺减少在焊料中形成金属间化合物的几率。金属间化合物更可能随反复加热形成。金属间化合物还可以导致脆性焊料接合点且增大缺陷焊料接合点的可能性。
图5从侧面示出图4的组件。如图5所示，引线框结构18和引线部分14(c)相互共面且置于临时衬底34上。临时衬底34可由任何适合的材料制成。例如，临时衬底34可由柔韧带(tape)制成。在封装形成后，临时衬底34可以被除去。
图6示出根据本发明一实施方式的引线框组件的仰视图。引线框组件包括引线框结构18，引线框结构18包括多条漏极引线18(a)、以及经蚀刻部分18(c)。经蚀刻部分18(c)可以形成半导体管芯封装的漏极焊盘18(b)并且最终焊接到电路板(未示出)。连接导轨20可将引线框结构18与框架74连接。框架74可包括前述导轨结构70和对准端部结构70(a)，且可以限定孔60。源极夹片结构的引线(未示出)可在封装组件期间在孔60中存在。
图7示出切削前的夹片组件102。如图7所示，桥结构52使源极夹片结构14的引线与栅极夹片结构18的引线耦合。如以上所说明地，桥结构52是从栅极夹片结构18和源极夹片结构14中分离出来的，且它们在成形的半导体管芯封装中相互电解耦合。先前已对图7中的其它元件进行了描述。
图8示出根据本发明一实施方式的夹片结构14的侧视图。如图8所示，基座14(a)-1类似台面结构。然而，在其它实施方式中，基座可以是锥形的、圆柱形的，或可以是任何其它突出形状。此外，在主要部分14(a)的底面与引线部分14(c)的底面之间的下移设置高度可由高度D指示。在优选实施方式中，下移设置高度可约是引线框结构18的厚度或夹片结构14的厚度的两倍(或更多)。引线框结构18和/或夹片结构14的厚度在一些实施方式中可约大于100微米。
如图9所示，基座14(a)-1的高度可约是50微米，而基座的宽度可近似是150微米。当然，在本发明其它实施方式中的其它基座的尺寸可以不同。
图10示出包括MOSFET管芯82和肖特基二极管管芯84的半导体管芯封装202。夹片组件102可以包括在MOSFET管芯82中的端子连接到源极和栅极连接以及到肖特基二极管管芯84的输入和/或输出。与之前的实施方式一样，夹片组件102可包括在对准结构70(a)之间对准的桥结构52。
图11示出包括两个MOSFET管芯82的半导体管芯封装204。夹片组件102可以包括在MOSFET管芯82中的端子连接到源极和漏极连接。与之前的实施方式一样，夹片组件102可包括在对准结构70(a)之间对准的桥结构52。
图12示出根据本发明另一实施方式的半导体管芯封装。此实施方式与图1示出的实施方式类似，其不同之处在于封装顶部的铸模材料20使夹片结构14的上表面暴露。如果需要，散热片(未示出)可以附着到夹片结构14的顶面14(f)。所暴露的夹片结构表面14(f)与铸模材料20的外表面20(b)基本共面。所暴露的夹片表面14(f)可实现更佳的热消散且还获得更薄的半导体管芯封装。经暴露的夹片表面14(f)可由用柔韧带或铸模管芯覆盖表面，或任何其它本领域技术人员已知的适合方法形成，然后将铸模材料20浇铸在半导体管芯16周围。先前已对图12中的其它特征进行了描述。
图13(a)到13(d)示出如何装配根据本发明实施方式的半导体管芯封装。
图13(a)示出安装在引线框结构34上的半导体管芯16。引线框结构34可以是引线框结构阵列或“组”。该组可以是由导轨或类似的连接在一起的引线框结构的2维或1维阵列。如前所述，焊料(例如，无铅焊料)可以用于将半导体管芯16附着到引线框结构18。在工艺的这一点上，引线框结构18可置于例如柔韧带的临时衬底34上。这样做是为了覆盖引线框结构18的底面以使其不被铸模材料覆盖。在这一点上，用于将引线框结构18附着到半导体管芯16的焊料还未回流。
图13(b)示出置于半导体管芯16上的夹片结构14。夹片结构14的下移设置部分未被示为是阶梯式的。然而，可以理解，在其它实施方式中，可使用有阶梯式下移设置部分的夹片结构14。与在其它实施方式中一样，夹片结构14可以具有将夹片结构14的主要部分与半导体管芯16的顶面隔开的基座14(a)-1。
在一些实施方式中，焊料可以沉积在半导体管芯16的顶面且夹片结构14可安装在其上。或者，焊料可以沉积在夹片结构14上且被焊料涂覆的夹片结构可以附着到半导体管芯16的顶面。
如以上所提及地，用于将半导体管芯16附着到引线框结构18的焊料可以与将夹片结构14附着到半导体管芯16的焊料相同或不同。在将夹片结构14附着到半导体管芯16之后，用于将这些组件附着到一起的焊料同时回流。适合的回流工艺条件为本领域普通技术人员所知。
图13(c)示出执行完浇铸工艺之后的组件。商业化可用的铸模工具可用来执行浇铸工艺。可以使用例如环氧铸模材料的铸模材料。
图13(d)示出切割工艺。在切割工艺中，连接在一起的半导体管芯封装100相互分离。任何适合的切削工具可用来实现此目的。例如，可以使用喷水口、激光、锯等将半导体管芯封装互相分离。
本发明的各个实施方式提供许多优点。例如，本发明的各个实施方式可以具有与其它常规的封装类型相同的覆盖区域和引线分配，然而还展现好的电性能和热性能。此外，根据本发明各个实施方式的方法可以使用对准结构将半导体管芯顶部的夹片结构与半导体管芯底部的引线框结构对准。此导致更有效的工艺，且在本发明实施方式中不需要执行倒装附着工艺。此外，本发明各个实施方式是鲁棒的。在一些实施方式中，半导体管芯不用暴露在环境中。
此外，在本发明的各个实施方式中，相同类型的焊膏或导电粘合剂可用于将引线框结构附着到半导体管芯的底面，且将一个或更多夹片结构附着到半导体管芯的顶面。一次焊膏回流工艺可以既对管芯附着又对夹片附着执行。因为在此示例中只需要一次回流工艺，因此在焊料接合点中的过多量金属间化合物的形成被最小化或防止。此外，因为在此示例中只需执行一次回流工艺，所以不需要具有不同熔点的两种类型的无铅焊料。
在常规的工艺处理中，管芯使用焊料附着到引线框结构且焊料回流。然后，夹片结构附着到半导体管芯且也回流。在管芯与引线框结构之间的料经受两次加热工艺。此加热的增加增大了金属间化合物可能形成的几率。
以上说明是示例性的而非限制性的。本发明的许多变体对本领域的技术人员在仔细查看本发明内容后是显而易见的。因此，本发明的范围不应参考以上说明来确定，而是应参考所附权利要求及它们的全部范围或等效方案来确定。此外，任何一个或更多个实施方式的一个或更多个特征可在不背离本发明的范围的情况下与任何其它实施方式的一个或更多个特征进行组合。例如，图10和图11的实施方式中的特征可在不背离本发明的范围的情况下与任何其它附图的任何其它实施方式的特征进行组合。
任何对诸如“顶部”、“底部”、“上部”、“下部”等位置的引用参考附图且用于提供方便。它们不是旨在指绝对位置。例如，虽然图1示出半导体管芯封装的“底”表面，但可以理解该半导体管芯封装可以向侧面、倒置、或正面朝上安装且仍在权利要求的范围之内。
“一”、“一个”或“该”的叙述旨在表示“一个或更多”除非具体指定为相反情况。
为了所有目的通过引用以上提及的所有专利、专利申请、公开及说明在此完整纳入。没有一项被认为属于现有技术。

Claims (26)

1.一种半导体封装的夹片结构，所述夹片结构包括：
主要部分；
至少一个从所述主要部分延伸出来的基座；
下移设置部分；以及
引线部分，
其中所述下移设置部分在所述引线部分和所述主要部分之间。
2.如权利要求1所述的夹片结构，其特征在于，所述夹片结构是源极夹片结构或栅极夹片结构。
3.如权利要求1所述的夹片结构，其特征在于，所述下移设置部分包括阶梯式构造。
4.一种半导体管芯封装，包括：
如权利要求1所述的夹片结构；
与所述夹片结构耦合的半导体管芯；以及
至少部分地覆盖所述夹片结构和所述半导体管芯的铸模材料。
5.如权利要求4所述的半导体管芯封装，进一步包括引线框结构，其中所述半导体管芯在所述引线框结构与所述夹片结构之间。
6.如权利要求4所述的半导体管芯封装，其特征在于，所述半导体管芯包括垂直功率MOSFET。
7.一种用于半导体封装的夹片结构，所述夹片结构包括：
主要部分；
下移设置部分，其中所述下移设置部分包括阶梯式构造；以及
引线部分，
其中所述下移设置部分在所述引线部分与所述主要部分之间。
8.如权利要求7所述的夹片结构，其特征在于，所述夹片结构是源极夹片结构。
9.如权利要求7所述的夹片结构，其特征在于，所述夹片结构包含铜。
10.一种半导体管芯封装，包括：
如权利7所述的夹片结构；
与所述夹片结构耦合的半导体管芯；以及
至少部分地覆盖所述夹片结构和所述半导体管芯的铸模材料。
11.如权利要求10所述的半导体管芯封装，进一步包括引线框结构，其中所述半导体管芯在所述引线框结构与所述夹片结构之间。
12.如权利要求10所述的半导体管芯封装，其特征在于，所述半导体管芯包括功率MOSFET。
13.一种半导体管芯封装，包括：
夹片结构，包括主要部分、至少一个从所述主要部分延伸出来的基座、下移设置部分、以及引线部分，其中所述下移设置部分在所述引线部分与所述主要部分之间，且具有阶梯式构造；
引线框结构；以及
半导体管芯，
其中所述半导体管芯在所述引线框结构与所述夹片结构之间。
14.如权利要求13所述的半导体管芯封装，进一步包括覆盖所述夹片结构、所述引线框结构、以及所述半导体管芯的至少一部分的铸模材料。
15.如权利要求13所述的半导体管芯封装，其特征在于，所述半导体管芯封装是MLP(微引线框封装)且包括功率MOSFET。
16.一种形成半导体管芯封装的方法，所述方法包括：
获得包括主要部分、至少一个从所述主要部分延伸出来的基座、下移设置部分、以及引线部分的夹片结构，其中所述下移设置部分在所述引线部分与所述主要部分之间；
获得半导体管芯；以及
将所述夹片结构附着到所述半导体管芯，其中至少一个所述基座面对所述半导体管芯。
17.如权利要求16所述的方法，进一步包括：
将所述半导体管芯附着到引线框结构；以及
将在所述半导体管芯周围浇铸铸模材料。
18.一种形成半导体管芯封装的方法，所述方法包括：
获得包括主要部分、下移设置部分、以及引线部分的夹片结构，其中所述下移设置部分在所述引线部分与所述主要部分之间，且包括阶梯式构造；
获得半导体管芯；以及
将所述夹片结构附着到所述半导体管芯。
19.如权利要求18所述的方法，包括：
将所述半导体管芯附着到引线框结构；以及
在所述半导体管芯周围浇铸铸模材料。
20.一种制造半导体管芯封装的方法，所述方法包括：
获得夹片组件；
获得与至少一个对准结构相关联的引线框结构，其中所述对准结构在装配半导体管芯封装期间将所述夹片组件与所述引线框结构对准；
将半导体管芯的第二表面附着到所述引线框结构；以及
将所述半导体管芯的第一表面附着到所述夹片组件。
21.如权利要求20所述的方法，其特征在于，所述夹片组件和所述引线框结构在引线框结构组和夹片组件中存在。
22.如权利要求20所述的方法，其特征在于，所述引线框结构至少包括两个对准结构，所述夹片组件的导轨在所述两个对准结构之间。
23.如权利要求20所述的方法，其特征在于，所述夹片组件和所述引线框结构包含铜。
24.如权利要求20所述的方法，其特征在于，所述半导体管芯包括垂直功率MOSFET。
25.如权利要求20所述的方法，其特征在于，将所述半导体管芯的第二表面附着到所述引线框结构包括使用第一焊料，且将所述夹片组件附着到所述半导体管芯的第一表面包括使用第二焊料，且其中所述方法进一步包括：
在单个回流工艺中使所述第一和第二焊料回流。
26.如权利要求20所述的方法，进一步包括：
将所述对准结构从所述引线框结构分离。
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US7285849B2 (en) 2007-10-23
US8058107B2 (en) 2011-11-15
KR20080070068A (ko) 2008-07-29
TW200729442A (en) 2007-08-01
CN101495014B (zh) 2012-11-28
DE112006003036T5 (de) 2008-10-23
WO2007061558A3 (en) 2009-04-23
US20070114352A1 (en) 2007-05-24
JP2011223016A (ja) 2011-11-04
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TWI447876B (zh) 2014-08-01
WO2007061558A2 (en) 2007-05-31

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