CN111261596A - 利用多个夹件结构的半导体封装及其制造方法 - Google Patents

利用多个夹件结构的半导体封装及其制造方法 Download PDF

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CN111261596A
CN111261596A CN201811466298.XA CN201811466298A CN111261596A CN 111261596 A CN111261596 A CN 111261596A CN 201811466298 A CN201811466298 A CN 201811466298A CN 111261596 A CN111261596 A CN 111261596A
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clip
main
clamping piece
semiconductor chip
connecting strip
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崔伦华
崔淳性
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Jamite Korea Kk
JMJ Korea Co Ltd
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Abstract

本发明公开了利用多个夹件结构的半导体封装及其制造方法，更具体地，半导体芯片的源极及漏极领域连接主夹件并且栅极领域连接副夹件而提高散热性能及电性连接性能，尺寸小于主夹件的副夹件能实现轻易结合。该半导体封装包括：导线架，由引脚与芯片座构成；半导体芯片，连结在芯片座的上部，上部由形成有源极或漏极端子的主领域和形成有栅极端子的副领域构成；主夹件，和半导体芯片的主领域及导线架的引脚连接；副夹件，和半导体芯片的副领域及导线架的引脚连接；封装主体，为保护半导体芯片而通过注塑予以包裹；在主夹件的一侧延伸出第一连接条，在副夹件的一侧延伸出第二连接条，第一连接条与第二连接条具有朝封装主体的外侧方向延伸而使得端部各自暴露的形态。

Description

利用多个夹件结构的半导体封装及其制造方法
技术领域
本发明涉及一种利用多个夹件结构的半导体封装及其制造方法，更具体地，半导体芯片的源极(source)及漏极(drain)领域连接主夹件并且栅极(gate)领域连接副夹件而提高散热性能及电性连接性能，尺寸小于主夹件的副夹件能轻易结合。
背景技术
半导体芯片封装通常包括半导体芯片、导线架(Lead Frame)及封装主体地构成，半导体芯片附接在导线架的芯片座上并且通过键合接线(B-W)电性连接到导线架的引脚。
然而，人们为了让制造工艺相比于基于键合接线的半导体芯片封装单纯并且改善散热性能及电气特性而近来开发了不使用键合接线而以夹件结构(clip structure)替代的技术。不仅如此，还要求在一个半导体封装的主体内部把2个以上的半导体芯片与夹件予以叠层以便提高半导体封装的容量。
因此，本发明人所揭示的韩国专利第10-1906470号(叠层式夹件键合半导体封装)、韩国专利第10-1652423号(压爪夹件键合半导体封装)揭示了结合多个夹件的技术。
上述现有技术由于半导体芯片的栅极领域具备较宽的面积而得以在制造过程中通过贴装设备把独立连接到该部分的夹件结构予以贴装，但是在具备小尺寸栅极领域的半导体芯片的情形下，连接到该部分的夹件结构也非常小而在制造过程中通过贴装设备握持夹件结构并予以举起在技术上非常困难。
因此，小型半导体芯片的栅极领域无法适用夹件结构，从而不得不通过键合接线实现电性连接。
发明内容
本发明旨在解决上述问题，本发明的目的是提供一种利用多个夹件结构的半导体封装及其制造方法，即使在小型半导体芯片的栅极领域也能和其它源极或漏极领域一样地适用夹件结构，提升电性连接特性，通过夹件结构进一步提高散热性能。
本发明包括：导线架，由引脚与芯片座(pad)构成；半导体芯片，连结在上述芯片座的上部，上部由形成有源极或漏极端子的主领域和形成有栅极端子的副领域构成；主夹件，和上述半导体芯片的主领域及导线架的引脚连接；副夹件，和上述半导体芯片的副领域及导线架的引脚连接；封装主体，为了保护上述半导体芯片而通过注塑予以包裹；在上述主夹件的一侧延伸出第一连接条(tie bar)，在副夹件的一侧延伸出第二连接条，上述第一连接条与第二连接条的形态是往封装主体的外侧方向延伸而使得端部各自暴露。
而且，上述主夹件及副夹件包括和上述半导体芯片的上表面连结的芯片接触部、和上述导线架的引脚连结的下端接合(down set)部、连接上述芯片接触部与下端接合部的连接部。
而且，上述主夹件及副夹件以下端接合部相对于连接部折弯的形态构成而使得形成于上述下端接合部末端部的一个角部面对引脚的表面，在上述下端接合部与连接部之间的折弯部分的外侧形成凹入形态的切口而防止回弹现象。
而且，上述主夹件及副夹件让下端接合部的接触部分可构成平坦面地形成而上述下端接合部的上部形成有与其对应的凹入形态的切口，第一连接条及第二连接条从下端接合部延伸形成。
本发明的利用多个夹件结构的半导体封装的制造方法包括下列步骤：准备主夹件与副夹件连接成一体状态的夹件材料；把半导体芯片连结到导线架的芯片座；通过导电性粘合剂把夹件材料的主夹件与副夹件对准各领域地附接在上述连结的半导体芯片的上部；在附接了上述夹件材料的状态下进行注塑而形成封装主体；把上述封装主体的一侧和夹件材料一起切割地清除主夹件与副夹件的连接部分而予以个别化。
而且，在准备上述夹件材料的步骤中，夹件材料在主夹件的一侧延伸出第一连接条而在副夹件的一侧延伸出第二连接条，还包括连接上述第一连接条与第二连接条的第三连接条。
而且，上述夹件材料为复数个并且以按照一定间距排列在边框(side r ail)内部的形态构成，上述夹件材料与边框通过第四连接条连接。
本发明把过去无法适用于小型半导体芯片的栅极领域的夹件结构予以适用而得以提高电性连接特性，凭借夹件结构进一步提高散热性能，从而提高产品的可靠度。
附图说明
图1是示出本发明的利用多个夹件结构的半导体封装的内部结构配置的俯视剖视图。
图2是剖切图1的A-A'线后示出的剖视图。
图3是剖切图1的B-B'线后示出的剖视图。
图4是示出本发明的主夹件与副夹件的初始状态的图形。
图5是示出本发明的利用多个夹件结构的半导体封装的另一个实施例的图形。
图6是剖切图5的C-C'线后示出的剖视图。
图7是示出适用于图5所示实施例的主夹件与副夹件的初始状态的图形。
图8至图12是按照顺序示出的本发明的制造方法的图形。
图13是示出本发明的制造方法中所使用的夹件材料连接到边框内部的形态的实施例的图形。
图14至15是示出本发明的半导体封装通过额外的半导体芯片构成叠层结构的另一个实施例的图形。
符号说明
S：粘合层
100：导线架 110：引脚
120：芯片座 200：半导体芯片
210：主领域 220：副领域
250：第二半导体芯片 300：主夹件
400：副夹件 310、410：芯片接触部
320、420：下端接合部 330、430：连接部
340、440：切口 500：封装主体
600：第一连接条 700：第二连接条
800：第三连接条 900：第四连接条
999：边框
具体实施方式
下面接合附图详细说明本发明的优选实施例。在说明本发明时，如果认为公知结构或功能的相关说明可能会非必要地混淆本发明的主旨，将省略其详细说明。
本发明涉及一种利用多个夹件结构的半导体封装，如图1至图3所示，其包括：导线架100，由引脚110与芯片座120构成；半导体芯片200，连结在上述芯片座120的上部，上部由形成有源极或漏极端子的主领域210和形成有栅极端子的副领域220构成；主夹件300，和上述半导体芯片200的主领域210及导线架100的引脚110连接；副夹件400，和上述半导体芯片200的副领域220及导线架100的引脚110连接；封装主体500，为了保护上述半导体芯片200而通过注塑予以包裹。而且，在上述主夹件300的一侧延伸出第一连接条600，在副夹件400的一侧延伸出第二连接条700，上述第一连接条600与第二连接条700具有往封装主体500的外侧方向延伸而使得端部各自暴露的形态。
本发明的包括半导体芯片200在内的各构成要素的电性连接是由导电性粘合剂构成的粘合层连结的，这是公知技术，因此将省略其具体说明。
本发明的半导体芯片200可分为主领域210与副领域220。主领域210相当于源极或漏极端子中一个以上的端子所构成的领域，其占据了半导体芯片200的较多领域。而且，副领域220是形成有栅极端子的领域，其相对于主领域210来说是较少领域。
连接在上述半导体芯片200的夹件结构是由主夹件300与副夹件400构成的。上述主夹件300和半导体芯片200的主领域210及源极或漏极引脚110进行电性连接，副夹件400和副领域220及栅极引脚110进行电性连接。副夹件400的尺寸和主夹件300的尺寸相比相对较小。
本发明的特征之一为，该主夹件300与副夹件400各自进一步形成连接条(Tiebar)。亦即，上述主夹件300的一侧进一步延伸形成第一连接条600，在副夹件400的一侧延伸形成第二连接条700。如此形成的第一连接条600与第二连接条700往各自的各个封装主体500的外侧方向延伸，是第一连接条600及第二连接条700的端部暴露于封装主体500外部的形态。
如前所述地，第一连接条600及第二连接条700的端部暴露于封装主体500的外部，因此能轻易实现主夹件300与副夹件400散热。
上述主夹件300及副夹件400包括和上述半导体芯片200的上表面连结的芯片接触部310、410、和上述导线架100的引脚110连结的下端接合部320、420、连接上述芯片接触部310、410与下端接合部320、420的连接部330、430。
本发明的主夹件300与副夹件400主要以两种形态的实施例构成。首先，如图1至图4所示，第一实施例以下端接合部320、420相对于连接部330、430折弯(bending)的形态构成以便让形成于上述下端接合部320、420末端部的一个角部面对引脚110的表面。此时，下端接合部320、420弯曲的折弯角度可以多样化，优选地，介于30至90度的角度范围地构成。
上述下端接合部320、420与连接部330、430之间的折弯部分在外侧形成凹入形态的切口(notch)340、440而得以在下端接合部320、420折弯的过程中防止凭借本身弹性使得弯曲状态被复原的回弹(spring back)现象。
如图5至图7所示，上述主夹件300与副夹件400的第二实施例中，让下端接合部320、420的接触部分可构成平坦面地形成，上述下端接合部320、420的上部形成有与其对应的凹入形态的切口340、440，第一连接条600及第二连接条700从下端接合部320、420延伸形成。上述第二实施例的切口340、440则可视为用来形成下端接合部320、420的构成要素。
第二实施例与第一实施例的差异除了下端接合部320、420的形状不同以外，还在于，第一实施例的第一连接条600及第二连接条700只在夹件的芯片接触部310、410延伸，第二实施例则是第一连接条600及第二连接条700在下端接合部320、420延伸的结构。
而且，图14至图15示出了本发明的利用多个夹件结构的半导体封装的再一个实施例，为了构成叠层结构，在主夹件300的上部贴装第二半导体芯片250而在第二半导体芯片250的上部则通过额外的夹件结构连接到另一个引脚110。
下面说明如前所述地构成的本发明的制造方法。如图8至图12所示，本发明的制造方法包括下列步骤：步骤S-1，准备主夹件与副夹件连接成一体状态的夹件材料；步骤S-2，把半导体芯片连结到导线架的芯片座；步骤S-3，通过导电性粘合剂把夹件材料的主夹件与副夹件对准各领域地附接在上述连结的半导体芯片的上部；步骤S-4，在附接了上述夹件材料的状态下进行注塑而形成封装主体；步骤S-5，把上述封装主体的一侧和夹件材料一起切割地清除主夹件与副夹件的连接部分而予以个别化。
如图8所示，准备上述夹件材料的步骤S-1是一种准备主夹件300与副夹件400连接成一体的状态的夹件材料的过程。副夹件400的尺寸相比于主夹件300非常小，因此个别准备时会在制造过程中无法握持并移动副夹件400。
在准备上述夹件材料的步骤S-1中，如图所示，夹件材料在主夹件300的一侧延伸出第一连接条600而在副夹件400的一侧延伸出第二连接条700，还包括连接上述第一连接条600与第二连接条700的第三连接条800。
与此同时，利用上述夹件材料批量生产半导体封装时，能如图13所示形态的实施例实现。亦即，夹件材料为复数个并且以按照一定间距排列在边框999内部的形态构成，成为上述夹件材料与边框999通过第四连接条900连接的形态。
然后，如图9所示，通过把半导体芯片200连结到导线架100的芯片座120的步骤S-2备妥连结了半导体芯片200的状态的导线架100。如此连结的半导体芯片200则由形成有源极或漏极端子的主领域210和形成有栅极端子的副领域220构成。
然后，如图10所示，进行步骤S-3，亦即，通过导电性粘合剂把夹件材料的主夹件300与副夹件400对准各领域地附接在已连结的半导体芯片200的上部。在该过程中，主夹件300与副夹件400处于互相连接的形态，因此一起置放并且附接。
图11示出在附接了夹件材料的状态下进行注塑而形成封装主体500的步骤S-4，在该过程形成整体半导体封装的形状。一般半导体封装的制造工艺能在该过程结束，但本发明还进行步骤S-5，亦即，如图12所示，把上述封装主体500的一侧和夹件材料一起切割而清除主夹件300与副夹件400的连接部330、430部分而予以个别化。该过程通过切割装置实现，主夹件300与副夹件400的连接部330、430部分，亦即，第三连接条800被切割而第一连接条600与第二连接条700的端部暴露于封装主体500的外部。
前文接合上述实施例对本发明进行了说明，但是在本发明的技术思想范畴内可实行各种变形。

Claims (7)

1.一种利用多个夹件结构的半导体封装，其特征在于，
包括：
导线架，由引脚与芯片座构成；
半导体芯片，连结在上述芯片座的上部，上部由形成有源极或漏极端子的主领域和形成有栅极端子的副领域构成；
主夹件，和上述半导体芯片的主领域及导线架的引脚连接；
副夹件，和上述半导体芯片的副领域及导线架的引脚连接；
封装主体，为了保护上述半导体芯片而通过注塑予以包裹；
在上述主夹件的一侧延伸出第一连接条，在副夹件的一侧延伸出第二连接条，上述第一连接条与第二连接条具有朝封装主体的外侧方向延伸而使得端部各自暴露的形态。
2.根据权利要求1所述的利用多个夹件结构的半导体封装，其特征在于，
上述主夹件及副夹件包括和上述半导体芯片的上表面连结的芯片接触部，和上述导线架的引脚连结的下端接合部，连接上述芯片接触部与下端接合部的连接部。
3.根据权利要求2所述的利用多个夹件结构的半导体封装，其特征在于，
上述主夹件及副夹件以下端接合部相对于连接部折弯的形态构成而使得形成于上述下端接合部末端部的一个角部面对引脚的表面，在上述下端接合部与连接部之间的折弯部分的外侧形成凹入形态的切口而防止回弹现象。
4.根据权利要求2所述的利用多个夹件结构的半导体封装，其特征在于，
上述主夹件及副夹件让下端接合部的接触部分可构成平坦面地形成，上述下端接合部的上部形成有与其对应的凹入形态的切口，第一连接条及第二连接条从下端接合部延伸形成。
5.一种利用多个夹件结构的半导体封装的制造方法，其特征在于，包括下列步骤：
步骤S-1，准备主夹件与副夹件连接成一体状态的夹件材料；
步骤S-2，把半导体芯片连结到导线架的芯片座；
步骤S-3，通过导电性粘合剂把夹件材料的主夹件与副夹件对准各领域地附接在上述连结的半导体芯片的上部；
步骤S-4，在附接了上述夹件材料的状态下进行注塑而形成封装主体；
步骤S-5，把上述封装主体的一侧和夹件材料一起切割地清除主夹件与副夹件的连接部分而予以个别化。
6.根据权利要求5所述的利用多个夹件结构的半导体封装的制造方法，其特征在于，在准备上述夹件材料的步骤S-1中，夹件材料在主夹件的一侧延伸出第一连接条而在副夹件的一侧延伸出第二连接条；
还包括连接上述第一连接条与第二连接条的第三连接条。
7.根据权利要求6所述的利用多个夹件结构的半导体封装的制造方法，其特征在于，
上述夹件材料为复数个并且以按照一定间距排列在边框内部的形态构成，上述夹件材料与边框通过第四连接条连接。
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