CN106158810B - 用于ic封装的具有偏转的连接杆的引线框架 - Google Patents
用于ic封装的具有偏转的连接杆的引线框架 Download PDFInfo
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- CN106158810B CN106158810B CN201510297163.5A CN201510297163A CN106158810B CN 106158810 B CN106158810 B CN 106158810B CN 201510297163 A CN201510297163 A CN 201510297163A CN 106158810 B CN106158810 B CN 106158810B
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- 238000000465 moulding Methods 0.000 claims abstract description 19
- 238000004806 packaging method and process Methods 0.000 claims abstract description 19
- 238000006073 displacement reaction Methods 0.000 claims abstract description 3
- 150000001875 compounds Chemical class 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 8
- 230000017525 heat dissipation Effects 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000012857 repacking Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
本发明涉及用于IC封装的具有偏转的连接杆的引线框架。一种封装集成电路(IC)器件,具有安装在IC管芯上的散热器,IC管芯自身安装在管芯焊垫上,使用具有连接杆的引线框架对该器件进行组装,连接杆在器件组装的封装阶段偏转,从而,当通过模制工具施加压力时,使得管芯焊垫、管芯和散热器相对于引线框架的支撑结构移动。该移动致使忽略封装期间散热器和管芯之间的相对位移,从而降低对管芯物理损坏的可能性。每个连接杆具有许多不同角度的区域,当向连接杆施加压力时,所述区域使连接杆偏转。
Description
背景技术
本发明涉及封装集成电路(IC)器件,以及更具体地,涉及使用引线框架组装的封装IC器件。
为了防止内部产生的热损坏封装IC器件内的IC管芯,所述器件可以包括安装在管芯之上的散热器,其中散热器的顶侧暴露于封装器件的外部表面。在器件组装过程的模制或封装阶段,模制工具向器件的子组件施加力以防止液体模制化合物在散热器的顶侧和模制工具的顶部模制槽的底表面之间渗出,从而导致模制化合物覆盖部分或者全部的散热器的顶侧,这会限制封装器件的散热能力。不幸地是,在封装阶段,由模制工具施加的压力会导致IC管芯的物理损坏(诸如断裂)。
附图说明
通过接下来的详细描述、所附权利要求和附图,本发明的实施例会变得完全的显而易见,附图中,相似的参考数字标识相似或者相同的元件。
图1A和图1B分别是根据本发明一个实施例的封装IC器件的俯视图和横截面侧视图。
图2A和图2B分别是用于组装图1A和图1B的封装IC器件的引线框架的俯视图和横截面侧视图。
图3A和图3B分别是图1A和图1B的IC管芯已经安装到管芯焊垫上并电连接到图2A和图2B的引线框架的引线结构之后的器件的子组件的俯视图和横截面侧视图。
图4是图1A和图1B的散热器已经安装到位于在组装图1A和图1B的封装IC器件的封装阶段使用的模制工具的顶部和底部模制槽之间的IC管芯上之后的图3A和图3B的子细件的横截面侧视图。
具体实施方式
在此公开了本发明详细的示例性实施例。然而,在此公开的具体结构和功能细节仅用于描述本发明示例实施例的目的。本发明可以体现为多种替代形式,并且不应该认为仅限于此处列出的实施例。此外,在此所使用的术语仅用于描述特定实施例的目的,以及不意在限制本发明的示例实施例。
如在此所使用的,单数形式“一个”和“该”也意在包括复数形式,除非上下文中明确相反地指示。还应明白的是,术语“包括”指明存在所陈述的特征、步骤或部件,但不排除存在或加入一个或多个其它特征、步骤或部件。还应注意,在一些可替代的实现方式中,所提到的功能/行为可以不按附图中所提到的顺序发生。例如,连续示出的两幅附图事实上可以基本上同时执行,或者有时可以以相反的顺序执行,视所涉及的功能/行为而定。
在一个实施例中,本发明是一种制造的物品,其包括用于封装器件的引线框架。引线框架包括管芯焊垫和多个连接杆(tie bar),该多个连接杆在其近端处连接到管芯焊垫,其中,在封装器件的组装期间,(i)连接杆的远端连接到引线框架支撑结构,以及(ii)连接杆偏转以使管芯焊垫相对于引线框架支撑结构移动。
在另一个实施例中,本发明提供一种用于组装封装器件的方法。将管芯安装到引线框架的管芯焊垫上,引线框架还包括多个连接杆,该多个连接杆在其近端连接到管芯焊垫,且在其远端连接到引线框架支撑结构。使用键合线将管芯引线键合到引线框架的导线。将散热器安装到管芯上以提供子组件。在子组件上执行封装阶段,其中,在封装阶段,连接杆偏转,并且管芯焊垫相对于引线框架支撑结构移动。
现在参考图1A和图1B,它们分别示出了根据本发明的一个实施例的封装IC器件100的俯视图和横截面侧视图(沿着图1A中的切割线AA)。封装IC器件100具有顶表面102,相对的底表面104,和外周表面106。具有顶表面112(可以利用特征114对其进行图形化)的散热器110安装在IC管芯120上,IC管芯120自身安装在管芯焊垫130上。器件100还具有在近端141处连接到管芯焊垫130的多个连接杆140。每个连接杆140具有近端141,近区143,中区145,远区147和远端149。(例如利用键合线)电连接到管芯120的有源表面上的键合焊垫(未示出)的多个外部引线150从封装体向外延伸并且允许管芯120连接到其它电子部件或电路。模制化合物160覆盖管芯120、管芯焊垫130、和键合线以及部分的散热器110、连接杆140和外部引线150。
优选利用特征114图形化散热器110的顶表面112,以增加顶表面112的整体有效表面积,从而增加散热器110的散热能力。优选地,散热器110的整个顶表面112在封装器件100的顶部外表面102处被暴露。还要注意到每个连接杆140的中区145在封装器件100的底部外表面104处被暴露,以及,每个连接杆140的远端149在封装器件100的外周表面106处被暴露。连接杆140的这些暴露部分145、149为封装器件100提供额外的散热路径。
如图1B所示,每个连接杆的近区143将近端141(在此处连接杆140连接到管芯焊垫130)连接到中区145,以及远区147将中区145连接到远端149。
如图1B所示,每个连接杆的近区143将近端141(在此处连接杆140连接到管芯焊垫130)连接到中区145,以及远区147将中区145连接到远端149。
图2A和图2B、图3A和图3B、图4示出细装图1A和图1B中的封装IC器件100的不同阶段。
图2A和2B分别是用于组装图1A和图1B的封装IC器件100的金属(例如铜)引线框架200的俯视图和横截面侧视图(沿图2A中的切割线AA)。引线框架200可以如现有技术中已知的那样分立形成或者形成为带状。引线框架200包括管芯焊垫130,4个连接杆140,和外部引线150,全部在图1A和图1B中示出。另外,引线框架200包括内部引线152和矩形坝型条(dambar)154,在器件组装期间,其将引线框架200的全部其它元件保持在一起。内部和外部引线152、150从坝型条270向内和向外突出。内部引线152利用键合线电连接到管芯120并且被模制化合物160覆盖,而外部引线150从模制化合物160向外突出。在细装过程中移除坝型条154,在这种情况下优选地通过冲压移除。
每个连接杆140的远端149将连接杆140连接到坝型条154。如图2B所示,(i)每个连接杆140的近区143以向下的角度从近端141延伸到中区145,(ii)中区145平行于由芯片焊垫130限定的平面,以及(iii)远区147以向上的角度从中区145延伸到远端149。由于这些不同区域的相对长度和角度,所以管芯焊垫130的标高低于坝型条154的标高。
图3A和图3B分别是IC管芯120已经(使用适当的粘合剂)安装并附接到管芯焊垫130并利用键合线380电连接到内部引线152之后的器件子组件300的俯视图和横截面侧视图(沿图3A的切割线AA)。图3A示出了键合线380,而在图3B中,为了简化略去了键合线380。注意,在组装过程的放置管芯和引线键合阶段,管芯焊垫130由组装阶段工具(未示出)从底部直接支撑。
图4是使用适当的粘合剂(诸如导热粘合剂)已经将散热器110安装到IC管芯120上之后的图3A和图3B中的子组件300的横截面侧视图。获得的子组件位于顶部模制槽410和底部模制槽420之间的模制工具中,从而可执行组装的封装阶段。提供状态间隙430以指示顶部和底部模制槽410和420被正确安装。如图4所示,顶部模制槽410的底部表面412与散热器110的顶部表面112相邻接。在封装阶段,液体模制化合物160(在图4中未示出)经由注入间隙(未示出)被注入由顶部和底部模制槽410和420形成的模具内。
为了防止模制化合物160覆盖散热器110的顶表面112,必须通过顶部和底部模制槽410和420对子组件施加足够的压力,以及正是该压力可能会导致IC管芯120的物理损坏。
然而,根据本发明,由于连接杆140的设计,连接杆140会偏转并且允许管芯焊垫130(与芯片120和散热器110一起)响应于通过顶部和底部模制槽410和420施加的压力关于引线框架坝型条154移动(图4的视图中垂直向下)。由于管芯焊垫130能够垂直移动,因此当在封装阶段,当模制工具施加压力时,可以忽略散热器110和管芯120之间的相对位移。
在封装阶段,连接杆140的中区145被直接支撑在底部模制槽420的顶表面422上,而底部模制槽420并不直接支撑管芯焊垫130,从而使管芯焊垫130响应于所施加的压力关于连接杆的中区145垂直移动。在理想的引线框架设计中,连接杆140的近区143会充分偏转以防止所施加的压力损坏IC管芯120,但还足够坚硬(stiff)以确保模制化合物160不会渗到散热器110的顶表面112上。在液体模制化合物160注入模具之后,例如通过加热来固化以封装子组件。
本领域技术人员应该明白,通常使用图2A和图2B的带状引线框架200将图1A和图1B的封装IC器件100与器件100的多个其它实例并行组装,其中,引线框架坝型条154作为带中相邻的引线框架200的支撑结构。在此种情况下,在图4的封装阶段之后,通过冲压掉坝型条的方式分离获得的封装子组件,从而电隔离封装IC器件100的外部引线150和管芯焊垫130。随后,可以修整并形成外部引线150,从而完成图1A和图1B的封装IC器件100的每个实例的组装。
注意,散热器110的暴露顶部宽于与管芯120相匹配的底部。这能够实现更强的散热,同时仍为键合线380提供至芯片120的顶表面的入口。
尽管已经在图2A和图2B的引线框架200的上下文中描述了本发明,该引线框架200具有4个彼此平行的连接杆140,但是本发明的其它实施例可以具有其它数量的连接杆和/或不完全彼此产行的连接杆。例如,连接杆可以是将矩形管芯焊垫的4个拐角连接到矩形支撑结构的4个拐角的4个呈对角分布的连接杆。
尽管已经在图2A和图2B的引线框架200的上下文中描述了本发明,其中,管芯焊垫130的标高低于坝型条154的标高,但是在本发明的其它实施例中,管芯焊垫的标高与支撑结构的标高相同,或者高于支撑结构的标高。
尽管已经在图2A和图2B的引线框架200的上下文中描述了本发明,其中,每个连接杆140具有近、中和远区143、145和147,然而,本领域技术人员应该认识到,存在连接杆在器件组装的封装阶段将产生足够偏转的其它的几何图形设计,从而防止或者至少抑制对IC管芯的物理损坏。
尽管已经在图2A和图2B的引线框架200的上下文中描述了本发明,其具有行为像弹簧的弹性连接杆140,但是通常,对于本发明的连接杆,在封装阶段在一个方向上偏转足矣。在去除封装阶段的压力之后,连接杆没有必要能够恢复到它们的原始形状。
尽管已经在具有单个IC管芯120的图1A和图1B的封装IC器件100的上下文中描述了本发明,但是本发明的其它实施例可以具有多个IC管芯,这些IC管芯被安装成一个挨着一个和/或一个在另一个和/或附加元件(诸如附加散热器和/或插入件,没有限制)之上。
引线框架是金属引线和可能的其它元件(例如,电力条、管芯焊垫,又称为管芯座(paddle)和管芯衬板(flag))的集合,用于半导体封装以将一个或者多个集成电路(IC)管芯组装为单个封装IC器件。在组装成封装器件之前,引线框架可以具有支撑结构(例如,坝型条和连接杆),以保持那些元器件在正确的位置。在组装过程中,可以移除支撑结构。如这里所使用的,术语“引线框架”可以用于指组装之前或者组装之后的元件的集合,而不管存在或者不存在那些支撑结构。
还需进一步理解的是,本领域技术人员在不脱离由下面的权利要求所涵盖的本发明的实施例的情况下,可以对已经描述和示出的、目的在于解释本发明的实施例的部件的细节、材料和配置方面进行不同变化。
在包括任何权利要求的说明书中,术语“每个”可以用于指多个之前所列举的元件或步骤中的一个或多个具体特征。当与开放式术语“包括”一起使用时,术语“每个”的陈述内容不排除附加的、未陈述的元件或者步骤。因此,应理解的是,制造的物品可以具有额外的、未陈述的元件,以及方法可以具有额外的、未陈述的步骤,其中,额外的、未陈述的元件或者步骤不具有一个或者多个已具体说明的特征。
在此提及“一个实施例”或者“实施例”意思是与实施例相联系的所描述的具体特征、结构或者特点可以被包括在本发明的至少一个实施例中。在说明书不同位置出现的短语“在一个实施例中”并非必然地完全指相同的实施例,也不是与其它实施例必然互斥的单独的或者替代的实施例。相同规则适用于术语“实现方式”。
本申请中权利更求所覆盖的实施例被限制于(1)由本说明书能实现的实施例,以及(2)对应于法定可授权主题的实施例。不能实现的实施例以及对应于非法定可授权主题的实施例即使它们落入权利要求的范围内,也明确放弃要求保护。
Claims (8)
1.一种封装器件,包括用于封装器件的引线框架,所述引线框架包括:
管芯焊垫;和
多个连接杆,在所述连接杆的近端处连接到所述管芯焊垫,其中,在所述封装器件的组装阶段,(i)所述连接杆的远端连接到所述引线框架的坝型条,和(ii)所述连接杆以偏转的方式配置,以使得所述管芯焊垫相对于所述坝型条移动;其中:
所述管芯焊垫限定管芯焊垫平面;和
每个连接杆具有一个或多个区域,所述一个或多个区域不与所述管芯焊垫平面平行,并且当在组装期间所述管芯焊垫相对于引线框架支撑结构移动时,使得所述连接杆偏转。
2.根据权利要求1所述的封装器件,其中,每个连接杆包括:
近区,以向下的角度从所述连接杆的近端延伸;
中区,连接到所述近区,其中,所述中区平行于并低于所述管芯焊垫平面;和
远区,以向上的角度从所述中区向所述连接杆的远端延伸。
3.根据权利要求2所述的封装器件,其中,每个连接杆的远端高于所述管芯焊垫平面,从而,在组装期间,所述管芯焊垫低于所述坝型条。
4.根据权利要求1所述的封装器件,其中,所述引线框架包括从所述管芯焊垫的4个拐角延伸的4个连接杆,并且每个连接杆从所述管芯焊垫的端部向所述坝型条呈直角。
5.根据权利要求4所述的封装器件,还包括:
管芯,安装于所述管芯焊垫上;
键合线,将所述管芯电连接至所述引线框架的引线;
散热器,安装于所述管芯上;和
模制化合物,用于封装所述管芯、所述键合线和所述管芯焊垫,
其中,所述散热器暴露在所述模制化合物的外表面。
6.根据权利要求5所述的封装器件,其中,在组装过程的封装阶段,所述连接杆偏转,以及所述管芯焊垫、所述管芯、和所述散热器相对于所述坝型条移动,从而,在封装阶段,所述散热器和管芯之间的相对位移可忽略不计。
7.一种用于组装封装器件的方法,所述方法包括:
经由管芯的底表面将管芯安装在引线框架的管芯焊垫上,其中,所述引线框架具有多个连接杆,在所述连接杆的近端处连接到所述管芯焊垫和在所述连接杆的远端处连接到坝型条;
使用键合线将所述管芯电连接到所述引线框架的引线;
将散热器安装在所述管芯的顶表面上以提供子组件;和
使用模制化合物封装所述子组件,其中,在封装步骤中,所述连接杆偏转,以及所述管芯焊垫相对于所述坝型条移动;其中:
所述管芯焊垫限定管芯焊垫平面;和
每个连接杆具有一个或多个区域,所述一个或多个区域不与所述管芯焊垫平面平行,并且在组装期间,当所述管芯焊垫相对于所述坝型条移动时,能够使所述连接杆偏转。
8.根据权利要求7所述的方法,其中,每个连接杆包括:
近区,以向下的角度从所述连接杆的近端延伸;
中区,连接到所述近区,其中,所述中区平行于并且低于所述管芯焊垫平面;和
远区,以向上的角度从所述中区延伸到所述连接杆的远端。
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US5889318A (en) * | 1997-08-12 | 1999-03-30 | Micron Technology, Inc. | Lead frame including angle iron tie bar and method of making the same |
US6246110B1 (en) * | 1998-07-06 | 2001-06-12 | Micron Technology, Inc. | Downset lead frame for semiconductor packages |
CN104134646A (zh) * | 2013-05-03 | 2014-11-05 | 英飞凌科技股份有限公司 | 具有支撑构件的引线框架条 |
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US9449901B1 (en) | 2016-09-20 |
US20160293526A1 (en) | 2016-10-06 |
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