CN104134646A - 具有支撑构件的引线框架条 - Google Patents

具有支撑构件的引线框架条 Download PDF

Info

Publication number
CN104134646A
CN104134646A CN201410180437.8A CN201410180437A CN104134646A CN 104134646 A CN104134646 A CN 104134646A CN 201410180437 A CN201410180437 A CN 201410180437A CN 104134646 A CN104134646 A CN 104134646A
Authority
CN
China
Prior art keywords
supporting member
lead frame
pipe core
welding disc
core welding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410180437.8A
Other languages
English (en)
Other versions
CN104134646B (zh
Inventor
C.马尔贝拉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN104134646A publication Critical patent/CN104134646A/zh
Application granted granted Critical
Publication of CN104134646B publication Critical patent/CN104134646B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • H01L23/49555Cross section geometry characterised by bent parts the bent parts being the outer leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73263Layer and strap connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92246Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

一种具有支撑构件的引线框架条。引线框架条包括多个连接的单元引线框架。每个单元引线框架具有用于附着于半导体管芯的管芯焊盘、将管芯焊盘连接到单元引线框架的外围的系杆以及从该外围朝着管芯焊盘突出的多个引线。引线框架条还包括支撑构件,其在近端处被图案化到每个单元引线框架的外围中或被连接到该外围,并弯曲到与引线不同的平面中,使得每个支撑构件的远端被设置在引线上面或下面并朝着管芯焊盘突出。能够将支撑构件的远端锚定在密封被附着于管芯焊盘的电子部件的模塑料中,以在单元引线框架分离之前的引线框架条测试期间维持结构完整性。

Description

具有支撑构件的引线框架条
技术领域
本申请涉及引线框架条,并且更具体地用于在引线框架条测试期间维持结构完整性的支撑构件。
背景技术
引线框架形成IC封装的底座或骨架,在到完成的封装的组装期间向半导体管芯提供机械支撑。引线框架通常包括用于附着半导体管芯的管芯焊盘(die paddle)和提供用于到管芯的外部电连接的装置的引线。能够由导线、例如通过导线结合或胶带自动接合来将管芯连接到引线。引线框架通常由扁平金属片构造而成,例如通过冲压或蚀刻。金属片通常被暴露于去除未被光致抗蚀剂覆盖的区域的化学蚀刻剂。在蚀刻过程之后,将被蚀刻框架单体化(分离)成引线框架条。每个引线框架条包括多个单元引线框架,每个具有上面描述的管芯焊盘和引线构造。
通常在单元引线框架从引线框架条的分离(例如通过打孔(punch))之后测试在引线框架条的组装过程完成之后附着于芯片焊盘的半导体管芯。替换地,单元引线框架在管芯测试期间通过系杆而保持机械连接到引线框架。这一般地称为引线框架条测试。单元引线框架与引线框架条的分离在电测试之后发生。管芯焊盘在测试期间通过系杆保持电连接到引线框架条。这对于其中管芯焊盘服务于电连接功能的应用而言是有问题的,例如在DSO(双重小轮廓)封装中,其中暴露的管芯焊盘提供到被附着于管芯焊盘的半导体管芯的背面的电连接。
在这种情况下,系杆将管芯焊盘电短路至引线框架条和被附着于相同的引线框架条的其它管芯焊盘,使电测试过程复杂化。
发明内容
根据本文所描述的实施例,提供了包括多个连接的单元引线框架的引线框架条。每个单元引线框架具有用于附着于半导体管芯的管芯焊盘、将管芯焊盘连接到单元引线框架的外围的系杆、以及从该外围朝着管芯焊盘突出的多个引线。引线框架条还包括在近端处被图案化到每个单元引线框架的外围中或被连接到该外围的支撑构件。支撑构件弯曲到与引线不同的平面中,使得每个支撑构件的远端被设置在引线上面或下面并朝着管芯焊盘突出。能够将支撑构件的远端锚定在密封被附着于管芯焊盘的电子部件的模塑料(mold compound)中。支撑构件在系杆被从管芯焊盘拆卸之后维持引线框架条的结构完整性,以使得能够在单元引线框架从引线框架条的分离之前发生可靠引线框架条测试。
根据测试被附着于引线框架条的电子部件的方法的实施例,该方法包括:
将半导体管芯附着于管芯焊盘中的每个;
使支撑构件弯曲到与引线不同的平面中,使得每个支撑构件的远端被设置在引线上面或下面并朝着管芯焊盘突出;
用模塑料来密封单元引线框架,使得每个支撑构件的远端被锚定在模塑料中,并且系杆的一部分保持不被模塑料覆盖;
在模塑料外面将系杆从管芯焊盘拆卸,使得支撑构件将单元引线框架固定就位,并且半导体管芯与引线框架条电隔离;
在将系杆从管芯焊盘拆卸之后测试半导体管芯;以及
在测试半导体管芯之后将单元引线框架分离。
根据包括引线框架条和支撑构件的半导体条组件的实施例,该组件还包括被附着于管芯焊盘中的每个的半导体管芯以及模塑料,其至少部分地密封单元引线框架,使得每个支撑构件的远端被锚定在模塑料中,并且系杆的一部分保持不被模塑料覆盖。在模塑料外面将系杆从单元引线框架的外围拆卸,使得支撑构件将单元引线框架固定就位,并且半导体管芯例如在条测试期间与引线框架条电隔离。
本领域的技术人员在阅读以下详细描述时并在浏览附图时将认识到附加特征和优点。
附图说明
图中的部件不一定按比例,而是将重点放在说明本发明的原理上。此外,在图中,相似的参考数字指示对应的部分。在所述附图中:
图1图示出根据实施例的具有支撑构件的引线框架条的自上而下的平面图;
图2图示出根据另一实施例的具有支撑构件的引线框架条的自上而下的平面图;
图3图示出在支撑构件的弯曲期间的具有支撑构件的引线框架条的透视截面图;
图4图示出根据实施例的包括具有多个单元引线框架和支撑构件的引线框架条以及被附着于单元引线框架的管芯焊盘的密封半导体管芯的半导体条组件的透视截面图;
图5图示出将系杆从管芯焊盘拆卸之后的图4的半导体条组件的透视截面图;
图6图示出根据另一实施例的包括具有多个单元引线框架和支撑构件的引线框架条以及被附着于单元引线框架的管芯焊盘的密封半导体管芯的半导体条组件的透视截面图;
图7图示出将系杆从管芯焊盘拆卸之后的图6的半导体条组件的透视截面图;以及
图8图示出测试被附着于具有支撑构件的引线框架条的单元引线框架的电子部件的方法的实施例的流程图。
具体实施方式
本文所描述的实施例提供了包括多个连接的单元引线框架的引线框架条。每个单元引线框架被设计成容纳半导体管芯。稍后在管芯附着之后将单元引线框架从引线框架条分离成单独的单元,并且稍后进行引线框架条测试。引线框架条还包括在近端处被图案化到每个单元引线框架的外围中或被连接到该外围的支撑构件。支撑构件弯曲到与引线不同的平面中,使得每个支撑构件的远端被设置在引线上面或下面并朝着管芯焊盘突出。能够将支撑构件的远端锚定在密封被附着于单元引线框架的管芯焊盘的电子部件的模塑料中,使得在引线框架条测试期间(在单元引线框架的分离之前)维持引线框架条的结构完整性。
图1图示出根据实施例的引线框架条100的一部分的自上而下的平面图。引线框架条100包括多个连接的单元引线框架102,在图1中示出了其中的两个。每个单元引线框架102具有用于附着于半导体管芯的管芯焊盘104、将管芯焊盘104连接到单元引线框架102的外围108的系杆106以及从该外围108朝着管芯焊盘104突出的多个引线110。
引线框架条100还包括在近端111处被图案化到每个单元引线框架102的外围108中或被连接到该外围的支撑构件112。支撑构件112可以包括与引线框架条100相同或不同的材料。例如,支撑构件112可以具有与系杆106、管芯焊盘104、以及引线110相同的CTE(热膨胀系数)和材料饰面(material finish),由于材料同性而提供类似的热循环应力特性和/或界面和粘附特性。
支撑构件112还可以与管芯焊盘104和引线110间隔开。例如,能够将支撑构件112空间地设置在与系杆108、引线110和/或管芯焊盘104不同的平面上。用此类配置,支撑构件112并不争夺与系杆106、引线110和管芯焊盘104相同的平面空间,允许管芯焊盘104和引线110的尺寸最大化。并且,用此类配置,支撑构件112并不争夺围绕管芯焊盘104的外围的邻近的引线框架金属。支撑构件112能够位于更远离管芯焊盘104,在那里存在更多可用金属,使得更宽支撑构件112的设计能够为引线框架条100提供更强机械支撑并避免对围绕管芯焊盘外围的引线框架材料的争夺。支撑构件112能够被涂敷电绝缘体或者保持不被涂敷。
在一个实施例中,引线框架条100例如通过冲压或蚀刻由扁平金属片构造。例如,能够使金属片暴露于去除未被光致抗蚀剂覆盖的区域的化学蚀刻剂。能够执行其它处理,例如诸如激光蚀刻以使金属片图案化。在图案化过程之后,将图案化框架单体化(分离)成引线框架条100。在图1中示出了一个此类引线框架条100。能够将支撑构件112图案化到金属片中作为图案化过程的一部分,并且因此将支撑构件112形成为引线框架条100的单一连续部分。替换地,能够在图案化过程之后例如通过胶合、焊接等将支撑构件112连接到每个单元引线框架102的外围。在每种情况下,根据图1中所示的实施例,单元引线框架102每个具有在外围108的相对侧被图案化到单元引线框架102的外围108中或连接到该外围108的一对支撑构件112。此外,根据图1中所示的实施例,被图案化到每个单元引线框架102的外围108中或被连接到该外围108的该对支撑构件112参考在图1中标记为‘CL’的中心线相互偏移。替换地,被图案化到每个单元引线框架102的外围108中或被连接到该外围108的该对支撑构件112能够对于每个单元引线框架102而被相互对准,或者能够为引线框架条100提供对准和未对准支撑构件配置的某个组合。
图2图示出根据另一实施例的引线框架条200的一部分的自上而下的平面图。图2中所示的引线框架条200类似于图1中所示的那个。然而,被图案化到每个单元引线框架102的外围108中或被连接到该外围108的该对支撑构件112在与对应管芯焊盘104平行的第一方向上弯曲,并且然后在垂直于第一方向且朝向对应管芯焊盘104的第二方向上弯曲。
图3图示出使支撑构件112弯曲到与引线110和系杆106不同的平面中之后的引线框架条100/200的截面图。引线110在图3中的视图之外。由图3中所示的曲线箭头来指示支撑构件的弯曲过程。能够使支撑构件112从单元引线框架外围108向上并朝着管芯焊盘104弯曲,如图3中所示。替换地,能够使支撑构件112从单元引线框架外围108向下并朝着管芯焊盘104弯曲。一般地,每个支撑构件112的远端113被设置在引线110和系杆106上面或下面并朝着管芯焊盘104突出。支撑构件112的近端111保持连接到对应的单元引线框架102的外围108。能够在半导体管芯到管芯焊盘104的附着之前或之后使支撑构件112弯曲到与引线110不同的平面中并朝向管芯焊盘104。在图1和2中,由参考数字112'来指示支撑构件的弯曲前位置,并且由参考数字112来指示弯曲后位置。
图4图示出将半导体管芯302附着于引线框架条100/200的管芯焊盘104且单元引线框架102至少部分地被诸如环氧树脂之类的模塑料304密封之后的半导体条组件300的截面图。根据本实施例,引线框架条100/200具有到管芯焊盘104的向下的延伸306,使得管芯焊盘104被定位在引线110下面。根据本实施例,支撑构件112在密封之前从引线框架条100/200向上且朝着管芯焊盘104弯曲,使得每个支撑构件112的远端113被锚定在管芯焊盘104上面的模塑料304中。能够如图4中所示使支撑构件112的远端113向下朝着管芯焊盘104弯曲,以更好地将支撑构件112的远端113锚定在模塑料304中。
面对管芯焊盘104的半导体管芯302的底侧在由模塑料304进行的密封之前被附着于管芯焊盘104。在垂直电流器件的情况下,管芯302的底侧具有端子或焊盘,并且电流在顶侧与底侧之间的器件中垂直地流动。根据本实施例,管芯302的底侧被诸如焊料之类的导电材料308附着于对应的管芯焊盘104。管芯焊盘104的底侧能够保持暴露以形成用于对应半导体管芯302的测试和正常操作的接触焊盘,即在管芯302的底侧提供到端子的外部电连接。在其中在管芯302的顶侧进行所有电器件连接的横向电流器件的情况下,能够使用诸如胶或环氧树脂之类的电绝缘材料308将管芯302的底侧胶合或别的方式附着到管芯焊盘104。能够由导线310、例如通过导线结合或胶带自动结合来将半导体管芯302的顶侧的端子或焊盘连接到对应的引线110。
在密封过程之后,将每个支撑构件112的远端113锚定在密封对应半导体管芯302的模塑料304中。此类配置在后续引线框架条测试期间(在单元引线框架102的分离之前)维持引线框架条100/200的结构完整性,如接下来参考图5所描述的。
图5示出了在模塑料304外面切断或切割将管芯焊盘104固定到单元引线框架102的外围108的系杆106之后的图4的半导体条组件300的截面图。在图5中由有角度的短划线来表示系杆切断/切割过程。在将系杆106从单元引线框架102的外围108拆卸之后,半导体管芯302与引线框架条100/200电隔离。支撑构件112在管芯302的后续测试期间(在单元引线框架102的分离之前)将单元引线框架102固定就位。
图6图示出将半导体管芯302附着于引线框架条100/200的管芯焊盘104且单元引线框架102至少部分地被诸如环氧树脂之类的模塑料304密封之后的半导体条组件400的另一实施例的截面图。图6中所示的半导体条组件400类似于图4中所示的那个,然而,支撑构件112在密封之前从引线框架条100/200向下而不是向上弯曲且朝向管芯焊盘104。根据本实施例,每个支撑构件112的远端113在密封过程之后被锚定于在管芯焊盘104下面的模塑料304中。能够如图6中所示地使支撑构件112的远端113朝着管芯焊盘104向上弯曲以更好地将支撑构件112的远端104锚定在模塑料304中。类似于图4中所示的那个,图6中所示的配置在后续引线框架条测试期间(在单元引线框架102的分离之前)维持引线框架条100/200的结构完整性,如接下来参考图7所描述的。
图7示出了在模塑料304外面切断或切割将管芯焊盘104固定到单元引线框架102的外围108的系杆106之后的图6的半导体条组件的截面图。在图7中由有角度的短划线来表示系杆切断/切割过程。根据本实施例,在支撑构件112上面切断/切割系杆106。半导体管芯302在将系杆106从单元引线框架102的外围108拆卸之后与引线框架条100/200电隔离,并且支撑构件112在管芯302的后续测试期间(在单元引线框架102的分离之前)将单元引线框架102固定就位,如本文中先前所描述的。
图8图示出如本文中先前所描述的测试被附着于包括多个连接的单元引线框架和支撑构件的引线框架条的电子部件的方法的实施例。该方法包括将半导体管芯附着于单元引线框架的管芯焊盘(方框500)和将管芯的顶侧与单元引线框架的对应引线之间的电连接导线结合(方框510)。在管芯附着和/或结合过程之前或之后使支撑构件弯曲到与引线不同的平面中,使得每个支撑构件的远端被设置在引线的上面或下面并朝着管芯焊盘突出(方框520)。可选地,能够在引线框架供应商处执行引线框架支撑构件弯曲或制造/准备,接下来是管芯组装过程(步骤500和510)。在每种情况下,用模塑料将单元引线框架密封,使得每个支撑构件的远端被锚定在模塑料中,并且系杆的一部分保持不被模塑料覆盖(方框530)。在模塑料外面将系杆从管芯焊盘拆卸,使得支撑构件将单元引线框架固定就位,并使半导体管芯与引线框架条电隔离(方框540)。在将系杆从管芯焊盘拆卸之后测试半导体管芯(方框550)。在测试半导体管芯之后将单元引线框架从引线框架条分离(方框560)。该方法能够可选地包括在用模塑料来密封单元引线框架之前用电绝缘体涂敷支撑构件。能够通过对引线框架条进行冲压或蚀刻或者通过将支撑构件附着于引线框架条(例如通过如本文中先前所描述的焊接或胶合)来形成支撑构件。
诸如“下”、“下面”、“较低”、“之上”、“上”等空间相对术语被用于容易描述以解释一个元件相对于第二元件的定位。除与图中所描绘的那些不同的取向之外,这些术语意图涵盖器件的不同取向。此外,还使用诸如“第一”、“第二”等的术语来描述各种元件、区域、部分等,并且也不意图是限制性的。遍及描述,相似的术语指的是相似的元件。
如本文所使用的,术语“具有”、“包含”、“包括”、“含有”等是开放性术语,其指示声称的元件或特征的存在,但是不排除附加元件或特征。冠词“一”、“一个”和“该”意图包括复数以及单数,除非上下文另外明确地指出。
鉴于以上变化和应用的范围,应理解的是本发明不受前述描述的限制,也不受附图的限制。事实上,本发明仅仅由以下权利要求及其法律等价物来限制。

Claims (20)

1.一种测试被附着于引线框架条的电子部件的方法,该引线框架条包括多个连接的单元引线框架,每个单元引线框架具有管芯焊盘、将管芯焊盘连接到单元引线框架的外围的系杆、从外围朝着管芯焊盘突出的多个引线、以及在近端处被图案化到外围中或连接到外围的支撑构件,该方法包括:
将半导体管芯附着于管芯焊盘中的每个;
使支撑构件弯曲到与引线不同的平面中,使得每个支撑构件的远端被设置在引线上面或下面并朝着管芯焊盘突出;
用模塑料来密封单元引线框架,使得每个支撑构件的远端被锚定在模塑料中,并且系杆的一部分保持不被模塑料覆盖;
在模塑料外面将系杆从管芯焊盘拆卸,使得支撑构件将单元引线框架固定就位,并且半导体管芯与引线框架条电隔离;
在将系杆从管芯焊盘拆卸之后测试半导体管芯;以及
在测试半导体管芯之后将单元引线框架分离。
2.权利要求1的方法,包括使在引线上面的支撑构件和支撑构件的远端朝着管芯焊盘向下弯曲。
3.权利要求1的方法,包括使在引线下面的支撑构件和支撑构件的远端朝着管芯焊盘向上弯曲。
4.权利要求1的方法,其中,所述支撑构件包括与引线框架条相同的材料。
5.权利要求1的方法,其中,所述支撑构件被形成为引线框架条的单一连续部分。
6.权利要求1的方法,还包括在用模塑料来密封单元引线框架之前用电绝缘体涂敷支撑构件。
7.权利要求1的方法,其中,所述支撑构件在被弯曲到与引线不同的平面中之后与管芯焊盘和引线间隔开。
8.权利要求1的方法,还包括通过对引线框架条进行冲压或蚀刻来形成支撑构件。
9.一种半导体条组件,包括:
包括多个连接的单元引线框架的引线框架条,每个单元引线框架具有管芯焊盘、用于将管芯焊盘连接到单元引线框架的外围的系杆、和从外围朝着管芯焊盘突出的多个引线;
支撑构件,其在近端处被图案化到每个单元引线框架的外围中或被连接到该外围,并被弯曲到与引线不同的平面中,使得每个支撑构件的远端被设置在引线上面或下面并朝着管芯焊盘突出;
半导体管芯,其被附着于管芯焊盘中的每个;
至少部分地密封单元引线框架的模塑料,使得每个支撑构件的远端被锚定在模塑料中,并且系杆的一部分保持不被模塑料覆盖,以及
其中,在模塑料外面将系杆从单元引线框架的外围拆卸,使得支撑构件将单元引线框架固定就位,并且半导体管芯与引线框架条电隔离。
10.权利要求9的半导体条组件,其中,所述支撑构件在引线上面弯曲,并且支撑构件的远端朝着管芯焊盘向下弯曲。
11.权利要求9的半导体条组件,其中,所述支撑构件在引线下面弯曲,并且支撑构件的远端朝着管芯焊盘向上弯曲。
12.权利要求9的半导体条组件,其中,所述支撑构件包括与引线框架条相同的材料。
13.权利要求9的半导体条组件,其中,所述支撑构件被形成为引线框架条的单一连续部分。
14.权利要求9的半导体条组件,其中,所述支撑构件被涂敷电绝缘体。
15.权利要求9的半导体条组件,其中,所述支撑构件与管芯焊盘和引线间隔开。
16.权利要求9的半导体条组件,其中,每个单元引线框架包括在单元引线框架的外围的相对侧被图案化到该外围中或被连接到该外围的一对支撑构件。
17.权利要求16的半导体条组件,其中,被图案化到每个单元引线框架的外围中或被连接到该外围的该对支撑构件相互偏移。
18.一种引线框架条,包括:
多个连接的单元引线框架,每个单元引线框架具有用于附着到半导体管芯的管芯焊盘、将管芯焊盘连接到单元引线框架的外围的系杆、以及从外围朝着管芯焊盘突出的多个引线;以及
支撑构件,其在近端处被图案化到每个单元引线框架的外围中或被连接到该外围,并弯曲到与引线不同的平面中,使得每个支撑构件的远端被设置在引线上面或下面并朝着管芯焊盘突出。
19.权利要求18的引线框架条,其中,每个单元引线框架包括在单元引线框架的外围的相对侧被图案化到该外围中或被连接到该外围的一对支撑构件。
20.权利要求19的引线框架条,其中,被图案化到每个单元引线框架的外围中或被连接到该外围的该对支撑构件相互偏移。
CN201410180437.8A 2013-05-03 2014-04-30 具有支撑构件的引线框架条 Expired - Fee Related CN104134646B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/886,407 US9171766B2 (en) 2013-05-03 2013-05-03 Lead frame strips with support members
US13/886407 2013-05-03

Publications (2)

Publication Number Publication Date
CN104134646A true CN104134646A (zh) 2014-11-05
CN104134646B CN104134646B (zh) 2017-10-24

Family

ID=51727587

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410180437.8A Expired - Fee Related CN104134646B (zh) 2013-05-03 2014-04-30 具有支撑构件的引线框架条

Country Status (3)

Country Link
US (1) US9171766B2 (zh)
CN (1) CN104134646B (zh)
DE (1) DE102014106158B4 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158810A (zh) * 2015-04-03 2016-11-23 飞思卡尔半导体公司 用于ic封装的具有偏转的连接杆的引线框架
CN107919339A (zh) * 2016-10-11 2018-04-17 恩智浦美国有限公司 具有高密度引线阵列的半导体装置及引线框架
CN108886033A (zh) * 2016-01-22 2018-11-23 德克萨斯仪器股份有限公司 引线框条带
CN114597189A (zh) * 2022-03-04 2022-06-07 泰兴市永志电子器件有限公司 一种集成电路用引线框架结构

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9263419B2 (en) * 2013-08-30 2016-02-16 Infineon Technologies Ag Lead frame strips with electrical isolation of die paddles
US9659843B2 (en) 2014-11-05 2017-05-23 Infineon Technologies Ag Lead frame strip with molding compound channels
JP1537979S (zh) * 2015-04-20 2015-11-16
JP1537980S (zh) * 2015-04-20 2015-11-16
JP1537981S (zh) * 2015-04-20 2015-11-16

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG102591A1 (en) * 2000-09-01 2004-03-26 Micron Technology Inc Dual loc semiconductor assembly employing floating lead finger structure
US20080265923A1 (en) * 2007-04-27 2008-10-30 Microchip Technology Incorporated Leadframe Configuration to Enable Strip Testing of SOT-23 Packages and the Like
JP2009141080A (ja) 2007-12-05 2009-06-25 Toshiba Corp リードフレームおよび半導体装置

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158810A (zh) * 2015-04-03 2016-11-23 飞思卡尔半导体公司 用于ic封装的具有偏转的连接杆的引线框架
CN106158810B (zh) * 2015-04-03 2020-04-10 恩智浦美国有限公司 用于ic封装的具有偏转的连接杆的引线框架
CN108886033A (zh) * 2016-01-22 2018-11-23 德克萨斯仪器股份有限公司 引线框条带
CN108886033B (zh) * 2016-01-22 2022-05-31 德克萨斯仪器股份有限公司 引线框条带
CN107919339A (zh) * 2016-10-11 2018-04-17 恩智浦美国有限公司 具有高密度引线阵列的半导体装置及引线框架
CN107919339B (zh) * 2016-10-11 2022-08-09 恩智浦美国有限公司 具有高密度引线阵列的半导体装置及引线框架
CN114597189A (zh) * 2022-03-04 2022-06-07 泰兴市永志电子器件有限公司 一种集成电路用引线框架结构
CN114597189B (zh) * 2022-03-04 2022-12-30 泰兴市永志电子器件有限公司 一种集成电路用引线框架结构

Also Published As

Publication number Publication date
CN104134646B (zh) 2017-10-24
DE102014106158B4 (de) 2018-10-11
DE102014106158A1 (de) 2014-11-06
US9171766B2 (en) 2015-10-27
US20140327004A1 (en) 2014-11-06

Similar Documents

Publication Publication Date Title
CN104134646A (zh) 具有支撑构件的引线框架条
CN102272922B (zh) 具有夹互连的半导体管芯封装
JP2786862B2 (ja) 接続要素
TW538661B (en) Method for making a hybrid integated circuit device
US9013013B1 (en) Pressure sensor package having a stacked die arrangement
JPH06216266A (ja) 電子装置パッケージ・アセンブリー
JP6251715B2 (ja) 基板アダプタを製造する方法、基板アダプタ、および半導体素子を接触させるための方法
CN105518851A (zh) 半导体装置及其制造方法
US9263419B2 (en) Lead frame strips with electrical isolation of die paddles
US8697496B1 (en) Method of manufacture integrated circuit package
CN104422558A (zh) 压力传感器封装的管芯边缘保护
US20190229044A1 (en) Lead frame with plated lead tips
CN112185923A (zh) 半导体装置的引线框架组件
JP2009164240A (ja) 半導体装置
CN108074901B (zh) 具有可湿拐角引线的半导体器件及半导体器件组装方法
CN103430305B (zh) 树脂封装
TW201923994A (zh) 附接在一偏移導線架晶粒附接墊及一分離晶粒附接墊之間之積體電路晶粒
JP4948436B2 (ja) レーザ素子用フレームパッケージおよびその製造方法
CN101399243B (zh) 半导体封装及半导体封装的制造方法
JP2007150044A (ja) 半導体装置
US10847449B2 (en) Lead frame with selective patterned plating
CN104979322A (zh) 半导体管芯封装及其组装方法
JP5857883B2 (ja) モールドパッケージの製造方法
JP2003234382A (ja) 半導体装置
JP4291788B2 (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20171024