CN103035631B - 联合封装高端和低端芯片的半导体器件及其制造方法 - Google Patents

联合封装高端和低端芯片的半导体器件及其制造方法 Download PDF

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CN103035631B
CN103035631B CN201110310147.7A CN201110310147A CN103035631B CN 103035631 B CN103035631 B CN 103035631B CN 201110310147 A CN201110310147 A CN 201110310147A CN 103035631 B CN103035631 B CN 103035631B
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chip
low side
source electrode
semiconductor device
lead frame
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CN103035631A (zh
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龚玉平
薛彦迅
赵良
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Chongqing Wanguo Semiconductor Technology Co ltd
Alpha and Omega Semiconductor Ltd
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NATIONS SEMICONDUCTOR (CAYMAN) Ltd
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Abstract

一种联合封装高端和低端芯片的半导体器件及其制造方法，该器件中低端和高端芯片分别粘贴在导电的引线框架的两边，使低端芯片的底部漏极电性连接载片基座的顶面，高端芯片的顶部源极通过对应的焊球，电性连接在载片基座的底面。本发明中由于低端芯片、引线框架的载片基座、高端芯片是立体布置的，能够减小整个器件的尺寸；将三者塑封之后，所述高端芯片背面覆盖的金属层或导电金属贴片，暴露设置在该半导体器件背面的封装体以外，有效改善器件的散热性能。

Description

联合封装高端和低端芯片的半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件的封装结构及制造方法，特别涉及一种联合封装高端和低端芯片的半导体器件及其制造方法。
背景技术
在功率晶体管的应用中，器件的尺寸及散热是两个重要的参数。通常通过暴露晶体管的栅极和漏极来改善器件的散热性能，但是实现过程往往比较复杂。
在一些开关电路，例如同步降压变流器、半桥式变流器和逆变器中，需要两个功率MOSFET以互补方式切换。如图1所示的开关电路中，包含连接在电压源3上的两个串联的MOSFET，通常分别称这两个MOSFET为高端和低端的MOSFET芯片(简称为高端芯片1和低端芯片2)。其中，高端芯片1的源极，经由若干寄生电感LDHS、LSHS、LDLS、LSLS，连接至低端芯片2的漏极。
对于这些器件来说，如果可以同时封装高端芯片和低端芯片，在封装体内部以引线连接这两个芯片，就能够减小引线电感。实际操作时，一般将高端芯片和低端芯片并排布置在引线框架的同一边，但是这样的平面布置使得整个器件的尺寸会比较大。
发明内容
本发明的目的是提供一种联合封装高端和低端芯片的半导体器件及其制造方法，通过将高端芯片和低端芯片分别连接在引线框架的两边，使三者堆叠起来以减小整个器件的尺寸；并且，可以将芯片背面直接暴露或经由散热片暴露在封装体以外，来改善散热性能。
为了达到上述目的，本发明的一个技术方案是提供一种联合封装高端和低端芯片的半导体器件，其包含
导电的引线框架，其设置有载片基座；
高端芯片和低端芯片，其各自设置有顶部源极、顶部栅极和底部漏极；其中所述高端芯片的顶部源极上植设有若干导电的源极焊球，顶部栅极上植设有若干导电的栅极焊球；
所述低端芯片的背面固定连接至引线框架的正面，并且使该低端芯片的底部漏极电性连接在载片基座的顶面；所述高端芯片的正面固定连接至引线框架的背面，并且使该高端芯片的顶部源极通过所述若干源极焊球电性连接至载片基座的底面；
所述半导体器件还包含封装体，将依次堆叠布置的低端芯片、引线框架的载片基座、高端芯片塑封在所述封装体中，而使所述高端芯片的背面暴露在所述半导体器件背面的封装体以外来进行散热。
所述引线框架还包含与所述载片基座分隔开且无电性连接的第一、第二、第三引脚，以及与所述载片基座电性连接的第四引脚。
所述低端芯片的底部漏极与所述高端芯片的顶部源极，分别连接在载片基座的两面，从而一起通过所述第四引脚与外部器件进行电性连接。
所述高端芯片的顶部栅极通过若干栅极焊球，电性连接至所述第三引脚。
在所述高端芯片的背面覆盖有一散热件；器件封装后，所述散热件暴露在器件背面的封装体以外；所述高端芯片的底部漏极通过所述暴露的散热件与外部器件电性连接。
所述散热件是在所述高端芯片背面，通过蒸发溅射形成的具有一定厚度的金属层。或者，所述散热件是在所述高端芯片背面粘贴的一个导电的金属贴片。
所述低端芯片的顶部源极，通过设置的一个金属连接片，电性连接至所述第一引脚；所述低端芯片的顶部栅极，通过设置的另一个金属连接片，电性连接至所述第二引脚。
所述金属连接片与所述低端芯片之间，所述金属连接片与所述第一引脚、第二引脚之间，分别设置有使其对应粘贴并电性连接的高温合金。
在所述低端芯片与所述引线框架的载片基座之间，设置有使两者相互粘贴并电性连接的高温合金。
所述高端芯片的顶部源极、顶部栅极上，对应植设的若干焊球分别是由低温合金制成。
本发明的另一个技术方案是提供一种联合封装高端和低端芯片的半导体器件的制作方法，其包含以下步骤：
步骤1、由导电材料制作一条引线框架；对应每个半导体器件，在所述引线框架上设置有载片基座；
步骤2、在一低端半导体晶圆的正面，对应制作多个低端芯片的顶部源极和顶部栅极；在该晶圆的背面，对应制作所述多个低端芯片的底部漏极；将晶圆切割分离，形成所述多个低端芯片；
步骤3、在一高端半导体晶圆的正面，对应制作多个高端芯片的顶部源极和顶部栅极；在该晶圆的背面，对应制作所述多个底端芯片的底部漏极；在高端芯片的顶部源极和顶部栅极上通过植球，对应形成有若干导电的源极焊球和栅极焊球；之后将晶圆切割分离，形成多个所述高端芯片；
步骤4、低端芯片正面朝上，将低端芯片的背面粘贴在引线框架的正面，使其底部漏极电性连接在载片基座的顶面上；
步骤5、翻转所述引线框架使其背面朝上；使所述高端芯片的正面朝下，将高端芯片的正面粘贴到引线框架的背面，使其顶部源极通过若干源极焊球，电性连接在载片基座朝上的底面，从而与所述低端芯片的底部漏极电性连接；
步骤6、通过模压方式，将依次堆叠的低端芯片、引线框架的载片基座、高端芯片全部塑封在封装体内，而使所述高端芯片的背面暴露在所述半导体器件背面的封装体以外，实现其底部漏极与外部器件的电性连接并进行散热；
步骤7、通过切筋成型的方式，将引线框架上的各个半导体器件分离。
步骤3中，通过漏极金属化工艺，在高端芯片的背面蒸发溅射形成具有一定厚度的金属层，或者在该高端芯片的背面粘贴有一导电的金属贴片；
在经过步骤6所述器件封装之后，所述金属层或金属贴片，暴露在器件背面的封装体以外来进行散热。
步骤1中，对应每个半导体器件，在所述引线框架上还设置了与所述载片基座分隔开且无电性连接的第一、第二、第三引脚，以及与载片基座电性连接的第四引脚。
步骤4中，所述低端芯片的顶部源极和顶部栅极，分别通过金属连接片电性连接至引线框架的所述第一引脚和第二引脚上。
步骤5中，所述高端芯片的顶部栅极通过所述若干栅极焊球，电性连接在引线框架的第三引脚上。
步骤5之后，所述低端芯片的底部漏极与所述高端芯片的顶部源极，分别连接在载片基座的两面，从而一起通过所述第四引脚与外部器件进行电性连接。
步骤4中，使用高温合金，作为所述低端芯片与载片基座之间，所述金属连接片与低端芯片之间，所述金属连接片与所述第一引脚、第二引脚之间电性连接的粘接材料。
步骤3中，所述高端芯片的顶部源极和顶部栅极上对应植设的若干焊球，是分别由低温合金制成的。
本发明所述联合封装高端和低端芯片的半导体器件中，低端芯片和高端芯片分别位于引线框架的上下两边，三者形成了立体堆叠的结构；相比现有技术中将低端和高端芯片并排贴附在引线框架同一边的结构，本发明有效减小了整个器件的尺寸。另外，本发明将高端芯片底部漏极上覆盖的金属层或导电的金属贴片作为散热片，暴露设置在封装后的器件背面之外，能够有效改善器件的散热性能。
附图说明
图1是现有技术中同步降压变流器的电路模型，其中高端芯片的源极电性连接至低端芯片的漏极；
图2是本发明所述联合封装高端和低端芯片的半导体器件中引线框架的结构示意图；
图3是本发明所述半导体器件中低端芯片与引线框架连接的示意图；
图4是本发明所述半导体器件中高端芯片的结构示意图；
图5是本发明所述半导体器件中高端芯片与引线框架连接的示意图；
图6是本发明所述半导体器件中低端芯片、高端芯片分别连接在引线框架上下两面的侧视图；
图7是本发明所述半导体器件在封装后的正面结构示意图；
图8是本发明所述半导体器件在封装后的背面结构示意图；
图9是本发明所述半导体器件在分离后的正面结构示意图；
图10是本发明所述半导体器件在分离后的背面结构示意图；
图11是本发明所述半导体器件在分离后的侧剖视图。
具体实施方式
以下结合附图说明本发明的具体实施方式。
配合参见图2～图11所示，本发明提供一种联合封装高端和低端芯片的半导体器件及其制造方法，图11是该半导体器件整体结构的侧剖视图。所述的半导体器件中包含一引线框架100，以及分别连接在该引线框架100上下两边的低端芯片200和高端芯片300。所述低端芯片200和高端芯片300中，栅极和源极分别位于芯片的顶部，漏极位于芯片的底部。
如图2所示，所述引线框架100上包含一载片基座110，以及在该载片基座110周边设置的若干引脚，该些引脚与载片基座110处在同一平面内。其中，第一引脚121、第二引脚122、第三引脚123，与所述载片基座110相互分隔且没有电性连接，将分别作为低端源极引脚、低端栅极引脚和高端栅极引脚；第四引脚124，与所述载片基座110连接为一体或是由载片基座110延伸形成，将同时作为高端漏极引脚及低端源极引脚。
配合参见图3、图6、图11所示，将低端芯片200背面粘贴到引线框架100上，使其底部漏极电性连接在载片基座110的顶面上。设置两个金属连接片230(例如铜片)，使其中一个金属连接片230的两端分别粘贴在低端芯片200的顶部源极211与引线框架100的第一引脚121上，另一个金属连接片230的两端分别粘贴在低端芯片200的顶部栅极212与引线框架100的第二引脚122上；也可以使用连接带、连接引线或其他导电的连接体来替代所述金属连接片230，以实现所述低端芯片200的源极211、栅极212与引线框架100上对应引脚的电性连接。在一个较佳实施例中，低端芯片200的顶部源极211用一个金属连接片电性连接到引线框架100的第一引脚121上，低端芯片200的顶部栅极212用一个连接引线电性连接到引线框架100的第二引脚121上。在进行上述芯片与引线框架100，金属连接片230与芯片或引脚之间的电性连接时，都可以使用高温合金220作为粘接的材料。
配合参见图4、图5、图6、图11所示，所述高端芯片300顶部的栅极和源极上通过植球，对应形成了若干源极焊球311和栅极焊球312，该些焊球分别由低温合金制成。通过蒸发溅射Ti/Ni/Ag(钛/镍/银)，在高端芯片300的背面形成有一定厚度的金属层320；或者，将一导电的金属贴片320’粘贴在高端芯片300的背面。将所述高端芯片300正面粘贴在引线框架100的背面，使对应高端芯片300源极设置的若干源极焊球311，电性连接至载片基座110的底面，而使对应高端芯片300栅极设置的栅极焊球312，电性连接至所述的第三引脚123。根据上述可知，高端芯片300的源极与低端芯片200的漏极，电性连接在载片基座110的两面，因此将一起通过第四引脚124与外部器件连通。
配合参见图6～图11所示，通过模压方式，将至上而下堆叠的低端芯片200、引线框架100的载片基座110、高端芯片300全部塑封在封装体400内；三者立体布置能够减小整个器件的尺寸。此时，所述第一至第四引脚，各自暴露在封装体400之外的部分经过弯折，使引脚端部与该器件的背面处在同一水平面上。另外，所述高端芯片300背面的金属层320或金属贴片320’，不仅对底部漏极起保护作用，并且可以在封装后暴露在器件的背面以外，实现高端芯片300底部漏极与外部器件电性连接的同时，还可以帮助器件散热。在一个较佳实施例中，连接低端芯片200的顶部源极211和引线框架100的第一引脚121的金属连接片230有一个顶面暴露在封装体400之外(未显示)以进一步帮助器件散热。
以下介绍制作上述联合封装高端和低端芯片的半导体器件的方法，具体包含以下步骤：
步骤1、由导电材料制作一条引线框架100；
如图2所示，对应每个半导体器件，在所述引线框架100上的同一个平面设置有载片基座110，与所述载片基座110分隔开的第一、第二、第三引脚，以及与载片基座110相连通的第四引脚124。
步骤2、在一低端半导体晶圆上，对应制作多个低端芯片200；
使各个低端芯片200的栅极212和源极211分别形成在该晶圆的正面，各个低端芯片200的漏极形成在该晶圆的背面。
将晶圆切割分离，形成多个所述低端芯片200。
步骤3、在一高端半导体晶圆上，对应制作多个高端芯片300；
如图4所示，使各个高端芯片300的栅极和源极分别形成在该晶圆的正面，各个高端芯片300的漏极形成在该晶圆的背面。
高端芯片300顶部的栅极和源极上通过植球，对应形成了若干源极焊球311和栅极焊球312，该些焊球分别由低温合金制成。
高端芯片300的背面通过金属化工艺，蒸发溅射了Ti/Ni/Ag(钛/镍/银)以形成具有一定厚度的金属层320；或者，在该高端芯片300的背面粘贴有一导电的金属贴片320’。
将晶圆切割分离，形成多个所述高端芯片300。
步骤4、将低端芯片200背面粘贴在引线框架100正面上；
如图3所示，低端芯片200的正面朝上，使其底部漏极电性连接在载片基座110的顶面上；而其顶部的源极和栅极，分别通过金属连接片230(或连接带或连接引线或类似的导电连接体)电性连接至引线框架100的第一引脚121和第二引脚122上。
可以使用高温合金220，作为上述低端芯片200与载片基座110，金属连接片230与低端芯片200，或金属连接片230与引脚之间电性连接的粘接材料。
步骤5、将高端芯片300的正面粘贴到引线框架100的背面；
如图5所示，翻转所述引线框架100使其背面朝上。所述高端芯片300的正面朝下，使其顶部的源极通过若干源极焊球311，电性连接在载片基座110朝上的底面；使其顶部的栅极通过栅极焊球312，电性连接在引线框架100的第三引脚123上。
步骤6、通过模压方式，将堆叠的低端芯片200、引线框架100的载片基座110、高端芯片300塑封在封装体400内；
配合参见图6～图8所示，在封装后的器件背面，使所述高端芯片300背面的金属层320或金属贴片320’暴露在封装体400以外，实现底部漏极与外部器件的电性连接，同时帮助器件散热。在一个较佳实施例中，连接低端芯片200的顶部源极211和引线框架100的第一引脚121的金属连接片230有一个顶面暴露在封装体400之外(未显示)以进一步帮助器件散热。
步骤7、通过切筋成型(Trim/Form)的方式，将引线框架100上的各个器件分离；
配合参见图9～图11所示，在若干引脚暴露在封装体400以外的部分进行切割使各个器件分离。并且，使引脚外露的端部在经过弯折后，与器件的背面处在同一水平面。
至此，完成整个半导体器件的制作。其中，所实施的步骤可以按不同的次序，比如，步骤1，2和3的次序可以任意改变，步骤4和5的次序也可以任意改变。另外，一个步骤中的几个动作也可以与另一步骤中的几个动作互相穿插，比如，步骤4中分别通过金属连接片230(或连接带或连接引线或类似的导电连接体)电性连接至引线框架100的第一引脚121和第二引脚122上的子步骤也可以在步骤5完成后再进行。因此上述方法中所引用的步骤顺序，并不等于要求在时间上严格遵守所引用的步骤顺序，而在于对器件的制作过程中不同操作任务的方便分类。综上所述，本发明所述半导体器件中，低端芯片和高端芯片分别位于引线框架的上下两边，三者形成了立体堆叠的结构；相比现有技术中将低端和高端芯片并排贴附在引线框架同一边的结构，本发明有效减小了整个器件的尺寸。另外，本发明将高端芯片底部漏极上覆盖的金属层或导电的金属贴片作为散热片，暴露设置在封装后的器件背面之外，能够有效改善器件的散热性能。本发明还可以将连接低端芯片的顶部源极和引线框架的金属连接片的一个顶面暴露在器件顶面之外以进一步帮助器件散热。
尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。

Claims (18)

1.一种联合封装高端和低端芯片的半导体器件，其特征在于，包含
导电的引线框架(100)，其设置有载片基座(110)，与所述载片基座(110)分隔开且无电性连接的第一、第二、第三引脚(121、122、123)，以及与所述载片基座(110)电性连接的第四引脚(124)；
低端芯片(200)和高端芯片(300)，其各自设置有顶部源极、顶部栅极和底部漏极；其中所述高端芯片(300)的顶部源极上植设有若干导电的源极焊球(311)，顶部栅极上植设有若干导电的栅极焊球(312)；
所述低端芯片(200)的背面固定连接至引线框架(100)的正面，并且使该低端芯片(200)的底部漏极电性连接在载片基座(110)的顶面；所述高端芯片(300)的正面固定连接至引线框架(100)的背面，并且使该高端芯片(300)的顶部源极通过所述若干源极焊球(311)电性连接至载片基座(110)的底面；
所述半导体器件还包含封装体(400)，将依次堆叠布置的低端芯片(200)、引线框架(100)的载片基座(110)、高端芯片(300)塑封在所述封装体(400)中，而使所述高端芯片(300)的背面暴露在所述半导体器件背面的封装体(400)以外来进行散热。
2.如权利要求1所述联合封装高端和低端芯片的半导体器件，其特征在于，
所述低端芯片(200)的底部漏极与所述高端芯片(300)的顶部源极，分别连接在载片基座(110)的两面，从而一起通过所述第四引脚(124)与外部器件进行电性连接。
3.如权利要求1所述联合封装高端和低端芯片的半导体器件，其特征在于，
所述高端芯片(300)的顶部栅极通过若干栅极焊球(312)，电性连接至所述第三引脚(123)。
4.如权利要求1所述联合封装高端和低端芯片的半导体器件，其特征在于，
所述低端芯片(200)的顶部源极，通过设置的一个金属连接片(230)，电性连接至所述第一引脚(121)；所述低端芯片(200)的顶部栅极，通过设置的另一个金属连接片(230)，电性连接至所述第二引脚(122)。
5.如权利要求4所述联合封装高端和低端芯片的半导体器件，其特征在于，
所述金属连接片(230)与所述低端芯片(200)之间，所述金属连接片(230)与所述第一引脚(121)、第二引脚(122)之间，分别设置有使其对应粘贴并电性连接的高温合金(220)。
6.一种联合封装高端和低端芯片的半导体器件，其特征在于，包含
导电的引线框架(100)，其设置有载片基座(110)；
低端芯片(200)和高端芯片(300)，其各自设置有顶部源极、顶部栅极和底部漏极；其中所述高端芯片(300)的顶部源极上植设有若干导电的源极焊球(311)，顶部栅极上植设有若干导电的栅极焊球(312)；
所述低端芯片(200)的背面固定连接至引线框架(100)的正面，并且使该低端芯片(200)的底部漏极电性连接在载片基座(110)的顶面；所述高端芯片(300)的正面固定连接至引线框架(100)的背面，并且使该高端芯片(300)的顶部源极通过所述若干源极焊球(311)电性连接至载片基座(110)的底面；
所述半导体器件还包含封装体(400)，将依次堆叠布置的低端芯片(200)、引线框架(100)的载片基座(110)、高端芯片(300)塑封在所述封装体(400)中，使所述高端芯片(300)的背面及覆盖在该高端芯片(300)背面的一散热件，暴露在所述半导体器件背面的封装体(400)以外来进行散热；所述高端芯片(300)的底部漏极通过所述暴露的散热件与外部器件电性连接。
7.如权利要求6所述联合封装高端和低端芯片的半导体器件，其特征在于，
所述散热件是在所述高端芯片(300)背面，通过蒸发溅射形成的具有一定厚度的金属层(320)。
8.如权利要求6所述联合封装高端和低端芯片的半导体器件，其特征在于，
所述散热件是在所述高端芯片(300)背面粘贴的一个导电的金属贴片(320’)。
9.一种联合封装高端和低端芯片的半导体器件，其特征在于，包含
导电的引线框架(100)，其设置有载片基座(110)；
低端芯片(200)和高端芯片(300)，其各自设置有顶部源极、顶部栅极和底部漏极；其中所述高端芯片(300)的顶部源极上植设有若干导电的源极焊球(311)，顶部栅极上植设有若干导电的栅极焊球(312)；
所述低端芯片(200)的背面固定连接至引线框架(100)的正面，并且使该低端芯片(200)的底部漏极电性连接在载片基座(110)的顶面；其中，在所述低端芯片(200)与所述引线框架(100)的载片基座(110)之间，设置有使两者相互粘贴并电性连接的高温合金(220)；
所述高端芯片(300)的正面固定连接至引线框架(100)的背面，并且使该高端芯片(300)的顶部源极通过所述若干源极焊球(311)电性连接至载片基座(110)的底面；
所述半导体器件还包含封装体(400)，将依次堆叠布置的低端芯片(200)、引线框架(100)的载片基座(110)、高端芯片(300)塑封在所述封装体(400)中，而使所述高端芯片(300)的背面暴露在所述半导体器件背面的封装体(400)以外来进行散热。
10.一种联合封装高端和低端芯片的半导体器件，其特征在于，包含
导电的引线框架(100)，其设置有载片基座(110)；
低端芯片(200)和高端芯片(300)，其各自设置有顶部源极、顶部栅极和底部漏极；其中，所述高端芯片(300)的顶部源极上植设有若干导电的源极焊球(311)，顶部栅极上植设有若干导电的栅极焊球(312)；所述源极焊球(311)和栅极焊球(312)分别由低温合金制成；
所述低端芯片(200)的背面固定连接至引线框架(100)的正面，并且使该低端芯片(200)的底部漏极电性连接在载片基座(110)的顶面；所述高端芯片(300)的正面固定连接至引线框架(100)的背面，并且使该高端芯片(300)的顶部源极通过所述若干源极焊球(311)电性连接至载片基座(110)的底面；
所述半导体器件还包含封装体(400)，将依次堆叠布置的低端芯片(200)、引线框架(100)的载片基座(110)、高端芯片(300)塑封在所述封装体(400)中，而使所述高端芯片(300)的背面暴露在所述半导体器件背面的封装体(400)以外来进行散热。
11.一种联合封装高端和低端芯片的半导体器件的制作方法，其特征在于，包含以下步骤：
步骤1、由导电材料制作一条引线框架(100)；对应每个半导体器件，在所述引线框架(100)上设置有载片基座(110)；
步骤2、在一低端半导体晶圆的正面，对应制作多个低端芯片(200)的顶部源极(211)和顶部栅极(212)；在该晶圆的背面，对应制作所述多个低端芯片(200)的底部漏极；将晶圆切割分离，形成所述多个低端芯片(200)；
步骤3、在一高端半导体晶圆的正面，对应制作多个高端芯片(300)的顶部源极和顶部栅极；在该晶圆的背面，对应制作所述多个高端芯片(300)的底部漏极；在高端芯片(300)的顶部源极和顶部栅极上通过植球，对应形成有若干导电的源极焊球(311)和栅极焊球(312)；之后将晶圆切割分离，形成多个所述高端芯片(300)；
步骤4、低端芯片(200)正面朝上，将低端芯片(200)的背面粘贴在引线框架(100)的正面，使其底部漏极电性连接在载片基座(110)的顶面上；
步骤5、翻转所述引线框架(100)使其背面朝上；使所述高端芯片(300)的正面朝下，将高端芯片(300)的正面粘贴到引线框架(100)的背面，使其顶部源极通过若干源极焊球(311)，电性连接在载片基座(110)朝上的底面，从而与所述低端芯片(200)的底部漏极电性连接；
步骤6、通过模压方式，将依次堆叠的低端芯片(200)、引线框架(100)的载片基座(110)、高端芯片(300)全部塑封在封装体(400)内，而使所述高端芯片(300)的背面暴露在所述半导体器件背面的封装体(400)以外，实现其底部漏极与外部器件的电性连接并进行散热；
步骤7、通过切筋成型的方式，将引线框架(100)上的各个半导体器件分离。
12.如权利要求11所述联合封装高端和低端芯片的半导体器件的制作方法，其特征在于，
步骤3中，通过漏极金属化工艺，在高端芯片(300)的背面蒸发溅射形成具有一定厚度的金属层(320)，或者在该高端芯片(300)的背面粘贴有一导电的金属贴片(320’)；
在经过步骤6所述器件封装之后，所述金属层(320)或金属贴片
(320’)，暴露在器件背面的封装体(400)以外来进行散热。
13.如权利要求11所述联合封装高端和低端芯片的半导体器件的制作方法，其特征在于，
步骤1中，对应每个半导体器件，在所述引线框架(100)上还设置了与所述载片基座(110)分隔开且无电性连接的第一、第二、第三引脚(121、122、123)，以及与载片基座(110)电性连接的第四引脚(124)。
14.如权利要求13所述联合封装高端和低端芯片的半导体器件的制作方法，其特征在于，
步骤4中，所述低端芯片(200)的顶部源极(211)和顶部栅极(212)，分别通过金属连接片(230)电性连接至引线框架(100)的所述第一引脚(121)和第二引脚(122)上。
15.如权利要求13所述联合封装高端和低端芯片的半导体器件的制作方法，其特征在于，
步骤5中，所述高端芯片(300)的顶部栅极通过所述若干栅极焊球(312)，电性连接在引线框架(100)的第三引脚(123)上。
16.如权利要求13所述联合封装高端和低端芯片的半导体器件的制作方法，其特征在于，
步骤5之后，所述低端芯片(200)的底部漏极与所述高端芯片(300)的顶部源极，分别连接在载片基座(110)的两面，从而一起通过所述第四引脚(124)与外部器件进行电性连接。
17.如权利要求14所述联合封装高端和低端芯片的半导体器件的制作方法，其特征在于，
步骤4中，使用高温合金(220)，作为所述低端芯片(200)与载片基座(110)之间，所述金属连接片(230)与低端芯片(200)之间，所述金属连接片(230)与所述第一引脚(121)、第二引脚(122)之间电性连接的粘接材料。
18.如权利要求11所述联合封装高端和低端芯片的半导体器件的制作方法，其特征在于，
步骤3中，所述高端芯片(300)的顶部源极和顶部栅极上对应植设的若干焊球，是分别由低温合金制成的。
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