TWI406372B - 具有立體匹配互聯板的緊密封裝半導體晶片 - Google Patents

具有立體匹配互聯板的緊密封裝半導體晶片 Download PDF

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TWI406372B
TWI406372B TW098126649A TW98126649A TWI406372B TW I406372 B TWI406372 B TW I406372B TW 098126649 A TW098126649 A TW 098126649A TW 98126649 A TW98126649 A TW 98126649A TW I406372 B TWI406372 B TW I406372B
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Taiwan
Prior art keywords
wafer
semiconductor package
circuit substrate
contact region
semiconductor
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TW098126649A
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English (en)
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TW201007905A (en
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劉凱
孫明
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萬國半導體股份有限公司
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Publication of TW201007905A publication Critical patent/TW201007905A/zh
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Description

具有立體匹配互聯板的緊密封裝半導體晶片
本發明涉及電子系統封裝領域，特別涉及一種半導體晶片的物理級封裝。
本發明與以下專利申請有關：由Lei Shi等人申請的美國專利申請號11/906,136“具有橋連接板互連接的半導體封裝”，公開號US20080087992，此後以美國申請11/906136稱呼；由Ming Sun等人申請的美國專利申請號11/799,467“具有凹陷型互聯板的半導體封裝”，此後以美國申請11/799467稱呼。
由於功率金屬氧化物半導體場效應晶體(metal-oxide-semiconductor field effect transistor，簡稱MOSFET)器件的高集成密度、極低的靜態漏電流和不斷改進的功率處理能力，它們被廣泛的用在功率電子產品中，例如開關式電源和電源轉換器，功率MOSFET器件的一個重要優勢是其封裝尺寸隨著消費者的需求的驅使而不斷減小，尤其體現在可擕式電子設備中。
本發明公開了一種半導體封裝，其包括：一個電路基底；兩個半導體晶片，其底部表面與電路基底的上面電連接，所述半導體晶片進一步包括：第一晶片的邊界為第一晶片第一縱向邊緣和第一晶片第二縱 向邊緣，第一晶片第一橫向邊緣和第一晶片第二橫向邊緣；第二晶片的邊界為第二晶片第一縱向邊緣和第二晶片第二縱向邊緣，第二晶片第一橫向邊緣和第二晶片第二橫向邊緣；第一晶片和第二晶片位置鄰近並且是相互獨立的，沿著它們各自第一晶片第二縱向邊緣和第二晶片第一縱向邊緣，設有內部晶片間距；一個立體匹配電連接，連接第二晶片表面上的頂部金屬接觸區和第一晶片底部表面，用來適配表面之間的高度差異，所述立體匹配電連接進一步包括：a)一個電路路徑，該路徑是電路基底的一部分，作為第一晶片的底部表面到電路基底上的中間接觸區的電路徑，所述的電路徑進一步包括L形路徑，該路徑從第一晶片第二橫向邊緣靠近第一晶片第二縱向邊緣的位置橫向延伸，將中間接觸區靠近第二晶片第二橫向邊緣；b)一個互聯板連接第二晶片頂部金屬接觸區和中間接觸區，所述中間接觸為三維的，用來適配接觸區之間的立體高度差；因而，半導體封裝減少了第一晶片第二縱向邊緣和第二晶片第一縱向邊緣之間的橫向電路路徑的內部晶片間距。
作為上述的半導體封裝的一個優選實施方式，所述互聯板還包括一個橋部分，設置在橋部分兩邊的穀部分，設置在穀部分、橋部分或平面之間連接部分兩邊的平面部分。
作為上述的半導體封裝的一個優選實施方式，所述互聯板還包括用來與第二晶片頂部金屬接觸區接觸的凹點。
作為上述的半導體封裝的另一個優選實施方式，至少有一個所述第一晶片和第二晶片還包括至少一個額外的頂部金屬接觸區，相應地，半導體封裝還包括一個額外的互聯板連接額外頂部金屬接觸區和電路基底，該互聯板是三維的用來適配他 們之間存在的立體高度差。
作為上述的半導體封裝的另一個優選實施方式，還包括一個橋部分，設置在橋部分兩邊的穀部分，設置在穀部分、橋部分或平面之間連接部分兩邊的平面部分，裸露在模塑膠外的互聯板的頂部表面為橋部分，用來散熱。
作為上述的半導體封裝的一個優選實施方式，所述電路基底設有第一晶片墊和第二晶片墊分別用來定位和連接第一晶片和第二晶片，相應地，L形路徑是從第一晶片墊和第一晶片的上表面的頂部金屬接觸區的延伸，通過一個互聯板與引線框引腳連接。
作為上述的半導體封裝的另一個優選實施方式，大部分用模塑膠封裝，僅暴露頂部表面的互聯板用來散熱。
作為上述的半導體封裝的另一個優選實施方式，所述電路基底是絕緣襯底，該絕緣襯底設有一個第一導電表面和一個第二導電表面分別用來定位和連接所述第一晶片和所述第二晶片，相應地，所述L形路徑是從第一導電表面延伸出來的導電電路路徑。
作為上述的半導體封裝的一個更加優選實施方式，所述的第一晶片和第二晶片都是MOSFET器件，它們的底表面分別漏接觸，他們的頂部表面分別為金屬源接觸和金屬柵接觸，以立體匹配電連接方式連接第二晶片的金屬源接觸區和第一晶片的漏接觸區，不需要倒裝晶片工藝。MOSFET的柵通過互聯線或互聯板連接電路基底。
本發明還提供了一種有效連接多個、獨立和三維互聯板的方法，每個都是設定好尺寸設置在具有一對連接半導體頂部的匹配電路基底上，該方法包括： a)製作一個多板載體框，具有多個互聯板完整的支撐和多個臨時支撐成分；b)通過破壞臨時支撐成分將獨立的互聯板從多個載體框中分離出來；c)將每個互聯板設置在設配電路基底上；每個互聯板進一步包括一個從半導體晶片頂部到中間接觸區的互聯板，其中的中間接觸區包括從其他半導體晶片底部延伸出來的L形電路路徑。
作為上述的製作方法的一個改進實施方式，製作多板載體邊框進一步包括用一個樣板刀三維製作互聯板。
作為上述的製作方法的一個優選實施方式，分開多板載體邊框還包括用沖孔工具將其分開。
作為上述的製作方法的一個優選實施方式，分開多板載體框還包括分開每個電路基底上的相互獨立的互聯板，於此同時將獨立互聯板從多板載體邊框中分開。
作為上述的製作方法的一個優選實施方式，將每個互聯板設置到匹配電路基底上的同時用多個頂部支撐板。
作為上述方法的一個優選實施方式，進一步包括封裝至少電路基底的一部分，多個半導體晶片和互聯板。
本發明的這些方面、他們的很多實施例以及本發明描述的其他部分將給本領域技術人員做進一步說明。
本發明的半導體封裝減少了晶片橫向邊緣之間的直接橫向電路路徑的內部晶片間距。
上述和下述之說明以及附圖僅僅用於集中描述本發明的一個或多個實施例以及若干可選功能和/或可選實施例。這些 描述和附圖僅做闡述之用而非限制本發明。因此，本領域的技術人員可以輕易的對本發明作出修改、變形和替換。然而這些修改、變形和替換應該認為仍落在本發明的範圍之內。
第1圖是一組相連的低壓(low-side，LS)和高壓(high-side,HS)功率MOSFET電路結構圖。低壓(LS)的源1a接地，一般情況下，高壓(HS)的漏極2c直接或間接的與電源正極相連。低壓(LS)漏極1c與高壓(HS)源極2a連接。本領域的技術人員知道，通常選擇性的給低壓(LS)的柵極1b和高壓(HS)的柵極2b加高壓使低壓(LS)MOSFET1和高壓(HS)MOSFET2導通，這樣的拓撲結構存在於很多整流器和調節器中。
低壓(LS)MOSFET 1和高壓(HS)MOSFET 2製造簡單並且成本低，與之對應的相關製造半導體晶片，器件的漏極接觸通常位於底部襯底表面，其源極接觸通常佔據襯底頂部表面，其柵極接觸佔據襯底頂部表面的一小部分。這樣，沒有複雜昂貴的倒裝晶片工藝，第2圖描述了已有技術中，對於低壓(LS)MOSFET 1和高壓(HS)MOSFET 2的半導體封裝5的頂視圖，如圖，分別為低壓(LS)晶片10和高壓(HS)晶片20、引線框8，因此，LS晶片10設有一個LS晶片頂部金屬源極接觸區10a，一個LS晶片頂部金屬柵極接觸區10b和一個LS晶片底部金屬漏極接觸區10c，類似的，HS晶片設有一個HS晶片頂部金屬源極接觸區20a，一個HS晶片頂部金屬柵極接觸區20b和一個HS晶片底部金屬漏極接觸區20c。注意LS晶片10的邊緣分別為第一LS晶片縱向邊緣11，第二LS晶片縱向邊緣13，第一LS晶片橫向邊緣12和第二LS晶片橫向邊緣14，類似的，HS晶片20的邊緣分別為第一HS晶片縱向邊緣21，第二HS晶片縱向邊緣23，第一HS晶片橫向邊緣22和第二 HS晶片橫向邊緣24。引線框8包括大量的物理和電學上分離的引線部分8a，8b(進一步包括8f)，8c，8d和8e。引線部分8a-8e可能但不是必需是共面。底部表面，例如，LS晶片10和HS晶片20的漏極接觸區分別電連接到引線部分8a和引線部分8b。LS晶片頂部金屬源極接觸區10a通過橫向LS終端連接線16連接引線部分8e，LS晶片頂部金屬柵極接觸區10b通過橫向連接線9a連接引線部分8c。HS晶片頂部金屬柵極接觸區20b通過縱向連接線9b連接引線部分8d。LS晶片底部金屬漏極接觸區10c電連接到引線部分8a的頂部表面，橫向LS-HS互聯線18，連接引線部分8a和HS晶片頂部金屬源極接觸區20a,從而是實現LS晶片底部金屬漏極接觸區10c和HS晶片頂部金屬源極接觸區20a之間所需的連接，最後用密封材料6封裝部分或整個的LS晶片10和HS晶片20，僅露出引線部分8a~8f週邊部分用於外部的連接。
和封裝有關的一個重要參數為內部晶片間距IDA，它是指第二LS晶片縱向邊緣13和第一HS晶片縱向邊緣21之間的間距。內部晶片間距IDA制約了已有技術中半導體封裝5的橫向方向的最小封裝尺寸。對於給定的封裝尺寸，內部晶片間距IDA限制了晶片的尺寸，因而增加了器件的導通電阻。下面已有的基本參數限定了內部晶片間距IDA的對應的基本最小值：最小橫向晶片-引線框邊緣A1，是指第二LS晶片縱向邊緣13和其最近的引線框部分8a縱向邊緣之間的橫向間距。
最小橫向晶片-引線框邊緣A2，是指第一HS晶片縱向邊緣21和其最近的引線框部分8b縱向邊緣之間的橫向間距。
最小橫向引線框-引線框間距A3，是指引線框部分8a和 引線框部分8b之間的橫向間距。關係：IDA=A1+A2+A3,橫向LS-HS互聯線18的實施使得橫向晶片-引線框邊緣A1和橫向引線框-引線框間距A3大於他們各自的基本最小值，因為產品設備的互聯機對於地互連端規定了更高的橫向晶片-引線框邊緣A1，對於最小需要的互聯環支撐物規定了更大的橫向引線框-引線框間距A3。
為了減小內部晶片間距IDA，從而相應減小現有技術中半導體封裝5沿橫向方向的尺寸，第3A圖和其透視圖第3B圖描述了本發明帶有一個內部晶片間距IDB的半導體封裝50。第2圖所示的橫向LS-HS互聯線18被一個立體匹配電連接所取代，該電連接用來連接HS晶片頂部金屬源極20a和LS晶片底部金屬漏極10c，這樣方便適應20a和10c表面之間的立體差。具體來說，立體匹配電連接包含如下：一個L形引線框路徑54是引線部分8a的一部分，因為電路徑是從LS晶片底部金屬漏極接觸區10c到引線框部分8a上面的裸露的中間接觸區52。L形引線框路徑54從靠近第二LS晶片橫向邊緣14的第二LS晶片縱向邊緣13橫向延伸出來，使中間接觸區52靠近第二HS晶片橫向邊緣24。
一個立體互聯板56以中間接觸區52連接HS晶片頂部金屬源極20a，立體互聯板56進一步三維結構連接從而適應20a和52表面立體差。
下面是規定內部晶片間距IDB基本最小值的基本參數：最小橫向晶片-引線框邊緣B1，是指第二LS晶片縱向邊緣13和其最近的引線部分8a的縱向邊緣之間的間距。
最小橫向晶片-引線框邊緣B2，是指第一HS晶片縱向邊緣21和其最近的引線部分8b的縱向邊緣之間的間距。
最小橫向引線邊框-引線邊框之間的間距B3，是指引線邊框部分8a和引線邊框部分8b之間的橫向間距。其關係為：IDB=B1+B2+B3,L形引線框路徑54和立體互聯板56不再需要橫向晶片-引線框邊緣B1和橫向引線框-引線框B3間距大於他們各自的基本最小值，因而本發明有效的減小了內部晶片間距，如下：IDB<IDA
減小的內部晶片間距IDB使元件包裝尺寸減小，二者取其一，對於相同的封裝尺寸，LS晶片10和HS晶片20可以做大，從而減小導通電阻。
進一步注意到，將中間接觸區52靠近HS晶片橫向邊緣24，引線框8a的L形引線框路徑54起重要的作用，由於本發明減小了內部晶片間距和相應的第二LS晶片縱向邊緣13和第一HS晶片縱向邊緣21之間的橫向電路路徑的半導體封裝尺寸。同樣的，已有半導體封裝技術中的橫向LS終端連接線16也被本發明半導體封裝50中的立體互聯板58所代替，具有減小寄生阻抗的優點，所述的代替不是本發明減小內部晶片的主要部分。用互聯板56取代第2圖中的互聯線18減小了高壓晶片20和低壓晶片10之間的感應係數。
第4圖描述了本發明半導體封裝50的另一個實施例，除了立體板56和58，其餘的封裝互聯也是用立體互聯板來完成。具體來講，一個立體互聯板60用來連接LS晶片頂部金屬柵極接觸區10b和引線框8c，一個立體互聯板62用來連接 HS晶片頂部金屬柵極接觸區20b到引線框8d。本領域的技術人員現在應該更清楚的知道，立體互聯板56和立體互聯板58還包括一個橋部分，橋部分任何一側的谷部分，穀部分、橋部分或平面之間連接部分的任何一側平面部分，US Application 11、906，136中有進一步詳述。本發明的半導體封裝50可以大部分封裝於密封材料6中，僅留下互聯板的橋部分用來散熱。同樣的，如第5圖所描述的，立體互聯板56和58其中一個或者都可以進一步包括接觸凹點70和72用來分別連接LS晶片頂部金屬源接觸區10a和HS晶片頂部金屬源接觸區20a,US Application 11/799,467有進一步的描述。
第6A圖和第3A圖相同，只是移去了立體互聯板56、58和連接線9a、9b，從而更清楚的顯示L型引線框路徑54和引線框8a中間接觸區52，為了避免多餘模糊的細節，這裏沒有顯示引線框8a和8b上的用於設置連接LS晶片10和HS晶片20的大量的晶片墊。
現在本技術領域的技術人員應該知道，一般而言，引線框8可以在本發明半導體封裝範圍內被大量其他種類的電路基底所取代，例如，印刷電路板可以取代引線框8。印刷電路板可以包括一個絕緣襯底，一個導電表面和一個導電表面分別用於設置和連接LS晶片10和HS晶片20。相應地，L型引線框路徑54由導電表面延伸出來的一個導電電路路徑構成。
第6B圖到第6D圖描述了一個多板載體邊框73和與此相關的有效連接多個，單個和三維的立體互聯板56、58、60和62到上面有半導體晶片的匹配電路基底上。這樣，匹配電路基底為引線框8，設置在上面的半導體晶片為LS晶片10和HS晶片20。
如第6B圖所示，一個多板載體邊框73由多個互聯板56、58、60和62、大量集成連接杆74和76構成，更為細化，互聯板可進一步與其他連接棒相互連接，製作多板載體邊框73進一步包括上面的三維成形互聯板，接著，藉由截斷連接杆74和76將獨立的互聯板56、58、60和62從多板載體邊框73中隔離。可以通過衝壓工具將其分開，然後每個互聯板可以用真空工具將其定位在適配電路基底上，細化工藝步驟，互聯板可獨立和同時附著在匹配電路基底上。另外一個工藝細化，每個電路基底上的獨立互聯板可以左置放置在一起分開多板載體邊框，然後將每個互聯板設置到適配的電路基底後，每個電路基底上的單個互聯板相互分開。最後，匹配電路基底和其封裝半導體晶片、互聯板用模塑膠封裝。
在本發明的內容中，每個互聯板進一步包括半導體晶片頂部到中間接觸區的互聯板連接部分，中間接觸區包括L形由從其他半導體晶片下面延伸出來的電路路徑。第6c圖是頂視圖描述用第6B圖的多板載體邊框連接的多個立體互聯板56、58、60和62，第6D圖是第6C圖的透視圖，將半導體晶片10，20和立體互聯板56，58，60和62向上浮動進一步露出邊框8、半導體晶片、L形邊框路徑54和立體互聯板。
現在本領域的技術人員應該瞭解，所描述的許多實例通過簡單的修改也可用到其他具體應用上，雖然上面的描述了很多特徵，但是其特徵並不構成對本發明範圍的限制。僅僅是提供本發明相關實例的說明。例如，本發明半導體封裝系統預期用到各種各樣的半導體晶片上，而不僅僅是本發明所描述的金屬氧化物半導體(MOSFET)晶片中。
在描述和圖形中，參照具體的結構給出了大量的實施例。 本技術領域的技術人員應該知道本發明可以應用到其他實施方式上，並且其他實施方式的實施不需要再經過試驗。本專利文獻的目的在於本發明的範圍不僅僅限於上述描述的具體實施例，而是為了說明以下申請專利範圍，在申請專利範圍範圍內，對等值含義和範圍做出的部分或全部修改，都被認為包含在本發明的精神和範圍內。
MOSFET‧‧‧功率金屬氧化物半導體場效應晶體
1b‧‧‧柵極
2b、2c‧‧‧漏極
5、50‧‧‧半導體封裝
IDA、IDB‧‧‧內部晶片間距
6‧‧‧密封材料
A1、A2、B1、B2‧‧‧最小橫向晶片-引線框邊緣
A3‧‧‧最小橫向引線框-引線框間距
8‧‧‧引線框
8a、8b、8c、8d、8e、8f‧‧‧引線部分
9a‧‧‧橫向連接線
9b‧‧‧縱向連接線
10‧‧‧低壓(LS)晶片
10a‧‧‧LS晶片頂部金屬源極接觸區
10b‧‧‧LS晶片頂部金屬柵極接觸區
10c‧‧‧LS晶片底部金屬漏極接觸區
11‧‧‧第一LS晶片縱向邊緣
12‧‧‧第一LS晶片橫向邊緣
13‧‧‧第二LS晶片縱向邊緣
14‧‧‧第二LS晶片橫向邊緣
16‧‧‧橫向LS終端連接線
18‧‧‧橫向LS-HS互聯線
20‧‧‧HS晶片
20a‧‧‧HS晶片頂部金屬源極接觸區
20b‧‧‧HS晶片頂部金屬柵極接觸區
20c‧‧‧HS晶片底部金屬漏極接觸區
21‧‧‧第一HS晶片縱向邊緣
22‧‧‧第一HS晶片橫向邊緣
23‧‧‧第二HS晶片縱向邊緣
24‧‧‧第二HS晶片橫向邊緣
B3‧‧‧最小橫向引線邊框-引線邊框之間的間距
52‧‧‧中間接觸區
54‧‧‧L形引線框路徑
56、58、60、62‧‧‧立體互聯板
70、72‧‧‧接觸凹點
73‧‧‧多板載體邊框
74、76‧‧‧連接杆
參考所附附圖，以更加充分的描述本發明的實施例。然而，所附附圖僅用於說明和闡述，並不構成對本發明範圍的限制。
第1圖是一組相連的低壓(low-side，LS)和高壓(high-side，HS)功率MOSFET電路結構圖；第2圖是現有技術同封裝半導體晶片引線框，本發明中的LS和HS功率MOSFET的互聯鍵合線與之對應；第3A圖是本發明在引線框中的同封裝半導體晶片，用立體匹配互聯板進行LS和HS功率MOSFET互聯；第3B圖是第3A圖的透視圖；第4圖是本發明同封裝半導體晶片在引線框中對應的LS和HS功率MOSFET用立體匹配互聯板進行全封裝互聯。
第5圖和第3B圖相同，除了每個立體匹配互聯板還包括微凹形用來連接對應的頂部金屬接觸區；第6A圖與第3A圖相同，但是去掉了立體連接板和互聯線， 更清楚的看到L形路線和引線框的中間接觸區；第6B圖是多板載體框架用來有效的將多個、分離的和三維成型立體連接板連接到上面有連接的半導體晶片的適配電路基底上。
第6C圖是頂視圖，用來說明用第6B圖中多板載體邊框連接立體互聯板；第6D圖是第6C圖的透視圖，使半導體晶片和立體互聯板浮在上面，露出引線框，半導體晶片和立體匹配互聯板。
IDB‧‧‧內部晶片間距
B2‧‧‧最小橫向晶片-引線框邊緣
8a、8b、8c、8d、8e、8f‧‧‧引線部分
9a‧‧‧橫向連接線
9b‧‧‧縱向連接線
10‧‧‧低壓(LS)晶片
10a‧‧‧LS晶片頂部金屬源極接觸區
10b‧‧‧LS晶片頂部金屬柵極接觸區
10c‧‧‧LS晶片底部金屬漏極接觸區
11‧‧‧第一LS晶片縱向邊緣
12‧‧‧第一LS晶片橫向邊緣
13‧‧‧第二LS晶片縱向邊緣
14‧‧‧第二LS晶片橫向邊緣
20‧‧‧HS晶片
20a‧‧‧HS晶片頂部金屬源極接觸區
20b‧‧‧HS晶片頂部金屬柵極接觸區
20c‧‧‧HS晶片底部金屬漏極接觸區
21‧‧‧第一HS晶片縱向邊緣
22‧‧‧第一HS晶片橫向邊緣
23‧‧‧第二HS晶片縱向邊緣
24‧‧‧第二HS晶片橫向邊緣
B3‧‧‧最小橫向引線邊框-引線邊框之間的間距
50‧‧‧半導體封裝
52‧‧‧間接觸區
54‧‧‧L形引線框路徑
56、58‧‧‧立體互聯板

Claims (23)

  1. 一種半導體封裝，其特徵在於，包括：一個電路基底；多個半導體晶片，所述半導體晶片的底部表面與上面的電路基底是電連接，所述半導體晶片進一步包括：第一晶片的邊界為第一晶片第一縱向邊緣和第一晶片第二縱向邊緣，另外加上第一晶片第一橫向邊緣和第一晶片第二橫向邊緣；第二晶片的邊界為第二晶片第一縱向邊緣和第二晶片第二縱向邊緣，另外加上第二晶片第一橫向邊緣和第二晶片第二橫向邊緣；所述第一晶片和第二晶片位置鄰近並且是獨立的，沿著它們各自第一晶片第二縱向邊緣和第二晶片第一縱向邊緣，設有內部晶片間距；一個立體匹配電連接，連接第二晶片表面上的頂部金屬接觸區和第一晶片底部表面，用來適配表面之間的差異，所述立體匹配電連接進一步包括：a)一個電路路徑方式，該路徑是電路基底的一部分，作為第一晶片的底部表面到電路基底上的中間接觸區的電路徑，所述的電路徑方式由L形路徑從第一晶片第二橫向邊緣靠近第一晶片第二縱向邊緣的位置橫向延伸，將中間接觸區靠近第二晶片第二橫向邊緣；b)一個互聯板連接第二晶片頂部金屬接觸區和中間接觸區，所述中間接觸為三維的，用來適配接觸區之間的立體高度差； 因而，半導體封裝減少了第一晶片第二縱向邊緣和第二晶片第一縱向邊緣之間的橫向電路路徑的內部晶片間距。
  2. 如申請專利範圍第1項所述的半導體封裝，其特徵在於，所述互聯板還包括一個橋部分，設置在橋部分兩邊的穀部分，設置在穀部分、橋部分或平面之間連接部分兩邊的平面部分。
  3. 如申請專利範圍第1項所述的半導體封裝，其特徵在於，所述互聯板還包括用來與頂部金屬接觸區接觸的凹點。
  4. 如申請專利範圍第1項所述的半導體封裝，其特徵在於，至少有一個所述第一晶片和第二晶片還包括至少一個額外的頂部金屬接觸區，相應地，半導體封裝還包括一個額外的互聯板連接額外頂部金屬接觸區和電路基底，該互聯板是三維的用來適配他們之間存在的立體高度差。
  5. 如申請專利範圍第1項所述的半導體封裝，其特徵在於，所述電路基底是一個引線框，該引線框還包括第一晶片墊和第二晶片墊用來分別定位和連接所述的第一晶片和所述的第二晶片，相對應的，所述L形路徑是所述第一晶片墊的延伸。
  6. 如申請專利範圍第5項所述的半導體封裝，其特徵在於，用互聯板將第一晶片上表面的頂部金屬接觸區與引線框引腳電連接。
  7. 如申請專利範圍第6項所述的半導體封裝，其特徵在於，還包括一個模塑膠，所述半導體封裝大部分封裝在模塑膠中，第一晶片上面的互聯板頂部表面露出模塑膠用來散熱。
  8. 如申請專利範圍第7項所述的半導體封裝，其特徵在於，第一晶片上面的互聯板還包括一個橋部分，設置在橋部分兩邊的穀部分，設置在穀部分、橋部分或平面之間連接部分兩邊的平面部分，互聯板裸露的頂部表面為橋部分一個部分。
  9. 如申請專利範圍第7項所述的半導體封裝，其特徵在於，所述電路基底是印刷電路板，還包括絕緣襯底，第一導電表面和第一導電表面2分別用來定位和連接所述第一晶片和所述第二晶片，相應地，所述L形路徑是從第一導電表面延伸出來的導電電路路徑。
  10. 如申請專利範圍第1項所述的半導體封裝，其特徵在於，所述的第一晶片和第二晶片都是MOSFET器件，它們的底表面分別漏接觸，他們的頂部表面分別為金屬源接觸和金屬柵接觸，立體匹配電連接連接第二晶片的金屬源接觸區和第一晶片的漏接觸區，不需要倒裝晶片工藝。
  11. 如申請專利範圍第10項所述的半導體封裝，其特徵在於，所述第一晶片是低壓金屬氧化物半導體場效應電晶體(MOSFET)器件，所述第二晶片是高壓金屬氧化物半導體場效應電晶體(MOSFET)器件。
  12. 如申請專利範圍第10項所述的半導體封裝，其特徵在於，所述MOSFET的柵通過互聯線連接電路基底。
  13. 如申請專利範圍第10項所述的半導體封裝，其特徵在於，所述MOSFET的柵通過互聯板連接電路基底。
  14. 如申請專利範圍第1項所述的半導體封裝，其特徵在於，所述第一晶片表面上的頂部金屬接觸區通過互聯板連接電路基底。
  15. 如申請專利範圍第1項所述的半導體封裝，其特徵在於，還包括一個模塑膠覆蓋至少電路基底的一個部分，多種半導體晶片和立體匹配電連接。
  16. 一種有效連接多個、獨立和三維互聯板的方法，每個都是設定好尺寸設置在具有一對連接半導體頂部的匹配電路基底上，該方法包括：a)製作一個多板載體框，具有多個互聯板完整的支撐和多個臨時支撐成分；b)通過破壞臨時支撐成分將獨立的互聯板從多個載體框中分離出來；c)將每個互聯板設置在設配電路基底上；其特徵在於，每個互聯板進一步包括一個從半導體晶片頂部到中間接觸區的互聯板，其中的中間接觸區包括從其他半導體晶片底部延伸出來的L形電路路徑。
  17. 如申請專利範圍第16項所述的方法，其特徵在於，製作多板載體邊框還包括用至少一個集成臨時支撐成分連接至少一對相互連接的互聯板。
  18. 如申請專利範圍第16項所述的方法，其特徵在於，在連接每個互聯板中還包括同時連接所有互聯板。
  19. 如申請專利範圍第16項所述的方法，其特徵在於，分開多個引線邊框包括使每個連接在一起的電路基底獨立；進一步包括，步驟c)，d)之後分開每個電路基底的獨立的互聯板。
  20. 如申請專利範圍第16項所述的方法，其特徵在於，分開多板載體框還包括分開每個電路基底上的相互獨立的互聯板。
  21. 如申請專利範圍第16項所述的方法，其特徵在於，製作多板載體邊框進一步包括用一個樣板刀三維製作互聯板。
  22. 如申請專利範圍第16項所述的方法，其特徵在於，分開多板載體邊框還包括用沖孔工具將其分開。
  23. 如申請專利範圍第16項所述的方法，其特徵在於，還包括：e)封裝至少電路基底的一部分，多個半導體晶片和互聯板。
TW098126649A 2008-08-07 2009-08-06 具有立體匹配互聯板的緊密封裝半導體晶片 TWI406372B (zh)

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