CN1357919A - 功率型半导体芯片的封装装置及封装方法 - Google Patents
功率型半导体芯片的封装装置及封装方法 Download PDFInfo
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Abstract
一种功率型半导体芯片的封装装置及封装方法;本装置包括:一芯片,其二表面分别含有芯片的第一、二电极及第三电极;第一导电框架上的二部分分别与二电极电连接,自二电极向芯片外延伸;一与第三电极电连接的第二导电框架,并向芯片外延伸。本方法包括:将第一导电框架的二部分分别电连接至芯片的二电极,将第一导电框架自二电极向芯片外延伸;将第二导电框架电连接至芯片的第三电极,并向芯片外延伸。本装置散热性好,生产效率高。
Description
本发明涉及一种半导体芯片的封装技术,特别是一种功率型半导体芯片的封装装置及封装方法,其为一种金属氧化物半导体场效应晶体管(POWERMOSFET)集成电路的封装方法,其可以有效利用芯片的面积,且具有良好的散热性。用本发明所完成的芯片封装,可以相当接近芯片尺寸。
为符合目前计算机、通信及消费市场小型化以及可携性的需求,半导体芯片的尺寸日益缩小,而线路的设计也日趋复杂。因此,半导体芯片的封装技术也必须随发生变革,芯片封装不只需符合更小、更快、更便宜的要求,同时也必须有更好的散热能力以及稳定度等优点。传统的芯片封装技术中,最常用的三种方式分别为:引线焊接(wire bonding),带状自动焊接(tape automated bonding,TAB)以及叩焊(flip-chip)等方式。上述方式各有其优缺点,然而在有效运用芯片面积的情况下,已逐渐发展出按芯片尺寸封装(chip scalepackage,以下简称CSP)的封装方式。该方式的要点在于提供一种封装尺寸缩小至几乎是一个裸芯片尺寸大小的封装体,且其稳定度较叩焊芯片更好。典型的按芯片尺寸封装方式可以达到芯片面积的1.5倍左右。
现有的功率型元件的封装,以一个功率型金属氧化物半导体场效应晶体管的封装为例,如美国专利第5,767,567号案所公开的。请参照图1A、1B及1C,图1A为一个功率型金属氧化物半导体场效应晶体管的电路示意图。该元件为一个N通道增强模式(N-channel enhancement mode)的金属氧化物半导体场效应晶体管,其中,晶体管的第一电极10(即闸极,gate)电连接至接脚4,第二电极20(即源极,source)连接至接脚1-3,而第三电极30(即漏极,drain)则电连接至接脚5-8。参看图1B所示,其中,功率型芯片11呈长方形,芯片11具有一个闸极10与一个源极20,其位于芯片11的同一表面,而漏极30则位于与闸极10与源极20所在芯片11表面对侧的另一个表面。由于功率型元件必须容许极大的电流通过源极20与漏极30,因此,可以看出源极20与漏极30的面积已相当近于芯片11的尺寸。至于闸极10,作为一个控制电极本身并不会有大电流流过,所以由图1B可以看出闸极10只占芯片11表面积的一小部分。现有功率金氧半导体场效电晶体封装应用两片金属导电框架(leadframe,通常是铜导电框架)。顶部导电框架13(toplaedframe)通过导线12分别与源极20及闸极10互相连接,而分别形成接脚1-3、及接脚4。另外,底部导电框架14(bottom laedframe)是直接(未通过导线)与芯片底部表面的漏极30互相连接,而形成接脚5-8。
现有功率型金属氧化物半导体场效应晶体管的芯片封装的一个特征在于其连接源极20及闸极10的导线12焊接的方式,如图1B所示,其是使用引线焊接(wire bonding)的方法,将许多导线12焊接,以连接源极20及闸极10至顶部导电框架13。同样,源极20有大电流流过故需要许多导线12,以供连接用,而闸极10用一根导线连接则已足够。现参照图1C,由现有功率型金属氧化物半导体场效应晶体管的芯片封装外观示意图可看出,芯片11、各导电框架13、各接脚以及导线,特别值得注意的是用以连接闸极10与接脚4的一根导线12,至于连接源极20及接脚1-3的许多导线在图1C中则已被覆盖而未显示。
现有的功率型金属氧化物半导体场效应晶体管的芯片封装方法具有许多缺点。首先,由于是采用引线焊接方法,所以芯片面积的利用效率不高,无法缩小封装尺寸。此外,由于顶部导电框架13的面积不大,且其是利用引线焊接来与芯片相连接,故封装的散热性不佳,而此为功率芯片致命的缺点。最后,由于现有的封装方式需焊接许多根引线,其工艺程序相当繁复,生产效率很低,且该芯片的闸极只通过一根导线与接脚连接,稳固性亦差,因此,需要研究出一种既能具备CSP的概念、散热性良好且兼具制作效率及稳固性的功率型芯片的封装体及制造方法。
本发明的一目的在于提供一种可有效利用芯片面积的功率型半导体芯片的封装装置及封装方法。
本发明的另一目的在于提供一种散热性优良的功率型半导体芯片的封装装置及封装方法。
本发明的又一目的在于提供一种制造程序简化,且能提高封装的生产效率的功率型半导体芯片的封装装置及其制造方法。
本发明的再一目的在于提供一种容易延伸为多芯片模组的功率型半导体芯片的封装装置及封装方法。
为达到上述目的,本发明采取如下技术措施:
本发明的一种功率型半导体芯片的封装装置,其中,芯片具有一个第一表面,该表面含有芯片的第一电极与第二电极,一个第二表面,其含有芯片的第三电极。一个第一导电框架的第一部分电连接第一电极,第一导电框架的第二部分电连接至功率元件的第二电极,一个第三导电框架电连接功率元件的第三电极;其中,第一导电框架自第一电极与第二电极向芯片外延伸,第二导电框架自第三电极处向芯片外延伸。
由于本发明的功率型半导体芯片的封装装置及封装方法采用按芯片尺寸封装方式,所以芯片面积的利用效率极高。由于本发明的功率元件芯片封装,其第一导电框架的面积很大,故封装的散热性极佳。同时,本发明的功率元件芯片封装方法,其制造程序简化,生产效率极高,而且稳固性佳。
本发明的一种功率型芯片封装装置与方法,由于其中第一导电框架及第二导电框架可以向芯片外延伸,而至少三者中之一可进一步与其他芯片的电极电连接,可以容易形成多芯片模组的封装体。
本发明采取如下具体结构及方法:
本发明的功率型半导体芯片的封装装置,包括:
一个芯片11,其具有一个第一表面111及一个第二表面112;第一表面111含有芯片的第一电极10与第二电极20;第二表面112含有芯片的第三电极30;
一个第一导电框架15,其具有第一部分151及第二部分152;第一部分151与第一电极10电连接,自第一电极10处向芯片外延伸;第二部分152与第二电极20电连接,并自第二电极20处向芯片外延伸;
一个第二导电框架16,其与第三电极30电连接,并自第三电极30处向芯片外延伸。
本发明的功率型半导体芯片的封装方法,包括如下步骤:
将一个第一导电框架15的一第一部分151电连接至芯片的第一电极10,并将第一导电框架15的一个第二部分152电连接至芯片的第二电极20,并将第一导电框架15自芯片的第一电极10与第二电极20处向芯片外延伸;
将一个第二导电框架16电连接至芯片的第三电极30,且将第二导电框架16自芯片的第三电极30处向芯片外延伸。
结合附图及实施例对本发明的结构特征及方法特征详细说明如下:
附图简述:
图1A:一功率金氧半导体场效电晶体的元件电路示意图;
图1B:一种现有功率型金属氧化物半导体场效应晶体管的芯片接线组装顶视图;
图1C:现有功率型金属氧化物半导体场效应晶体管的芯片封装外观示意图;
图2A:本发明功率型半导体芯片的封装体实施例中芯片组装的侧视图;
图2B:本发明功率型半导体芯片的封装体实施例中芯片组装的顶视图;
图2C:本发明功率型半导体芯片的封装体实施例中芯片组装的底视图。
如图2A所示,其为本发明功率型半导体芯片的封装体实施例中芯片组装的侧视图,其中,芯片11具有一个第一表面111及一个第二表面112。第一表面111与第一导电框架15电连接,第二表面112与一个第二导电框架16电连接。导电框架与芯片11连接的方式,主要为焊接(利用焊锡)或是利用导电胶粘着等。此外,从图中可以看出,在本实施例中,第一导电框架15与第二导电框架16上各有数个导电接点153与163。导电接点153用以与芯片11的第一表面111直接接触,导电接点163用以与第二表面112直接接触。
如图2B所示,其为本发明功率型半导体芯片的封装体实施例中芯片组装的顶视图;其表示本发明主要特征之一的第一导电框架15,第一导电框架15含有一个第一部分151及一个第二部分152,第一部分151电连接芯片11的一个第一电极10(或闸极),第二部分152电连接芯片的一个第二电极20(或源极)。由前述可知,源极的面积远大于闸极的面积,所以,在芯片11上方的第一部分151的面积远小于在芯片11上方的第二部分152的面积。第一导电框架15的材料最好为铜,导电框架主要经由冲压或蚀刻的方式形成,第一导电框架15向芯片外延伸的部分用以形成接脚,其步骤为将该延伸部分经过二次折弯的方式(参见图2A),再将该延伸部分延着aa’线切割,则可以形成图1C中的四个接脚(1-4)。
如图2C所示,其为本发明功率型半导体芯片的封装体实施例中芯片组装的底视图,第二导电框架16电连接芯片11的一个第三电极30(或漏极),第三电极的面积近似于芯片的面积。如同第一导电框架15,第二导电框架16的材料可以为铜,而导电框架图案主要是经由冲压或蚀刻的方式形成,而第二导电框架16向芯片外延伸的部分则经过折弯及切割手续用以形成接脚。图2C中的实施例是形成四个接脚(5-8)。
本发明的另一个实施例(图未显示),若将图2A、2B、2C中的第一导电框架15的第一部分151、第二部分152或第二导电框架16,三者中的至少一个,向芯片外延伸而进一步与其他芯片的电极电连接,这样,则可以形成多芯片模组的封装体。
与现有技术相比,本发明具有如下效果:
比较本发明的图2B及现有技术的图1B的封装方式,可以清楚看出本发明的优点。由于本发明的芯片封装并不采用引线焊接,所以芯片面积的利用效率极高,可以趋近于按芯片尺寸封装(CSP)的方式。另一方面,由于本发明的功率型芯片的封装,其中,第一导电框架15的面积很大,因此,封装的散热性远较现有技术为佳。同时本发明并不需要焊接许多根引线,因此制造程序简化,便于自动化生产,且效率极高,而且稳回性亦较好。
本发明的功率型芯片的封装体,芯片面积的利用效率极高,且导电框架的面积很大,故封装体的散热性极佳。本发明的功率型芯片封装方法,其制造程序简单,便于自动化,可大大提高生产效率。另外,本发明的封装稳固性较好,同时富有弹性,可以扩充成为多芯片模组的封装。
上述内容是利用实施例说明本发明的技术特征,并非用于限制本发明的保护范围,即使有人在本发明构思的基础上稍作变动,仍应属于本发明的保护范围内。
Claims (22)
1、一种功率型半导体芯片的封装装置,包括:
一个芯片(11),其具有一个第一表面(111)及一个第二表面(112);第一表面(111)含有芯片的第一电极(10)与第二电极(20);第二表面(112)含有芯片的第三电极(30);
一个第一导电框架(15),其具有第一部分(151)及第二部分(152);第一部分(151)与第一电极(10)电连接,自第一电极(10)处向芯片外延伸;第二部分(152)与第二电极(20)电连接,并自第二电极(20)处向芯片外延伸;
一个第二导电框架(16),其与第三电极(30)电连接,并自第三电极(30)处向芯片外延伸。
2、根据权利要求1所述的封装装置,其特征在于,所述芯片为一个金属氧化物半导体场效应晶体管芯片。
3、根据权利要求2所述的封装装置,其特征在于,所述第一电极、第二电极与第三电极分别是场效应晶体管的闸极、源极与漏极。
4、根据权利要求1所述的封装装置,其特征在于,所述第一导电框架及第二导电框架为铜导电框架。
5、根据权利要求1所述的封装装置,其特征在于,所述第一导电框架的第一部分向所述芯片外延伸,进一步形成所述第一电极的接脚。
6、根据权利要求5所述的封装装置,其特征在于,所述第一电极的接脚为一个接脚。
7、根据权利要求1所述的封装装置,其特征在于,所述第一导电框架的第二部分向所述芯片外延伸,进一步形成所述第二电极的接脚。
8、根据权利要求7所述的封装装置,其特征在于,所述第二电极的接脚为三个接脚。
9、根据权利要求1所述的封装装置,其特征在于,所述第二导电框架向所述芯片外延伸,进一步形成所述第三电极的接脚。
10、根据权利要求9所述的封装装置,其特征在于,所述第三电极的接脚为四个接脚。
11、根据权利要求1所述的封装装置,其特征在于,所述第一导电框架的第一部分、第二部分以及第二导电框架向芯片外延伸,且至少三者中之一进一步与其他芯片的电极电连接,以形成多芯片模组封装装置。
12、根据权利要求1所述的封装装置,其特征在于,所述第一导电框架的第一部分上设有一个用以与所述第一电极电连接的导电接点。
13、根据权利要求1所述的封装装置,其特征在于,所述第一导电框架的第二部分上设有数个用以与所述第二电极电连接的导电接点(153)。
14、根据权利要求1所述的封装装置,其特征在于,所述第二导电框架上设有数个用以与所述第三电极电连接的导电接点(163)。
15、一种适用于权利要求1~14中任一项装置的功率型半导体芯片的封装方法,包括如下步骤:
将一个第一导电框架(15)的一第一部分(151)电连接至芯片的第一电极(10),并将第一导电框架(15)的一个第二部分(152)电连接至芯片的第二电极(20),并将第一导电框架(15)自芯片的第一电极(10)与第二电极(20)处向芯片外延伸;
将一个第二导电框架(16)电连接至芯片的第三电极(30),且将第二导电框架(16)自芯片的第三电极(30)处向芯片外延伸。
16、根据权利要求15所述的方法,其特征在于,还包括如下步骤:将第一导电框架的第二部分向芯片外延伸,形成第二电极的接脚。
17、根据权利要求15所述的方法,其特征在于,还包括如下步骤:将第一导电框架的第二部分向芯片外延伸,形成第二电极的接脚。
18、根据权利要求15所述的方法,其特征在于,还包括如下步骤:将第二导电框架向芯片外延伸,形成第三电极的接脚。
19、根据权利要求15所述的方法,其特征在于,还包括如下步骤:将第一导电框架的第一部分、第二部分及第二导电框架向芯片外延伸,且电连接至少三者中之一到其他芯片的电极,以形成多芯片模组。
20、根据权利要求15所述的方法,其特征在于,还包括如下步骤:在第一导电框架的第一部分上形成一个用以与第一电极电连接的导电接点。
21、根据权利要求15所述的制造方法,其特征在于,还包括如下步骤:在第一导电框架的第二部分上形成数个用以与第二电极电连接的导电接点(153)。
22、根据权利要求15所述的制造方法,其特征在于,还包括如下步骤:在第二导电框架上形成数个用以与第三电极电连接的导电接点(163)。
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CN100435328C (zh) * | 2005-12-12 | 2008-11-19 | 三菱电机株式会社 | 模塑封装件 |
CN100444400C (zh) * | 2004-01-10 | 2008-12-17 | HVVi半导体股份有限公司 | 功率半导体器件及其方法 |
CN101656250B (zh) * | 2008-08-07 | 2011-10-19 | 万国半导体股份有限公司 | 具有立体匹配互连板的紧密封装半导体芯片 |
CN102956509A (zh) * | 2011-08-31 | 2013-03-06 | 飞思卡尔半导体公司 | 功率器件和封装该功率器件的方法 |
CN107305850A (zh) * | 2016-04-20 | 2017-10-31 | 艾马克科技公司 | 制造封装的半导体装置的方法、形成封装的半导体装置的方法和封装的半导体装置 |
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CN100444400C (zh) * | 2004-01-10 | 2008-12-17 | HVVi半导体股份有限公司 | 功率半导体器件及其方法 |
CN100435328C (zh) * | 2005-12-12 | 2008-11-19 | 三菱电机株式会社 | 模塑封装件 |
CN101656250B (zh) * | 2008-08-07 | 2011-10-19 | 万国半导体股份有限公司 | 具有立体匹配互连板的紧密封装半导体芯片 |
CN102956509A (zh) * | 2011-08-31 | 2013-03-06 | 飞思卡尔半导体公司 | 功率器件和封装该功率器件的方法 |
CN107305850A (zh) * | 2016-04-20 | 2017-10-31 | 艾马克科技公司 | 制造封装的半导体装置的方法、形成封装的半导体装置的方法和封装的半导体装置 |
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