JP2016184757A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2016184757A JP2016184757A JP2016116626A JP2016116626A JP2016184757A JP 2016184757 A JP2016184757 A JP 2016184757A JP 2016116626 A JP2016116626 A JP 2016116626A JP 2016116626 A JP2016116626 A JP 2016116626A JP 2016184757 A JP2016184757 A JP 2016184757A
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- Prior art keywords
- conductor
- lead terminal
- electrode
- semiconductor
- semiconductor element
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 294
- 239000004020 conductor Substances 0.000 claims abstract description 163
- 125000006850 spacer group Chemical group 0.000 claims abstract description 45
- 229920005989 resin Polymers 0.000 claims abstract description 36
- 239000011347 resin Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims description 61
- 239000002184 metal Substances 0.000 claims description 61
- 238000007789 sealing Methods 0.000 claims description 22
- 238000000034 method Methods 0.000 description 22
- 238000010586 diagram Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
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Abstract
Description
金属板と、上記金属板に設置された1つの半導体素子と、上記半導体素子に電気的に接続された少なくとも3つのリード端子とを備える半導体装置であって、
上記半導体素子は、該半導体素子の第1面に少なくとも1つの電極を有するとともに、上記第1面の反対側にある第2面が上記金属板と対向するように、上記金属板に設置され、
上記リード端子は、上記半導体素子と重ならないように配置され、
上記半導体素子の第1面にある各電極は、上記リード端子のうち互いに異なるいずれか1つのリード端子と、導電体によってそれぞれ接続され、
上記導電体に接続されるリード端子の該導電体との接合部分は、該導電体を介して接続される電極と近接するように配置されており、
上記導電体によって接続される電極およびリード端子は、該電極の該導電体との接合部分と、該リード端子の該導電体との接合部分とが同じ高さに位置しており、
絶縁性のスペーサーと、少なくとも上記半導体素子を封止する封止樹脂とをさらに備え、
上記導電体に接続されるリード端子は、上記スペーサーを介して上記金属板に支えられており、
上記スペーサーは、上記リード端子の上記導電体との接合部分の下方に配置されており、
上記導電体に接続される上記リード端子は、上記金属板の上方に配置され、上記リード端子と上記金属板との間に上記スペーサーが配置されている第1部分と、該間に上記スペーサーが配置されていない第2部分とを有し、上記第2部分が、上記第1部分よりも上記金属板から離れるように、曲折されていることを特徴としている。
金属板と、上記金属板に設置された複数の半導体素子と、上記複数の半導体素子に電気的に接続された少なくとも3つのリード端子とを備える半導体装置であって、
上記複数の半導体素子のそれぞれは、該半導体素子の第1面に少なくとも1つの電極を有するとともに、上記第1面の反対側にある第2面が上記金属板と対向するように、上記金属板に設置され、
上記リード端子は、上記複数の半導体素子と重ならないように配置され、
上記複数の半導体素子の各第1面にある全ての電極のうち少なくとも1つの電極は、上記リード端子のうち互いに異なるいずれか1つのリード端子と、導電体によってそれぞれ接続され、
上記導電体に接続されるリード端子の該導電体との接合部分は、該導電体を介して接続される電極と近接するように配置されており、
上記導電体によって接続される電極およびリード端子は、該電極の該導電体との接合部分と、該リード端子の該導電体との接合部分とが同じ高さに位置しており、
絶縁性のスペーサーと、少なくとも上記半導体素子を封止する封止樹脂とをさらに備え、
上記導電体に接続されるリード端子は、上記スペーサーを介して上記金属板に支えられており、
上記スペーサーは、上記リード端子の上記導電体との接合部分の下方に配置されており、
上記導電体に接続される上記リード端子は、上記金属板の上方に配置され、上記リード端子と上記金属板との間に上記スペーサーが配置されている第1部分と、該間に上記スペーサーが配置されていない第2部分とを有し、上記第2部分が、上記第1部分よりも上記金属板から離れるように、曲折されていることを特徴としている。
本発明の一実施形態について図面に基づいて説明すれば、以下の通りである。
図1は、本実施の形態の半導体装置1の一構成例を示す図であり、図1の(a)は平面視を示し、図1の(b)は図1の(a)に示されるA−A’線断面視を示し、図1の(c)は(a)に示されるB−B’線断面視を示す。なお、図1の(a)は、モールド樹脂10を部分的に透過して図示している。
次に、ゲート端子7、ドレイン端子8およびソース端子9のパッケージ内の接続構造について詳細に説明する。なお、以下では、図1の(b)の上下方向および図1の(c)の左右方向を「平面方向」とし、図1の(b)の左右方向および図1の(c)の上下方向を「高さ方向」とする。
図2の(a)〜図2の(d)は、半導体装置1の変形例である半導体装置1a〜1dの概略構成を示す図である。
前記実施の形態1の半導体装置1は、1パッケージに1つの半導体チップ3を搭載したものであったが、これに限らず、1パッケージに複数の半導体チップを搭載してもよい。本実施の形態では、一例として、1パッケージに、電気的に接続された2つの半導体チップを搭載する形態について説明する。
以上のように、本発明に係る半導体装置は、
金属板と、上記金属板に設置された1つの半導体素子と、上記半導体素子に電気的に接続された少なくとも3つのリード端子とを備える半導体装置であって、
上記半導体素子は、該半導体素子の第1面に少なくとも1つの電極を有するとともに、上記第1面の反対側にある第2面が上記金属板と対向するように、上記金属板に設置され、
上記リード端子は、上記半導体素子と重ならないように配置され、
上記半導体素子の第1面にある各電極は、上記リード端子のうち互いに異なるいずれか1つのリード端子と、導電体によってそれぞれ接続され、
上記導電体に接続されるリード端子の該導電体との接合部分は、該導電体を介して接続される電極と近接するように配置されていることを特徴としている。
金属板と、上記金属板に設置された複数の半導体素子と、上記複数の半導体素子に電気的に接続された少なくとも3つのリード端子とを備える半導体装置であって、
上記複数の半導体素子のそれぞれは、該半導体素子の第1面に少なくとも1つの電極を有するとともに、上記第1面の反対側にある第2面が上記金属板と対向するように、上記金属板に設置され、
上記リード端子は、上記複数の半導体素子と重ならないように配置され、
上記複数の半導体素子の各第1面にある全ての電極のうち少なくとも1つの電極は、上記リード端子のうち互いに異なるいずれか1つのリード端子と、導電体によってそれぞれ接続され、
上記導電体に接続されるリード端子の該導電体との接合部分は、該導電体を介して接続される電極と近接するように配置されていることを特徴としている。
2 ヘッダ(金属板)
3,3a,3b 半導体チップ(半導体素子)
4,4a,4b ゲート電極(電極)
5,5a,5b ソース電極(電極)
7,31 ゲート端子(リード端子、第3リード端子)
8,32 ドレイン端子(リード端子、第1リード端子)
9,33 ソース端子(リード端子、第2リード端子)
10 モールド樹脂(封止樹脂)
11a,11b,11c,11d,11e,11f,11g 導電体
12 スペーサー
20 半導体装置
21 半導体チップ(半導体素子、第1半導体素子)
22,26 ゲート電極(電極)
23 ソース電極(電極)
24,27 ドレイン電極(電極)
25 半導体チップ(半導体素子、第2半導体素子)
Claims (14)
- 金属板と、上記金属板に設置された1つの半導体素子と、上記半導体素子に電気的に接続された少なくとも3つのリード端子とを備える半導体装置であって、
上記半導体素子は、該半導体素子の第1面に少なくとも1つの電極を有するとともに、上記第1面の反対側にある第2面が上記金属板と対向するように、上記金属板に設置され、
上記リード端子は、上記半導体素子と重ならないように配置され、
上記半導体素子の第1面にある各電極は、上記リード端子のうち互いに異なるいずれか1つのリード端子と、導電体によってそれぞれ接続され、
上記導電体に接続されるリード端子の該導電体との接合部分は、該導電体を介して接続される電極と近接するように配置されており、
上記導電体によって接続される電極およびリード端子は、該電極の該導電体との接合部分と、該リード端子の該導電体との接合部分とが同じ高さに位置しており、
絶縁性のスペーサーと、少なくとも上記半導体素子を封止する封止樹脂とをさらに備え、
上記導電体に接続されるリード端子は、上記スペーサーを介して上記金属板に支えられており、
上記スペーサーは、上記リード端子の上記導電体との接合部分の下方に配置されており、
上記導電体に接続される上記リード端子は、
上記金属板の上方に配置され、
上記リード端子と上記金属板との間に上記スペーサーが配置されている第1部分と、該間に上記スペーサーが配置されていない第2部分とを有し、
上記第2部分が、上記第1部分よりも上記金属板から離れるように、曲折されていることを特徴とする半導体装置。 - 上記導電体は、直線状の形状を有していることを特徴とする請求項1に記載の半導体装置。
- 上記導電体によって接続される電極およびリード端子の両者の配置距離は、上記リード端子が上記半導体素子と干渉しないように定められた最小距離であることを特徴とする請求項1または2に記載の半導体装置。
- 上記半導体素子は、上記第2面に少なくとも1つの電極をさらに有していることを特徴とする請求項1から3の何れか1項に記載の半導体装置。
- 上記導電体に接続されるリード端子は、外部と接続可能な端子として機能することを特徴とする請求項1から4のいずれか1項に記載の半導体装置。
- 上記導電体に接続されるリード端子は、該導電体との接合部分を含む一部分が上記封止樹脂内に配置され、該一部分以外の部分が上記封止樹脂外に配置されていることを特徴とする請求項1から5のいずれか1項に記載の半導体装置。
- 上記半導体素子には、ドレイン電極、ソース電極およびゲート電極を有するパワートランジスタが形成されており、
上記リード端子として、上記ドレイン電極に電気的に接続される第1リード端子と、上記ソース電極に電気的に接続される第2リード端子と、上記ゲート電極に電気的に接続される第3リード端子とを備えていることを特徴とする請求項1から6のいずれか1項に記載の半導体装置。 - 金属板と、上記金属板に設置された複数の半導体素子と、上記複数の半導体素子に電気的に接続された少なくとも3つのリード端子とを備える半導体装置であって、
上記複数の半導体素子のそれぞれは、該半導体素子の第1面に少なくとも1つの電極を有するとともに、上記第1面の反対側にある第2面が上記金属板と対向するように、上記金属板に設置され、
上記リード端子は、上記複数の半導体素子と重ならないように配置され、
上記複数の半導体素子の各第1面にある全ての電極のうち少なくとも1つの電極は、上記リード端子のうち互いに異なるいずれか1つのリード端子と、導電体によってそれぞれ接続され、
上記導電体に接続されるリード端子の該導電体との接合部分は、該導電体を介して接続される電極と近接するように配置されており、
上記導電体によって接続される電極およびリード端子は、該電極の該導電体との接合部分と、該リード端子の該導電体との接合部分とが同じ高さに位置しており、
絶縁性のスペーサーと、少なくとも上記半導体素子を封止する封止樹脂とをさらに備え、
上記導電体に接続されるリード端子は、上記スペーサーを介して上記金属板に支えられており、
上記スペーサーは、上記リード端子の上記導電体との接合部分の下方に配置されており、
上記導電体に接続される上記リード端子は、
上記金属板の上方に配置され、
上記リード端子と上記金属板との間に上記スペーサーが配置されている第1部分と、該間に上記スペーサーが配置されていない第2部分とを有し、
上記第2部分が、上記第1部分よりも上記金属板から離れるように、曲折されていることを特徴とする半導体装置。 - 上記導電体は、直線状の形状を有していることを特徴とする請求項8に記載の半導体装置。
- 上記導電体によって接続される電極およびリード端子の両者の配置距離は、上記リード端子が上記半導体素子と干渉しないように定められた最小距離であることを特徴とする請求項8または9に記載の半導体装置。
- 上記複数の半導体素子のうち少なくとも1つの半導体素子は、上記第2面に少なくとも1つの電極をさらに有していることを特徴とする請求項8から10の何れか1項に記載の半導体装置。
- 上記導電体に接続されるリード端子は、外部と接続可能な端子として機能することを特徴とする請求項8から11のいずれか1項に記載の半導体装置。
- 上記導電体に接続されるリード端子は、該導電体との接合部分を含む一部分が上記封止樹脂内に配置され、該一部分以外の部分が上記封止樹脂外に配置されていることを特徴とする請求項8から12のいずれか1項に記載の半導体装置。
- 上記複数の半導体素子として、第1半導体素子および第2半導体素子を備え、
上記リード端子として、第1リード端子、第2リード端子および第3リード端子を備え、
上記第1半導体素子および上記第2半導体素子にはそれぞれ、ドレイン電極、ソース電極およびゲート電極を有するNチャネル型のパワートランジスタが形成されており、
上記第1半導体素子のドレイン電極は、上記第1リード端子に電気的に接続され、
上記第1半導体素子のソース電極は、上記第2半導体素子のドレイン電極に電気的に接続され、
上記第1半導体素子のゲート電極は、上記第2半導体素子のソース電極に電気的に接続され、
上記第2半導体素子のソース電極は、上記第2リード端子に電気的に接続され、
上記第2半導体素子のゲート電極は、上記第3リード端子に電気的に接続されていることを特徴とする請求項8から13のいずれか1項に記載の半導体装置。
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