CN1630945A - 半导体器件封装件及具有悬伸出引线框接合区的管芯的引线框 - Google Patents

半导体器件封装件及具有悬伸出引线框接合区的管芯的引线框 Download PDF

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CN1630945A
CN1630945A CN01820533.XA CN01820533A CN1630945A CN 1630945 A CN1630945 A CN 1630945A CN 01820533 A CN01820533 A CN 01820533A CN 1630945 A CN1630945 A CN 1630945A
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T·萨蒙
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Infineon science and technology Americas
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13034—Silicon Controlled Rectifier [SCR]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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Abstract

半导体管芯被用焊料或环氧树脂接合到引线框接合区(20)上，并悬伸出所述接合区，从而减小从引线框接合区(21，22)施加到管芯的热差膨胀和收缩应力。标准尺寸的塑料外套在尺寸上没有改变，但容纳了更大的总共硅管芯面积。

Description

半导体器件封装件及具有悬伸出引线框接合区的管芯的引线框
相关申请
本发明要求2000年12月14日申请的美国临时专利申请No.60/255,470的利益。
技术领域
本发明涉及半导体器件封装件，更具体说涉及半导体管芯上的机械应力减小的新型封装件。
背景技术
半导体器件是已知的，其中薄且脆的硅管芯被通过焊料或通过使用导电或不导电的粘接剂(例如环氧树脂)固定到引线框上。引线框通常是导电的金属例如薄且平的镀铜合金条，引线框的所述条内具有大量相同的压制图形。所述图形提供扩大的接合区区，各管芯可以固定在这些接合区区上，所述图形还提供多个一体的终端部分或引线，或称为“引脚”，它们然后与所述接合区隔绝开，接合区接收从引线到管芯顶表面上的电极的丝焊。在丝焊之后，单个引线框器件部分上面被模制一适当的塑料外套。单个封装件接着被分开，各端头与从端头部分延伸出的引线或引脚彼此隔绝开，接合区连接体延伸通过所述外套壁以允许电连接至容纳在所述封装件内的管芯。
过去，接收硅管芯的接合区一直是比管芯的面积大，因此管芯的整个底部表面刚性连接到接合区表面。由于硅管芯与金属或其它接合区基体具有不同的热膨胀系数，因此在焊接或其它产生热的连接过程中以及在实验或工作中的热循环期间，会在所述管芯的整个表面区域上引起机械应力。这些应力可以造成对管芯的损害或使管芯损坏。
发明内容
根据本发明，硅管芯的尺寸被确定为使得该管芯在至少一个尺寸上(最好是在所有尺寸上)大于管芯接收接合区。因而，管芯的面积的一小部分被刚性连接到接合区，从而施加到管芯上的总应力降低。
在一个优选实施例中，至少两个小面积的管芯采用了两个各自面积更小的接合区，从而管芯悬伸出来。这样，两个管芯具有的总面积将与以前使用的一个管芯的面积相同。因此，两个(或更多)管芯上的应力被大大减小。
在本发明的一个优选实施例中，两个悬伸的MOSFET管芯可以用于6引线TSOT型封装件。如果需要，管芯可以相互连接(以并联或串联布置)。其它器件管芯组合，例如MOSFET管芯和肖特基二极管管芯，也可以设置在一个共同的封装件中，两个都从其各自的引线框接合区悬伸出。
本发明的一个显著优点是，其允许在标准外形的塑料封装内容纳明显增大的管芯面积，而不增加外形尺寸。
附图说明
图1示出了可以用于本发明的引线框的一小部分。
图2示出了具有叠加在各自的引线框接合区上的两个就位的管芯的图1所示引线框。
图3是已在上面模制有塑料外套并由引线框加工出封装件之后的单个6引脚封装件的顶视示意图。
图4是图3的封装件的侧视图。
具体实施方式
参见图1，示出了一个大的传统引线框20的一小部分，该引线框被压制而成，用来提供多个相同的图形，其中一个图形如图1所示。该图形包括两个管芯接收接合区21和22，它们各具有一体的延伸引脚23和24。引线框还包括栅极引线引脚25和26(用于各金属氧化物场效应晶体管(MOSFET)的栅极)和源极引脚27和28(用于处在接合区21和22上的各MOSFET的源极)。
应知道，尽管对一个封装件只示出两个接合区，但是可以采用任何所需数目的接合区，实际上，一个管芯可以拥有一个以上的接合区。而且，可以采用除了MOSFET管芯之外的管芯，并对引线框的引脚输出进行适当改变。
如图2所示，两个半导体管芯30和31分别被固定到接合区21和22上。管芯30和31是具有常规的底部漏极以及位于上表面上的源极和栅极的垂直导通MOSFET。电极图形是公知的，因而没有示出。还可以采用任何其它半导体管芯，包括二极管、IGBT、可控硅整流器和双极晶体管。
根据本发明，管芯30和31的面积分别大于接合区21和22，并从接合区21和22的四周悬伸出。在本发明的一个例子中，管芯30和31每个可具有0.99mm乘1.092mm的尺寸，同时接合区21和22每个可具有0.79mm乘0.89mm的尺寸。虽然示出的两个管芯具有相等的尺寸，并且示出的两个接合区具有相等的尺寸，但应知道，接合区21和22彼此可以具有不同的尺寸，管芯30和31也同样可以具有不同的尺寸。
管芯30和31的底部漏极通常分别刚性连接到接合区21和22的相对区域，连接例如可以通过焊接或通过粘接剂接合。
显然，管芯30和31从其各自的接合区21和22悬伸出，减小了接触面积，从而减小了硅管芯和引线框材料之间不同的热膨胀和收缩过程中传递到管芯30和31上的应力大小。
在管芯30和31被固定到接合区21和22上之后，管芯的顶部电极通常用丝焊到引脚25和28，并且管芯31的顶部电极用丝焊到引脚26和27。
应注意，此时外套50内可以具有更大的管芯面积，而不增加其尺寸。
然后通常所述引线框被在上面模制一塑料外套50，如图3(以虚线)和图4所示。然后对引线框进行加工，除去所得封装件一侧上的端头或引脚23、25和27之间的桥接部分，以及另一侧上的24、26和28之间的桥接部分。
引线23至28都延伸通过封装件的侧面，确定了一6引脚TSOT型器件，并分别对应于MOSFET30和31的引线D1、D2、G2、G1、S2和S1，如图3和4所示。所有具有下标“1”的引脚是用于MOSFET30的引脚，而具有下标“2”的引脚是用于MOSFET31的引脚。应注意，不同的引脚可以根据需要外部连接，或者内部连接以形成两个管芯之间的各种连接。
虽然已结合具体实施例对本发明进行了说明，但本领域技术人员显然还知道还有很多其它的改变和改进。因而，本发明不是通过这里具体公开的内容限定的，而是通过所附权利要求书限定的。

Claims (17)

1.一种半导体器件，包括一薄且平的半导体管芯和一薄且平的导电元件，该导电元件是用于支承所述半导体管芯的基本支承件；所述管芯设于所述导电元件的顶部表面上并与之表面接合；所述管芯具有至少一个比所述支承件的相应尺寸大的尺寸，从而所述管芯至少在所述尺寸上部分地悬伸出所述支承件。
2.如权利要求1所述的器件，其中所述管芯悬伸出所述支承件的全部顶部表面区域。
3.如权利要求1所述的器件，其中所述管芯通过焊料接合到所述支承件。
4.如权利要求1所述的器件，其中所述管芯通过环氧树脂粘接剂接合到所述支承件。
5.如权利要求1所述的器件，其中所述支承件是引线框的一部分。
6.如权利要求1所述的器件，其中所述器件被容纳在一塑料封装中。
7.如权利要求5所述的器件，其中所述管芯悬伸出所述支承件的全部顶部表面区域。
8.如权利要求6所述的器件，其中所述器件悬伸出所述支承件的全部顶部表面区域。
9.如权利要求8所述的器件，其中所述支承件是引线框的一部分。
10.如权利要求9所述的器件，其中所述支承件包括一引线框接合区；所述引线框接合区包括在一体的横向延伸部分内，该横向延伸部分延伸通过所述封装件的壁从而可接近，以用于实现与所述封装件外部的连接。
11.一种半导体器件封装件，包括：一平的导电引线框，该导电引线框具有至少一个引线框接合区；至少一个薄且平的半导体器件，其支承在所述引线框接合区上并紧密连接到所述引线框接合区；和一塑料外套，其包封着所述引线框接合区和所述管芯；所述管芯在至少一个尺寸上悬伸出所述引线框接合区，从而由于所述接合区和管芯之间不同的膨胀和收缩而产生的应力被减小。
12.如权利要求11所述的封装件，其中所述管芯在全部尺寸上悬伸出所述接合区。
13.如权利要求11所述的封装件，其中所述管芯是金属氧化物半导体场效应晶体管。
14.如权利要求11所述的封装件，其中所述引线框接合区具有一横向延伸的一体引脚，该引脚延伸通过所述外套的壁。
15.如权利要求11所述的封装件，它还包括一位于所述塑料外套内的第二引线框接合区和一固定到接合区上的第二管芯，并且所述第二管芯的至少一部分悬伸出所述第二引线框接合区。
16.如权利要求15所述的封装件，其中所述第一和第二管芯在所有尺寸上分别悬伸出所述第一和第二接合区。
17.如权利要求16所述的封装件，其中所述第一和第二管芯都是金属氧化物场效应晶体管。
CNB01820533XA 2000-12-14 2001-12-06 一种半导体器件以及一种半导体器件封装件 Expired - Fee Related CN100423251C (zh)

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US10/002,252 US6433424B1 (en) 2000-12-14 2001-10-26 Semiconductor device package and lead frame with die overhanging lead frame pad
PCT/US2001/046676 WO2002049108A1 (en) 2000-12-14 2001-12-06 Semiconductor device package and lead frame with die overhanging lead frame pad

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CN104157620A (zh) * 2014-08-22 2014-11-19 苏州日月新半导体有限公司 扁平无引脚封装体
CN110071078A (zh) * 2014-08-22 2019-07-30 苏州日月新半导体有限公司 扁平无引脚封装体

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CN100423251C (zh) 2008-10-01
US20020047198A1 (en) 2002-04-25
WO2002049108A8 (en) 2002-11-28
WO2002049108A1 (en) 2002-06-20
US6433424B1 (en) 2002-08-13
TW523888B (en) 2003-03-11

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