CN101794758B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101794758B
CN101794758B CN2010100020878A CN201010002087A CN101794758B CN 101794758 B CN101794758 B CN 101794758B CN 2010100020878 A CN2010100020878 A CN 2010100020878A CN 201010002087 A CN201010002087 A CN 201010002087A CN 101794758 B CN101794758 B CN 101794758B
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mentioned
semiconductor device
lead
projection
closing line
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CN101794758A (zh
Inventor
河野贤哉
芦田喜章
武藤邦治
清水一男
井上富文
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本发明提供一种半导体器件。通过销钉加工在源极引线(14)上设置突起(7)，以在突起(7)上连接接合线(4)时防止超声波衰减为目的，在源极引线(14)的背面的凹部(20)设置支柱(16)，从而防止接合线(4)与源极引线(14)的连接强度不够。另外，围绕源极引线(14)和接合线(4)的连接部而在突起(7)上设置连续的台阶(17)，防止由树脂(6)和源极引线(14)的分离引起的接合线(4)的断线。根据本发明，能够使用可简单加工且廉价制造的装置来实现防止由树脂(6)和引线框的界面分离引起的接合线(4)的断线、以及连接强度的提高。

Description

半导体器件
技术领域
本发明涉及半导体器件，尤其涉及有效应用于对功率MOSFET(Metal Oxide Semiconductor Field Effect Transistor：金属氧化物半导体场效应晶体管)、IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极晶体管)、双极型功率晶体管元件进行了树脂密封的半导体器件的技术。 
背景技术
作为用于便携电话、摄像机等的充电器、办公自动化(OA)设备等的电源电路以及汽车电装设备等的电源用晶体管，已知有低压驱动用功率晶体管。 
近年来，这种功率半导体器件存在进一步高输出化的倾向，为了确保半导体芯片的散热性，提出了使装载有半导体芯片的压料垫(Die Pad)(框)露出一部分的半导体器件(例如，专利文献1)。 
该半导体器件被形成为图1所示那样的形状。图1是表示现有的一般半导体器件9的内部结构的侧视图，半导体器件9是通过回焊工序被安装在衬底8的上表面的状态，树脂6用双点划线示出了外形。在图1中，在引线框1上装载有半导体芯片2，并设置有突起7a。半导体芯片2的端子(未图示)通过一方的接合线(bonding wire)4与突起7a连接，通过另一方的接合线3与引线端子(lead terminal)5相连接。将它们用树脂6密封并使装载了半导体芯片2的引线框1的背面的一部分露出来，从而构成半导体器件9。 
在该半导体器件9中，通过设置突起7a，防止由于回焊工序中的热负荷导致由树脂6和引线框1的热膨胀系数差引起的界面的分离，防止了由该分离所引起的接合线4的断线和分离。 
专利文献1：日本特开平7-193173号 
发明内容
上述专利文献1的半导体器件9中的突起7a实际上很难形成在引线框1上。例如，考虑通过切削加工在引线框1上形成突起7a，或者将突起7a作为单独部件通过例如焊锡等连接在引线框1上，但在引线框1的制造成本和批量生产方面是不利的。 
另外，还考虑到例如从引线框的背面通过销钉加工(半冲压)形成突起并进行引线接合(wire bonding)，但仅通过销钉加工形成突起，突起的背面的凹部会出现空隙，所以在焊线接合线连接时超声波能量衰减，有可能得不到足够的焊线接合线和引线框的连接强度。 
因此，担心由于回焊工序的热负荷导致由树脂和引线框的热膨胀系数差引起的界面分离，由此对接合线和引线框的连接部施加过度的应力，有可能引起接合线的断线和分离。 
本发明的目的在于，以简单加工提供一种廉价、可靠性高的半导体器件，该半导体器件具有在引线框上连接了接合线的结构，其能够提高接合线和引线框的连接强度，而且能够将由树脂和引线框的界面分离引起的接合线的断线和分离防于未然。 
本发明的上述以及其他目的和新特征通过本说明书的叙述和附图得以明确。 
简单说明本申请公开的发明中的代表性的技术方案的概要，如下。 
本发明的半导体器件包括：引线框，具有压料垫部和配置在上述压料垫部的附近的第一引线；装载在上述压料垫部上的半导体芯片；接合线，将形成在上述半导体芯片的表面的电极和上述第一引线电连接；以及树脂，对上述半导体芯片、上述引线框、上述第一引线以及上述接合线进行密封， 
上述半导体器件的特征在于， 
在上述第一引线和上述接合线的连接面上，在上述第一引线的上表面设置有成为上述接合线的接合部的突起，在上述突起的背面的一部分上形成有凹部， 
上述第一引线的上述凹部内且位于上述接合部的正下方，通过销钉加工形成有由上述第一引线的一部分构成的支柱，上述支柱被形成为从上述突起的背面开始直至与上述第一引线的背面相同的高度， 
在上述第一引线的上述凹部内且位于上述接合部的正下方，通过销钉加工形成有由上述第一引线的一部分构成的支柱，上述支柱被形成为从上述突起的背面开始直至与上述第一引线的背面相同的高度。 
简单说明由本申请公开的发明中的代表性的一个实施方式所得到的效果，如下所述。 
通过在引线框上形成的突起的背面凹部设置支柱，能够防止接合线连接时的超声波的衰减，能够坚固地连接接合线和引线框。 
另外，通过在引线框和接合线连接部周边设置连续的突起，能够将由回焊工序的热负荷导致树脂和引线框的界面分离以及由此引起的接合线的断线防于未然。 
进而，接合部的突起通过冲压引线框而形成，所以能够以简单的加工且低廉地形成。 
附图说明
图1是表示现有的半导体器件的内部结构的侧视图。 
图2是沿着图3的A-A线的剖视图。 
图3是表示本发明实施方式1的半导体器件的内部结构的俯视图。 
图4是表示从本发明实施方式1的半导体器件的上表面观察的俯视图。 
图5是表示从本发明实施方式1的半导体器件的下表面观察的俯视图。 
图6是表示本发明半导体器件中组装的半导体芯片的外观的侧视图。 
图7是沿着图8的B-B线的剖视图。 
图8是表示本发明实施方式2的半导体器件内部结构的俯视图。 
图9是表示从本发明实施方式2的半导体器件的上表面观察的俯视图。 
图10是表示从本发明实施方式2的半导体器件的下表面观察的俯视图。 
图11是沿着图12的C-C线的剖视图。 
图12是表示本发明实施方式3的半导体器件内部结构的俯视图。 
图13是表示从本发明实施方式3的半导体器件的上表面观察的俯视图。 
图14是表示从本发明实施方式3的半导体器件的下表面观察的俯视图。 
图15是沿着图15的E-E线的剖视图。 
图16是表示本发明实施方式4的半导体器件内部结构的俯视图。 
图17是表示从本发明实施方式4的半导体器件的上表面观察的俯视图。 
图18是表示从本发明实施方式4的半导体器件的下表面观察的俯视图。 
图19是表示本发明实施方式4的半导体器件的制造方法的剖视图。 
标号说明
1引线框 
2半导体芯片 
3接合线 
4接合线 
5引线端子 
6树脂 
7突起 
7a突起 
8衬底 
9半导体器件 
11漏电极 
12源电极 
13栅电极 
14源极引线 
15栅极引线 
16支柱 
17台阶(高低差) 
18周边突起 
19压料垫 
20凹部 
21突起 
22台 
23毛细管(capillary) 
D漏电极 
S源电极 
G栅电极 
具体实施方式
在以下的实施方式中，为方便起见，必要时分为多个部分或实施方式来说明，但除特别指出的情况外，它们不是互不相关的，而是存在一方是另一方的一部分或全部的变形例、具体情况、补充说明等的关系。 
另外，在以下的实施方式中，提及要素的数等(包括个数、数值、数量、范围等)时，除特别指出的情况和原理上明确限定为特定数的情况等以外，并不限于该特定的数，既可以是特定的数以上， 还可以是特定的数以下。 
而且，在以下的实施方式中，其构成要素(也包括要素步骤等)除特别指出的情况和被认为原理上明显是必须的情况等以外，未必是必须的。此外，在实施方式等中，关于构成要素等，提到“由A构成”时，除特别指出了仅限于该要素的情况等之外，当然并不排除其以外的要素。 
同样，在以下的实施方式中，在提及构成要素等的形状、位置关系等时，除特别指出了的情况和被认为原理上明显不是这样的情况等之外，实质上也包括与其形状等近似或类似的情况等。该情况对上述数值和范围也同样适用。 
另外，在提及材料等时，除特别明确记载了不是这样的情况或者原理上或状况上不是这样的情况以外，特定的材料是主要材料，并不排除次要的要素、添加物、添加要素等。例如，硅部件在除特别指出了的情况等之外，并不只是单纯的硅，还包括添加杂质、将硅作为主要要素的2元、3元等的合金(例如SiGe)等。 
另外，在用于说明以下实施方式的全部附图中，原则上对具有同一功能的部件标记同一标号并省略对其进行重复说明。 
另外，在以下的实施方式所使用的附图中，即使是俯视图，也有为了便于观察图面而局部性地添加阴影的情况。 
(实施方式1) 
本实施方式应用于功率MOSFET封装的制造，使用图2～图6进行说明。 
图2是沿着图3的A-A线的剖视图，示出了本实施方式的半导体器件9的内部结构。图3是表示图2的半导体器件9的内部结构的俯视图，用双点划线示出了树脂6的外形。另外，图4和图5是本实施方式的半导体器件9的外观形状。图4是半导体器件9的上表面俯视图，图5是半导体器件9的下表面俯视图。 
本实施方式是将本发明应用于纵型功率晶体管的例子。即，组装有具备漏电极D、源电极S、栅电极G的场效应晶体管的半导体 芯片2被组装在半导体器件9中。 
半导体芯片2形成例如纵型功率MOSFET，如图6所示，在下表面(背面)具有漏电极11，在上表面(主面)具有源电极12和栅电极13。半导体芯片2如图2所示，被装载在兼作漏极引线的压料垫19上。 
此时，压料垫19上连接半导体芯片2的漏电极11的接合材料(未图示)能够使用例如焊锡或导电性接合材料。 
源电极12和栅电极13通过接合线4和3分别与源极引线14和栅极引线15连接。此时，流过较大电流的源极侧的接合线4使用例如Al线。但是，接合线4可以根据流过半导体器件9的电流值来改变材料和截面面积，还可以代替Al线而使用例如Au线、Cu线或者Al带。 
另一方面，流过较少电流的栅极侧的接合线3使用例如Au线。当然，也可以代替Au线而使用Al线、Cu线或者Al带。 
将这些用树脂6密封，使装载有半导体芯片2的压料垫19、源极引线14以及栅极引线15的一部分露出，从而构成半导体器件9。 
此时，在流过较大电流的源极引线14上设置突起7。该突起7通过例如销钉加工而形成，利用例如压力机从源极引线14的背面通过半冲压形成。 
通过设置该突起7，利用锚定(锁定)效果来提高树脂6与源极引线14的粘着性，防止由于将半导体器件9安装在衬底时的回焊工序中的热负荷导致树脂6和源极引线14发生分离。 
在此，在形成突起7的工序中，在突起7的背面的凹部20形成支柱16。该支柱16用于防止本发明要解决的问题即连接接合线4和源极引线14时的超声波衰减。也就是说，当通过销钉加工在源极引线14上设置突起7时，在突起7的背面形成凹部20，但在凹部20没有支柱16的情况下，例如用超声波将接合线4连接在源极引线14上时，由于凹部20没有支撑，所以存在突起7发生振动、超声波能量发生衰减导致接合线4与源极引线14的连接强度降低的问题。 于是，通过在突起7的背面的凹部20形成支柱16，能够抑制超声波能量的衰减，能够坚固地连接接合线4和源极引线14。 
由此，能够提供如下这样的可靠性高的半导体器件9，即：大幅度提高接合线4和源极引线14的连接强度，将由于在衬底上安装半导体器件9时的回焊工序中的热负荷而使得由树脂6与源极引线14的热膨胀系数差引起的界面分离从而导致接合线4的断线和分离防于未然，不会使接合线4和源极引线14的连接强度降低。另外，本实施方式的突起7和支柱16能够利用压力机容易地形成，所以能够用低廉的原材料费和加工费形成。 
另外，突起7和支柱16可以与同源极引线14连接的接合线4的条数相应地设置多个，还可以分别独立地设置。而且，还可以在一个突起7和支柱16上连接多条接合线4。 
进而，突起7和支柱16还可以形成在栅极引线15上，在该情况下，也能够提高接合线3和栅极引线15的连接强度。 
(实施方式2) 
本实施方式应用于功率MOSFET的封装的制造，使用图7～图10进行说明。 
图7是沿着图8的B-B线的剖视图，示出了本实施方式的半导体器件9的内部结构。图8是表示图7的半导体器件9的内部结构的俯视图，用双点划线示出了树脂6的外形。另外，图9和图10是本实施方式的半导体器件9的外观形状。图9是半导体器件9的上表面俯视图，图10是半导体器件9的下表面俯视图。 
如图7所示，本实施方式的半导体器件9是在实施方式1的半导体器件9中，在突起7的接合部周边围绕接合部连续地设置台阶17。 
在本实施方式的半导体器件9中，在源极引线14的与接合线4的连接部即突起7的周边连续地形成有台阶17。该突起7和台阶17通过例如销钉加工而形成，利用例如压力机从源极引线14的背面通过半冲压而形成。 
该台阶17用于防止本发明要解决的问题即树脂6和源极引线14的界面分离。也就是说，通过围绕与源极引线14上的突起7连接的接合线4的周边而连续地设置台阶17，能够利用锚定(锁定)效果来更大幅度地提高树脂6和源极引线14的粘着性，能够防止树脂6和源极引线14的界面分离。特别是，台阶17是围绕接合线4和源极引线14的连接部即接合部的周边而连续地设置，所以能够应对从所有的方向施加的机械应力而保护接合部。即，能够将由于在衬底上安装半导体器件9时的回焊工序中的热负荷而使得由树脂6和源极引线14的热膨胀系数差引起的界面分离从而导致接合线4的断线和分离防于未然。 
而且，与实施方式1同样，在突起7的背面的凹部20形成有支柱16，所以在将接合线4连接在源极引线14时，能够防止超声波的能量衰减。另外，本实施方式的突起7、支柱16以及台阶17能够利用压力机容易地形成，所以能够以低廉的原材料费和加工费来形成。 
由此，能够大幅度提高接合线4和源极引线14的连接可靠性、提供可靠性高的半导体器件9。 
(实施方式3) 
本实施方式应用于功率MOSFET的封装的制造，使用图11～图14进行说明。 
图11是沿着图12的C-C线的剖视图，示出了本实施方式的半导体器件9的内部结构。图12是表示图11的半导体器件9的内部结构的俯视图，用双点划线示出了树脂6的外形。另外，图13和图14是本实施方式的半导体器件9的外观形状。图13是半导体器件9的上表面俯视图，图14是半导体器件9的下表面俯视图。 
本实施方式的半导体器件9是在实施方式1的半导体器件9中，代替突起7和支柱16而在接合部周边围绕接合部而连续地设置周边突起18。 
在本实施方式的半导体器件9中，在源极引线14的与接合线4的连接部周边连续地形成有周边突起18。该周边突起18通过例如销 钉加工而形成，例如利用压力机从源极引线14的背面通过半冲压而形成。 
该周边突起18用于防止本发明要解决的问题即树脂6和源极引线14的界面分离。也就是说，通过围绕在源极引线14上连接的接合线4的周边而连续地设置周边突起18，利用锚定(锁定)效果来大幅度提高树脂6和源极引线14的粘着性，防止树脂6和源极引线14的界面分离。特别是，周边突起18是围绕接合线4和源极引线14的连接部即接合部的周边而连续地设置的，所以能够应对从所有方向施加的机械应力而保护接合部。即，能够将由于在衬底上安装半导体器件9时的回焊工序中的热负荷而使得由树脂6和源极引线14的热膨胀系数差引起的界面分离从而导致的接合线4的断线和分离防于未然。另外，本实施方式的周边突起18能够利用压力机容易地形成，所以能够以低廉的原材料费和加工费来形成。 
由此，能够大幅度提高接合线4和源极引线14的连接可靠性提供可靠性高的半导体器件9。 
(实施方式4) 
本实施方式应用于功率MOSFET的封装的制造，使用图15～图19进行说明。 
图15是沿着图16的E-E线的剖视图，示出了本实施方式的半导体器件9的内部结构。图16是表示图15的半导体器件9的内部结构的俯视图，用双点划线示出了树脂6的外形。另外，图17和图18是本实施方式的半导体器件9的外观形状。图17是半导体器件9的上表面俯视图，图18是半导体器件9的下表面俯视图。图19是表示制造工序中的本实施方式的半导体器件9的剖视图。 
本实施方式的半导体器件9是在实施方式1的半导体器件9中，在突起7的背面不设置支柱16而仅形成凹部20。 
本实施方式的半导体器件9中，在源极引线14的与接合线4的连接部形成有突起7。该突起7和源极引线14背面的凹部20例如通过销钉加工而形成，利用例如压力机从源极引线14的背面通过半冲 压而形成。 
通过设置该突起7，能够利用锚定效果来提高树脂6和源极引线14的粘着性，能够抑制由于在衬底上安装半导体器件9时的回焊工序中的热负荷导致树脂6和源极引线14发生分离。 
此时，在突起7的背面的凹部20上没有形成实施方式1的支柱16。在本实施方式中，为了防止本发明要解决的问题即连接接合线4和源极引线14时的超声波衰减，如图19所示，在用树脂6密封半导体器件9之前的工序的、将接合线4连接在源极引线14上的工序中，使用预先配置有达到凹部20的底面的突起21的台22来作为设置半导体器件9的台。 
由此，例如在将接合线4连接在源极引线14时，即使从毛细管23的前端将超声波施加在接合线4上，也由于在凹部20的下部存在成为支撑的突起21，而能够防止由突起7发生振动使超声波的能量衰减而导致的接合线4和源极引线14之间的连接强度的降低。 
即，通过使用具备突起21的台22来代替实施方式1的支柱16，突起21成为突起7的支撑，能够抑制超声波能量的衰减，坚固地连接接合线4和源极引线14。另外，本实施方式的突起7和凹部20能够利用压力机容易地形成，所以能够以低廉的原材料费和加工费形成。 
由此，能够大幅度提高接合线4和源极引线14的连接可靠性、提供可靠性高的半导体器件9。 
图19中的引线接合以球焊(ball bonding)的连接为例进行说明，但也可以不使用毛细管23，通过使用了楔形工具的楔焊接向接合线4施加超声波来连接在源极引线14上。 
以上，根据实施方式具体说明了本发明者完成的发明，但本发明不限于上述实施方式，在不超出其主旨的范围内能够进行各种变更。 
工业上的可利用性 
本发明能够应用于对功率MOSFET、IGBT、双极型功率晶体管 等、以及将通过引线接合与引线框电连接的元件进行树脂密封的半导体器件的制造。 

Claims (13)

1.一种半导体器件，包括：
引线框，具有压料垫部和配置在上述压料垫部附近的第一引线；
装载在上述压料垫部上的半导体芯片；
接合线，使形成在上述半导体芯片的表面上的电极和上述第一引线电连接；以及
树脂，对上述半导体芯片、上述引线框、上述第一引线以及上述接合线进行密封，
上述半导体器件的特征在于，
在上述第一引线和上述接合线的连接面上，在上述第一引线的上表面设置有成为上述接合线的接合部的突起，并在上述突起的背面的一部分上形成有凹部，
在上述第一引线的上述凹部内且位于上述接合部的正下方，通过销钉加工形成有由上述第一引线的一部分构成的支柱，上述支柱被形成为从上述突起的背面开始直至与上述第一引线的背面相同的高度。
2.根据权利要求1所述的半导体器件，其特征在于，
上述突起和上述凹部通过销钉加工而形成。
3.根据权利要求1所述的半导体器件，其特征在于，
在上述突起的上表面，围绕上述接合部而通过销钉加工连续或者不连续地形成有台阶。
4.根据权利要求1所述的半导体器件，其特征在于，
上述接合线由Al构成。
5.根据权利要求1所述的半导体器件，其特征在于，
上述半导体芯片通过焊锡与上述压料垫部相接合。
6.根据权利要求1所述的半导体器件，其特征在于，
在上述半导体芯片上形成有功率MOSFET，上述压料垫部构成上述功率MOSFET的源电极。
7.根据权利要求1所述的半导体器件，其特征在于，
具有上述压料垫部的上述引线框的背面露出一部分，上述压料垫部和上述引线框兼作散热板用。
8.一种半导体器件，包括：
引线框，具有压料垫部和配置在上述压料垫部附近的第一引线；
装载在上述压料垫部上的半导体芯片；
接合线，使形成在上述半导体芯片的表面的电极和上述第一引线电连接；以及
树脂，对上述半导体芯片、上述引线框、上述第一引线以及上述接合线进行密封，
上述半导体器件的特征在于，
在上述第一引线和上述接合线的连接面上，在上述引线框的上表面围绕上述接合线的接合部而连续或不连续地设置有突起，并在上述突起的背面的一部分上形成有凹部。
9.根据权利要求8所述的半导体器件，其特征在于，
上述突起和上述凹部通过销钉加工而形成。
10.根据权利要求8所述的半导体器件，其特征在于，
上述接合线由Al构成。
11.根据权利要求8所述的半导体器件，其特征在于，
上述半导体芯片通过焊锡与上述压料垫部相接合。
12.根据权利要求8所述的半导体器件，其特征在于，
在上述半导体芯片上形成有功率MOSFET，上述压料垫部构成上述功率MOSFET的源电极。
13.根据权利要求8所述的半导体器件，其特征在于，
具有上述压料垫部的上述引线框的背面露出一部分，上述引线框兼作散热板用。
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JP5622934B2 (ja) * 2011-06-09 2014-11-12 三菱電機株式会社 半導体装置
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CN104103619B (zh) * 2014-06-30 2017-05-24 通富微电子股份有限公司 半导体功率器件的导线强化焊接结构
CN104600042A (zh) * 2014-12-25 2015-05-06 杰群电子科技（东莞）有限公司 一种半导体器件
DE102015104996B4 (de) * 2015-03-31 2020-06-18 Infineon Technologies Austria Ag Halbleitervorrichtungen mit Steuer- und Lastleitungen von entgegengesetzter Richtung
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1291789A (zh) * 1999-09-01 2001-04-18 松下电子工业株式会社 引线架及树脂封装型半导体器件的制造方法

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Publication number Priority date Publication date Assignee Title
JP3895570B2 (ja) * 2000-12-28 2007-03-22 株式会社ルネサステクノロジ 半導体装置
JP3436253B2 (ja) * 2001-03-01 2003-08-11 松下電器産業株式会社 樹脂封止型半導体装置およびその製造方法
JP4244318B2 (ja) * 2003-12-03 2009-03-25 株式会社ルネサステクノロジ 半導体装置
WO2008057770A2 (en) * 2006-10-27 2008-05-15 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
TWI337387B (en) * 2007-04-20 2011-02-11 Chipmos Technologies Inc Leadframe for leadless package, package structure and manufacturing method using the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1291789A (zh) * 1999-09-01 2001-04-18 松下电子工业株式会社 引线架及树脂封装型半导体器件的制造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JP特开2002-237559A 2002.08.23
JP特开平7-193173A 1995.07.28

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