CN104103619B - 半导体功率器件的导线强化焊接结构 - Google Patents
半导体功率器件的导线强化焊接结构 Download PDFInfo
- Publication number
- CN104103619B CN104103619B CN201410308021.XA CN201410308021A CN104103619B CN 104103619 B CN104103619 B CN 104103619B CN 201410308021 A CN201410308021 A CN 201410308021A CN 104103619 B CN104103619 B CN 104103619B
- Authority
- CN
- China
- Prior art keywords
- wire
- framework
- lead
- power device
- semiconductor power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Wire Bonding (AREA)
Abstract
本发明公开了一种半导体功率器件的导线强化焊接结构,包括框架内引线,所述框架内引线的表面具有焊接区,所述焊接区焊接有导线,所述焊接区两侧的框架内引线上设有向上的翻边,所述框架内引线、翻边及导线与焊接区连接的一端的外围设有塑封层。本发明通过设置翻边及塑封层,使框架内引线形成锁定结构,形成过程简单,框架内引线的锁定结构在塑封后通过塑封料的反作用力,可以有效提高导线跟框架内引线之间的结合力,从而改善导线的剥离强度,提高功率产品的可靠性。
Description
技术领域
本发明涉及半导体封装领域,具体涉及一种半导体功率器件的导线强化焊接结构。
背景技术
在半导体功率器件封装过程中,主要使用铝线、铝带等金属线将芯片和引线框架的内引线之间实现有效焊接,以满足功率器件工作时的大电压、大电流等高电性能要求。封装结构示意图如图1a和图1b所示,包括:用以散热和承载芯片2的框架载片台1;用以电连结的框架内引线3;用以连结芯片2与框架内引线3的铝线4或铝带5;用以将芯片2粘接在框架载片台1的装片胶6。
由于功率产品在工作时器件内部温度较高、有时外部工作环境也比较恶劣,要求铝线4或铝带5跟框架内引线3之间的焊接可靠性比较高,但是在功率产品可靠性中,实际应用时还是因为热应力、湿气、过程质量控制的波动等使铝线4、铝带5跟框架内引线3之间产生剥离,导致产品的电参数、功能失效。针对此失效,业内虽然通过键合参数、钢嘴结构、材料、过程分层控制等方面改善焊接可靠性,但是还不能非常有效地避免铝线4、铝带5跟框架内引线3之间的剥离。
发明内容
在下文中给出关于本发明的简要概述,以便提供关于本发明的某些方面的基本理解。应当理解,这个概述并不是关于本发明的穷举性概述。它并不是意图确定本发明的关键或重要部分,也不是意图限定本发明的范围。其目的仅仅是以简化的形式给出某些概念,以此作为稍后论述的更详细描述的前序。
本发明实施例的目的是针对上述现有技术的缺陷,提供一种能够避免导线与框架内引线之间的剥离,提高半导体功率器件可靠性的半导体功率器件的导线强化焊接结构。
为了实现上述目的,本发明采取的技术方案是:
一种半导体功率器件的导线强化焊接结构,包括框架内引线,所述框架内引线的表面具有焊接区,所述焊接区焊接有导线,所述焊接区两侧的框架内引线上设有向上的翻边,所述框架内引线、翻边及导线与焊接区连接的一端的外围设有塑封层。
与现有技术相比,本发明的有益效果是:
本发明通过设置翻边及塑封层,使框架内引线形成锁定结构,形成过程简单,框架内引线的锁定结构在塑封后通过塑封料的反作用力,可以有效提高导线跟框架内引线之间的结合力,从而改善导线的剥离强度,提高功率产品的可靠性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。
图1a是本发明实施例提供的半导体功率器件铝线键合后结构示意图;
图1b是本发明实施例提供的半导体功率器件铝带键合后结构示意图;
图2a是本发明实施例提供的铝线键合后半导体功率器件的导线强化焊接结构一种制作状态下的结构示意图;
图2b是本发明实施例提供的铝线键合后的半导体功率器件的导线强化焊接结构的另一种制作状态下结构示意图;
图2c是本发明实施例提供的铝线键合后半导体功率器件的导线强化焊接结构的结构示意图;
图3a是本发明实施例提供的铝带键合后半导体功率器件的导线强化焊接结构一种制作状态下的结构示意图;
图3b是本发明实施例提供的铝带键合后半导体功率器件的导线强化焊接结构另一种制作状态下的结构示意图;
图3c是本发明实施例提供的铝带键合后半导体功率器件的导线强化焊接结构的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。在本发明的一个附图或一种实施方式中描述的元素和特征可以与一个或更多个其它附图或实施方式中示出的元素和特征相结合。应当注意,为了清楚的目的,附图和说明中省略了与本发明无关的、本领域普通技术人员已知的部件和处理的表示和描述。基于本发明中的实施例,本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
参见图2c和图3c,一种半导体功率器件的导线强化焊接结构,包括框架内引线3,框架内引线3的表面具有焊接区,所述焊接区焊接有导线,所述焊接区两侧的框架内引线3上设有向上的翻边30,框架内引线3、翻边30及导线与焊接区连接的一端的外围设有塑封层7。
本发明通过设置翻边及塑封层,使框架内引线形成锁定结构,框架内引线的锁定结构在塑封后通过塑封料的反作用力,可以有效提高导线跟框架内引线之间的结合力,从而改善导线的剥离强度,提高功率产品的可靠性。
参见图2a和图3a,本实施例中,翻边30在竖直方向的高度为框架内引线3的厚度的2.5-3.5倍。优选为3.0倍。
为了对塑封料具有较强的锁定力,本发明在框架内引线两侧形成垂直竖起的翻边,翻边高度从框架内引线下表面开始计算,至少是框架内引线厚度的2.5倍,导线焊接在框架内引线的翻边之间。
参见图2b和图3b,本实施例中,为了进一步加强对塑封料的锁定力,通过反作用力从而改善导线在框架内引线上焊接点的剥离强度,翻边30与框架内引线3表面的夹角为5~85°。
本实施例中,为了便于制作,框架内引线3与翻边30为一体结构。
本发明更优选的实施例如下:
参见图2c和图3c,框架内引线3包括间隔距离依次设置的第一框架内引线31、第二框架内引线32及第三框架内引线33,导线包括第一导线和两个第二导线,第一框架内引线31的焊接区焊接有第一导线,第三框架内引线33的焊接区分别焊接有两个第二导线,第三框架内引线33的两侧设有向上的翻边30,第一框架内引线31、第二框架内引线32、第三框架内引线33、翻边30、第一导线与第一框架内引线31焊接区连接的一端、两个第二导线与第三框架内引线33焊接区连接的一端的外围设有塑封层7。
本发明两个第二导线焊接在两个翻边30之间,塑封料将第一框架内引线31、第二框架内引线32、第三框架内引线33、翻边30、第一导线与第一框架内引线31焊接区连接的一端、两个第二导线与第三框架内引线33焊接区连接的一端进行塑封,形成塑封层,实现对框架内引线3的锁定结构,塑封后通过塑封料的反作用力,可以有效提高导线跟框架内引线之间的结合力,从而改善导线的剥离强度,提高功率产品的可靠性。
参见图2a、图2b和图2c,第一导线及两个第二导线均为铝线4。
参见图3a、图3b和图3c,第一导线为铝线4,两个第二导线均为铝带5。
参见图2c和图3c,实际使用中,导线可以为铝线4、铝带5或铝线4与铝带5的组合。
参见图1a和图1b,实际使用中,本发明的半导体功率器件的导线强化焊接结构还包括框架载片台1,框架载片台1上固定连接有芯片2,可以采用装片胶6将芯片2粘接在框架载片台1上,导线远离框架内引线3的一端与芯片2焊接。
本发明在半导体功率器件封装过程中所用铝质焊线在焊接过程中,改善铝质焊线与框架内引线焊点连接的牢固强度,本发明尤其适用于功率较大或/和可靠性比较高的MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor,金氧半场效晶体管)、IGBT(Insulated Gate Bipolar Transistor),绝缘栅双极型晶体管)、SiC等芯片使用铝线或铝带焊接到框架内引线上。
最后应说明的是:以上实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。
Claims (8)
1.一种半导体功率器件的导线强化焊接结构,包括框架内引线,所述框架内引线的表面具有焊接区,所述焊接区焊接有导线,其特征在于,所述焊接区两侧的框架内引线上设有向上的翻边,所述框架内引线、翻边及导线与焊接区连接的一端的外围设有塑封层;
所述翻边与框架内引线表面的夹角为5~85°。
2.根据权利要求1所述的半导体功率器件的导线强化焊接结构,其特征在于,所述翻边在竖直方向的高度为所述框架内引线的厚度的2.5-3.5倍。
3.根据权利要求2所述的半导体功率器件的导线强化焊接结构,其特征在于,所述翻边在竖直方向的高度为所述框架内引线的厚度的3.0倍。
4.根据权利要求1所述的半导体功率器件的导线强化焊接结构,其特征在于,所述框架内引线与所述翻边为一体结构。
5.根据权利要求1-4任一项所述的半导体功率器件的导线强化焊接结构,其特征在于,所述框架内引线包括间隔距离依次设置的第一框架内引线、第二框架内引线及第三框架内引线,所述导线包括第一导线和两个第二导线,所述第一框架内引线的焊接区焊接有第一导线,所述第三框架内引线的焊接区分别焊接有两个第二导线,所述第三框架内引线的两侧设有向上的翻边。
6.根据权利要求5所述的半导体功率器件的导线强化焊接结构,其特征在于,所述第一导线和两个第二导线均为铝线。
7.根据权利要求5所述的半导体功率器件的导线强化焊接结构,其特征在于,所述第一导线为铝线,两个所述第二导线为铝带。
8.根据权利要求5所述的半导体功率器件的导线强化焊接结构,其特征在于,还包括框架载片台,所述框架载片台上固定连接有芯片,所述导线远离所述框架内引线的一端与所述芯片焊接。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410308021.XA CN104103619B (zh) | 2014-06-30 | 2014-06-30 | 半导体功率器件的导线强化焊接结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410308021.XA CN104103619B (zh) | 2014-06-30 | 2014-06-30 | 半导体功率器件的导线强化焊接结构 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104103619A CN104103619A (zh) | 2014-10-15 |
CN104103619B true CN104103619B (zh) | 2017-05-24 |
Family
ID=51671629
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410308021.XA Active CN104103619B (zh) | 2014-06-30 | 2014-06-30 | 半导体功率器件的导线强化焊接结构 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104103619B (zh) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1291789A (zh) * | 1999-09-01 | 2001-04-18 | 松下电子工业株式会社 | 引线架及树脂封装型半导体器件的制造方法 |
CN1663037A (zh) * | 2002-06-26 | 2005-08-31 | 三井金属矿业株式会社 | Cof薄膜输送带及其制造方法 |
CN101794758A (zh) * | 2009-01-22 | 2010-08-04 | 株式会社瑞萨科技 | 半导体器件 |
CN102222657A (zh) * | 2011-06-30 | 2011-10-19 | 天水华天科技股份有限公司 | 多圈排列双ic芯片封装件及其生产方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002237559A (ja) * | 2001-02-09 | 2002-08-23 | Sanyo Electric Co Ltd | 半導体装置の製造方法およびそれを用いた混成集積回路装置の製造方法 |
-
2014
- 2014-06-30 CN CN201410308021.XA patent/CN104103619B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1291789A (zh) * | 1999-09-01 | 2001-04-18 | 松下电子工业株式会社 | 引线架及树脂封装型半导体器件的制造方法 |
CN1663037A (zh) * | 2002-06-26 | 2005-08-31 | 三井金属矿业株式会社 | Cof薄膜输送带及其制造方法 |
CN101794758A (zh) * | 2009-01-22 | 2010-08-04 | 株式会社瑞萨科技 | 半导体器件 |
CN102222657A (zh) * | 2011-06-30 | 2011-10-19 | 天水华天科技股份有限公司 | 多圈排列双ic芯片封装件及其生产方法 |
Also Published As
Publication number | Publication date |
---|---|
CN104103619A (zh) | 2014-10-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105679750B (zh) | 压接式半导体模块及其制作方法 | |
CN106298722B (zh) | 一种大电流功率半导体器件的封装结构及制造方法 | |
CN205984966U (zh) | 一种大电流功率半导体器件的封装结构 | |
JP4973046B2 (ja) | 半導体装置の製造方法 | |
JPWO2014122908A1 (ja) | 半導体装置およびその製造方法 | |
CN104396011A (zh) | 半导体装置 | |
CN103928408B (zh) | 功率半导体模块和用于制造功率半导体模块的方法 | |
CN103682046A (zh) | 一种led用陶瓷基板 | |
CN104103619B (zh) | 半导体功率器件的导线强化焊接结构 | |
CN105914205A (zh) | 一种功率模块结构及制造方法 | |
CN104064484B (zh) | 半导体功率器件的强化导线焊接点的方法 | |
JP2012174925A (ja) | 半導体装置及びその製造方法、電源装置 | |
CN103779305A (zh) | 一种金属连接件及功率半导体模块 | |
CN104064484A (zh) | 半导体功率器件的强化导线焊接点的方法 | |
CN108074802A (zh) | 一种金属电极制备方法及压接式igbt | |
CN104064540B (zh) | 半导体器件的导线焊点强化结构 | |
CN104078374B (zh) | 半导体器件的导线焊接点强化方法 | |
CN204011404U (zh) | 半导体器件的导线焊接点强化结构 | |
CN104064485B (zh) | 半导体器件的导线焊点强化方法 | |
CN204991689U (zh) | Igbt模块 | |
CN104867919B (zh) | 提高光耦可靠性的封装结构及封装工艺 | |
KR102394542B1 (ko) | 반도체 패키지 및 그 제조 방법 | |
CN204558445U (zh) | 半导体封装结构 | |
CN102456656A (zh) | 芯片封装结构 | |
CN219246674U (zh) | 一种半导体芯片 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information |
Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
|
COR | Change of bibliographic data | ||
GR01 | Patent grant | ||
GR01 | Patent grant |