CN102456656A - 芯片封装结构 - Google Patents

芯片封装结构 Download PDF

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CN102456656A
CN102456656A CN2011103393795A CN201110339379A CN102456656A CN 102456656 A CN102456656 A CN 102456656A CN 2011103393795 A CN2011103393795 A CN 2011103393795A CN 201110339379 A CN201110339379 A CN 201110339379A CN 102456656 A CN102456656 A CN 102456656A
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chip
lead frame
contiguous block
chip carrier
gold
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资重兴
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Abstract

本发明公开一种芯片封装结构，主要通过当芯片进行封装，在打上连接芯片与芯片座的连接金线前，先行于芯片座的导电层上接合一连接块，并将连接金线的两端分别焊设于该连接块与芯片座上，藉此防止因脱层现象发生所造成的电讯连接断离，以有效提高芯片封装的良率、降低制造及加工成本为其主要发明要点。

Description

芯片封装结构
技术领域
本发明涉及一种芯片封装结构，主要是利用于芯片座的导电层上先行接合有连接块，并将连接金线的两端分别焊设于芯片与该连接块上，除能有效防止脱层现象发生所造成的电讯断离外，更能进一步增加芯片封装的良率、降低制造及加工成本。
背景技术
目前产业上所使用的芯片组封装，如图1及图2所示，主要构件包括有芯片座导线架1、芯片4、导线架6及金线5，其中，芯片座1上会被涂布设有一层铜质物层2做为导电之用，而芯片座1与芯片4的接合是通过一种接合剂3，而导线架6的上层也涂布设有铜质物层7，并通过金线5的连接使芯片4分别与芯片座1及导线架6做电性信号连接；然而，有时会因为芯片座1的铜质物层2上有杂质存在(业界称铜层污染)，或是接合剂3的溢出置于铜质物层2上未被发现，使金线5被焊设于芯片座1上的一端实际是接触到杂质或接合剂3的情况下，当该芯片组进行封装过程时，其热胀冷缩作用就会造成芯片座1的表面有脱层现象(Delamination)8的发生，连带使得本应被焊设于芯片座1的铜质物层2上的金线5一端，因脱层现象8的影响而脱离芯片座1的铜质物层2上；换言的，就是金线5的本应接合于芯片座1的铜质物层2上的一端51并不会被牢固地接合，如此一来便造成电讯的无法连接，而该芯片组也成为一个暇疵不良品，不仅大幅降低芯片组封装的良率外，相对也会造成制造及加工成本的居高不下，形成业界不小的困扰。
因此为有效解决上述缺失，本发明提出一利用连接块构件的适当增设来有效降低脱层现象的产生，以提升芯片组封装良率外，也相对降低封装成本以符合产业之利用。
发明内容
本发明的目的在于提供一种芯片封装结构，主要是通过在芯片座的导电层上先行接合一连接块，再将金线的一端焊设于该连接块上，藉此防止因脱层现象发生所造成的电讯连接断离，以有效提高芯片封装的良率、降低制造及加工成本为其主要创作目的。
为达上述目的，本发明提供一种芯片封装结构，包括：
一芯片座导线架，其上设有一层导电层；
一芯片，利用接合剂可使该芯片与该芯片座导线架加以接合固设；
一连接块，设于芯片座导线架的导电层上的适当位置处，与芯片座导线架具有电性连接；
一金线，两端分别连接芯片与连接块，以达电讯连结。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图说明
图1为现有芯片封装的组合剖视示意图；
图2为现有芯片封装具有脱层现象发生时的组合剖视示意图；
图3为本发明的组合剖视示意图；
图4为本发明另一较佳实施例的组合剖视示意图。
其中，附图标记
现有技术
芯片座导线架1
铜质物层2
接合剂3
芯片4
金线5
导线架6
铜质物层7
脱层现象8
本发明
芯片座导线架10
导电层101
芯片20
顶部201
接合剂30
连接块40
顶面401
金球402
金线50
金球体501
导线架60
具体实施方式
下面结合附图对本发明的结构原理和工作原理作具体的描述：
请参阅图3所示，主要包括有一芯片座导线架10，该芯片座导线架10主要是供予芯片20放置之用，在该芯片座导线架10上涂布有一层导电层101做为导电物质之用，而介于该导电层101与芯片20之间则通过接合剂30加以接合，而令该芯片20可被固设于该芯片座导线架10之上，其中该导电层101的材质可为金、铜或铝等导电性佳的金属材质；
在该芯片座导线架10的导电层101的上方的适当位置处，是利用超音波震荡接合的方式设有一连接块40，该连接块40与芯片座导线架10具有电性连接，且由于该连接块40的接合是于无尘室中利用超音波震荡原理完成，因此能完全避免杂质中介于芯片座导线架10及连接块40间的情况发生，同时该连接块40的接合程序可早于芯片20被接合于芯片座导线架10的接合程序前，因此也能避免接合剂中介于芯片座导线架10及连接块40间的情况发生，而该连接块40的材质可为金、铜或铝等导电性佳的金属块；
当连接块40及芯片20分别被接合于芯片座导线架10之上后，则利用焊针(图中未表示)穿置有金线50先行于芯片20的顶部201(即非接合于芯片座导线架10的一面)焊烧出金球体501后，再行拉引出金线50至连接块40的顶面401(即为非接合于芯片座导线架10的一面)进行焊设连接，如此便完成芯片20与芯片座导线架10的电讯连结，其后再同样利用金线50将芯片20与导线架60形成电讯连结后再行封装，即成芯片的封装程序；
由于该连接块40有其体积及高度，在芯片20利用接合剂30接合于芯片座导线架10上时，即使用少量的接合剂30溢出，也不会令接合剂30沾附于连接块40的顶面401(即为将进行金线50焊接的面)而对电讯连接造成影响，因此能完全改善目前业界芯片封装因脱层现象(Delamination)发生所造成的电讯连接断离及良率低等不良情况；
请再参阅图4所示，图4为本发明另一较佳实施例图，主要是为了令金线50与连接块40的顶面401有更佳的电讯连接状况，因此在进行金线50焊接前，先行于连接块40的顶面401烧设有一金球402，而在金线50先行于芯片20的顶部201焊烧出金球体501并拉引金线50至连接块40的顶面401时，则直接将金线50焊设连接于连接块40顶面401的金球402上，如此一来能使金线50与连接块40的结合更形稳固，进而提高芯片封装的良率；
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。

Claims (5)

1.一种芯片封装结构，其特征在于，包括：
一芯片座导线架，其上设有一层导电层；
一芯片，利用接合剂可使该芯片与该芯片座导线架加以接合固设；
一连接块，设于芯片座导线架的导电层上的适当位置处，与芯片座导线架具有电性连接；
一金线，两端分别连接芯片与连接块，以达电讯连结。
2.根据权利要求1所述的芯片封装结构，其特征在于，该导电层的材质为金、铜或铝等导电性金属材质。
3.根据权利要求1所述的芯片封装结构，其特征在于，该连接块的材质为金、铜或铝等导电性的金属块。
4.根据权利要求1所述的芯片封装结构，其特征在于，该连接块与芯片座导线架的接合于无尘室中利用超音波震荡原理完成。
5.根据权利要求1所述的芯片封装结构，其特征在于，连接块的顶面预先烧设有金球，以增加金线与连接块的结合稳固性。
CN2011103393795A 2010-10-28 2011-10-28 芯片封装结构 Pending CN102456656A (zh)

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