CN202816917U - 一种多芯片半导体器件 - Google Patents

一种多芯片半导体器件 Download PDF

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CN202816917U
CN202816917U CN2012204687546U CN201220468754U CN202816917U CN 202816917 U CN202816917 U CN 202816917U CN 2012204687546 U CN2012204687546 U CN 2012204687546U CN 201220468754 U CN201220468754 U CN 201220468754U CN 202816917 U CN202816917 U CN 202816917U
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semiconductor device
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chips
circuit substrate
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罗艳玲
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Great Team Backend Foundry Dongguan Co Ltd
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Abstract

本实用新型涉及半导体器件技术领域，特别涉及一种多芯片半导体器件，其结构包括IC芯片和MOS芯片，还包括管脚和电路基板，所述IC芯片和MOS芯片分别焊接在对应的电路基板上，所述IC芯片通过铜线分别与MOS芯片、电路基板和管脚电连接，所述MOS芯片通过铝线分别与电路基板和管脚电连接。由于IC芯片焊盘尺寸较小，不利于铝线焊接，因此采用铜线焊接，而MOS芯片的焊盘尺寸较大，采用铝线替代铜线焊接，而一条铝线能够代替多条铜线，因此能减少了接合线的数量，减小了器件的总体尺寸，同时也避免了大量密集的铜线会产生寄存性电容的问题，提高器件性能。

Description

一种多芯片半导体器件
技术领域
本实用新型涉及半导体器件技术领域，特别涉及一种多芯片半导体器件。
背景技术
现如今，半导体集成电路芯片因其体积小，处理能力强而得到越来越广泛的使用。而随着技术的进步，越来越多的半导体器件需要将多个半导体元件封装在一起。同时为了实现各个半导体元件之间的电连接，一般需要采用接合线使半导体元件之间实现电连接。
现有技术中，一般采用铜线或者铝线等单一形式的金属线作为接合线，但是由于半导体器件中有多个半导体元件，所以需要较多的接合线，如果单独采用铜线作为接合线，大量的铜线会占用比较多的空间，增加了半导体器件的体积，同时比较密集的铜线之间也容易产生较大的寄存性电容，影响半导体器件性能。另一方面，由于接合线数量较多，焊接需要较多时间，生产效率低下。如果采用铝线作为连接线，由于一根铝线可替代多条铜线，因此可大大减少接合线的数量，避免采用铜线时遇到的诸多问题，但是，由于IC芯片上的焊盘尺寸较小，而采用铝线焊点较大，容易造成短路等问题，所以在IC芯片上不适合采用铝线作为接合线。
因此，为解决现有技术中的不足之处，提供一种能减少半导体器件接合线数量，缩小半导体器件尺寸，同时又不影响半导体器件性能的半导体器件技术显得尤为重要。
发明内容
本实用新型的目的在于避免上述现有技术中的不足之处而提供一种能减少半导体器件接合线，缩小半导体器件尺寸的多芯片半导体器件。
本实用新型的目的通过以下技术方案实现：
提供了一种多芯片半导体器件，包括IC芯片和MOS芯片，还包括管脚和电路基板，所述IC芯片和MOS芯片分别焊接在对应的电路基板上，所述IC芯片通过铜线分别与MOS芯片、电路基板和管脚电连接，所述MOS芯片通过铝线分别与电路基板和管脚电连接。
其中，所述铜线外表面涂覆有涂覆层。
其中，还包括引线框架，所述引线框架上设置有焊接区，所述电路基板焊接于所述焊接区上。
其中，所述半导体应先框架的外部对应所述IC芯片的位置设置有散热板。
其中，所述引线框架的外部对应所述MOS芯片的位置设置有散热板。
本实用新型的有益效果：提供了一种多芯片半导体器件，包括IC芯片和MOS芯片，还包括管脚和电路基板，所述IC芯片和MOS芯片分别焊接在对应的电路基板上，所述IC芯片通过铜线分别与MOS芯片、电路基板和管脚电连接，所述MOS芯片通过铝线分别与电路基板和管脚电连接。由于IC芯片焊盘尺寸较小，不利于铝线焊接，因此，采用铜线焊接，而MOS芯片的焊盘尺寸较大，采用铝线替代铜线焊接，而一条铝线能够代替多条铜线，本实用新型采用铜线和铝线相结合的接合方式，不仅能减少接合线的使用数量，减小了器件的总体尺寸，同时也避免了大量密集的铜线会产生寄存性电容的问题，提高器件性能。
附图说明
利用附图对本实用新型作进一步说明，但附图中的实施例不构成对本实用新型的任何限制，对于本领域的普通技术人员，在不付出创造性劳动的前提下，还可以根据以下附图获得其它的附图。
图1为本实用新型一种多芯片半导体器件的实施例的内部结构示意图。
图2为本实用新型一种多芯片半导体器件的实施例的结构示意图。
在图1至图2中包括有：
1——IC芯片、2——MOS芯片、3——管脚、4——电路基板、5——铜线、6——铝线、7——引线框架 、8——散热板。
具体实施方式
结合以下实施例对本实用新型作进一步描述。
本实用新型一种多芯片半导体器件的具体实施方式，如图1至图2所示，包括有：包括IC芯片1和MOS芯片2，还包括管脚3和电路基板4，所述IC芯片1和MOS芯片2分别焊接在对应的电路基板4上，所述IC芯片1通过铜线5分别与MOS芯片2、电路基板4和管脚3电连接，所述MOS芯片2通过铝线6分别与电路基板4和管脚3电连接。由于IC芯片1焊盘尺寸较小，不利于铝线6焊接，因此采用铜线5焊接，而MOS芯片2的焊盘尺寸较大，采用铝线6替代铜线5焊接，而一条铝线6能够代替多条铜线5，因此能减少了接合线的数量，减小了器件的总体尺寸，同时也避免了大量密集的铜线5会产生寄存性电容的问题，提高器件性能。
本实施例中，所述铜线5外表面涂覆有涂覆层。涂覆层既能够有效的保护铜线5，提高铜线5以及金线的耐高温特性，耐迁移性等，同时还可以减低接合线之间的寄存性电容，进一步提高多芯片半导体器件的性能。
本实施例中，还包括引线框架7，所述引线框架7上设置有焊接区，所述电路基板4焊接于所述焊接区上。引线框架7的设置既能固定电路基板4进一步固定芯片，是半导体器件的结构更加牢固可靠，同时也方便对半导体器件的封装。
本实施例中，所述引线框架7的外部应所述IC芯片的位置和MOS芯片的位置设置有散热板8。由于在半导体元件工作时会产生大量的热量，如不及时散热会严重引线半导体元件的性能甚至烧坏元件。通过设置散热板8能有效将半导体元件产生的热量向外传导，达到散热的目的，使得高性能半导体元件能正常工作，不影响性能。
最后应当说明的是，以上实施例仅用以说明本实用新型的技术方案，而非对本实用新型保护范围的限制，尽管参照较佳实施例对本实用新型作了详细地说明，本领域的普通技术人员应当理解，可以对本实用新型的技术方案进行修改或者等同替换，而不脱离本实用新型技术方案的实质和范围。

Claims (5)

1.一种多芯片半导体器件，包括IC芯片（1）和MOS芯片（2），其特征在于：还包括管脚（3）和电路基板（4），所述IC芯片（1）和MOS芯片（2）分别焊接在对应的电路基板（4）上，所述IC芯片（1）通过铜线（5）分别与MOS芯片（2）、电路基板（4）和管脚（3）电连接，所述MOS芯片（2）通过铝线（6）分别与电路基板（4）和管脚（3）电连接。
2.如权利要求1所述的一种多芯片半导体器件，其特征在于：所述铜线（5）外表面涂覆有涂覆层。
3.如权利要求1所述的一种多芯片半导体器件，其特征在于：还包括引线框架（7），所述引线框架（7）上设置有焊接区，所述电路基板（4）焊接于所述焊接区上。
4.如权利要求3所述的一种多芯片半导体器件，其特征在于：所述引线框架（7）的外部对应所述IC芯片（1）的位置设置有散热板（8）。
5.如权利要求3所述的一种多芯片半导体器件，其特征在于：所述引线框架（7）的外部对应所述MOS芯片（2）的位置设置有散热板（8）。
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