CN104064540B - 半导体器件的导线焊点强化结构 - Google Patents

半导体器件的导线焊点强化结构 Download PDF

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CN104064540B
CN104064540B CN201410308072.2A CN201410308072A CN104064540B CN 104064540 B CN104064540 B CN 104064540B CN 201410308072 A CN201410308072 A CN 201410308072A CN 104064540 B CN104064540 B CN 104064540B
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CN104064540A (zh
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石海忠
王洪辉
郇林香
缪小勇
成明建
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Tongfu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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Abstract

本发明提供一种半导体器件的导线焊点强化结构，包括框架内引线，所述框架内引线的表面具有焊接区，所述焊接区焊接有导线，还包括锁定卡；所述锁定卡包括按压部，所述按压部向外悬伸有锁定部，所述按压部压在所述导线上，所述锁定部穿过所述框架内引线，且卡在所述框架内引线背离所述导线的一侧。本发明提供的上述方案，通过锁定卡将焊接于框架内引线上的导线，牢靠的卡箍在框架内引线上，有效的避免了导线与框架内引线剥离的情况发生，加强了导线与框架内引线的电连接，提高了半导体器件，特别是半导体功率器件的可靠性。

Description

半导体器件的导线焊点强化结构
技术领域
本发明涉及半导体器件封装技术领域，尤其涉及一种半导体器件的导线焊点强化结构。
背景技术
在半导体功率器件封装过程中，主要使用铝线、铝带等金属线将芯片和引线框架的框架内引线之间实现有效焊接，以满足功率器件工作时的大电压、大电流等高电性能要求。封装结构示意如图1-图4所示，包括：用以散热和承载芯片2的框架载片台1；用以电连结的框架内引线3；用以连结芯片2与框架内引线3的铝线4和/或铝带5；用以将芯片2粘接在框架载片台1的装片胶6。
由于功率产品在工作时器件内部温度较高、有时外部工作环境也比较恶劣，要求铝线4和/或铝带5跟框架内引线3之间的焊接可靠性比较高，但是在功率产品可靠性中、实际应用时还是会因为热应力、湿气、过程质量控制的波动等使铝线4、铝带5跟框架内引线3之间产生剥离，导致产品的电参数、功能失效。针对此失效，业内虽然通过键合参数、钢嘴结构、材料、过程分层控制等方面改善焊接可靠性，但是还不能非常有效地避免铝线4、铝带5跟框架内引线3之间的剥离。
发明内容
在下文中给出关于本发明的简要概述，以便提供关于本发明的某些方面的基本理解。应当理解，这个概述并不是关于本发明的穷举性概述。它并不是意图确定本发明的关键或重要部分，也不是意图限定本发明的范围。其目的仅仅是以简化的形式给出某些概念，以此作为稍后论述的更详细描述的前序。
本发明提供一种半导体器件的导线焊点强化结构，包括框架内引线，所述框架内引线的表面具有焊接区，所述焊接区焊接有导线，还包括：
锁定卡；
所述锁定卡包括按压部，所述按压部向外悬伸有锁定部，所述按压部压在所述导线上，所述锁定部穿过所述框架内引线，且卡在所述框架内引线背离所述导线的一侧。
本发明提供的上述方案，通过锁定卡将焊接于框架内引线上的导线，牢靠的卡箍在框架内引线上，有效的避免了导线与框架内引线剥离的情况发生，加强了导线与框架内引线的电连接，提高了半导体器件，特别是半导体功率器件的可靠性。
附图说明
参照下面结合附图对本发明实施例的说明，会更加容易地理解本发明的以上和其它目的、特点和优点。附图中的部件只是为了示出本发明的原理。在附图中，相同的或类似的技术特征或部件将采用相同或类似的附图标记来表示。
图1为现有技术的结构示意图；
图2为图1的A-A剖面图；
图3为另一现有技术的结构示意图；
图4为图3的B-B剖面图；
图5为本发明实施例提供的半导体器件的导线焊点强化结构的示意图；
图6为图5的C-C剖面图。
具体实施方式
下面参照附图来说明本发明的实施例。在本发明的一个附图或一种实施方式中描述的元素和特征可以与一个或更多个其它附图或实施方式中示出的元素和特征相结合。应当注意，为了清楚的目的，附图和说明中省略了与本发明无关的、本领域普通技术人员已知的部件和处理的表示和描述。
图5为本发明实施例提供的半导体器件的导线焊点强化结构的示意图；图6为图5的C-C剖面图。如图5、图6所示，本发明实施例提供的半导体器件的导线焊点强化结构，包括框架内引线3，框架内引线3的表面具有焊接区，焊接区焊接有导线，还包括锁定卡；锁定卡包括按压部，按压部向外悬伸有锁定部，按压部压在导线上，锁定部穿过框架内引线3，且卡在框架内引线3背离导线的一侧。
本发明提供的上述方案，通过锁定卡将焊接于框架内引线3上的导线，牢靠的卡箍在框架内引线3上，有效的避免了导线与框架内引线剥离的情况发生，加强了导线与框架内引线的电连接，提高了半导体器件，特别是半导体功率器件的可靠性。
具体地，锁定部具有远离所述按压部的悬伸末端，悬伸末端弯折扣于框架内引线3背离导线的一侧。其中，锁定部可以是从按压部向外悬伸的金属条或金属片。金属条或金属片远离按压部的一端即为悬伸末端。在金属条或金属片穿过通孔后，将其悬伸末端进行折弯，使其紧紧的压在框架内引线3的一侧。采用此种结构连接可靠性高，连接工艺易于实现，成本低。
实际使用中，在导线的两侧均设置有贯穿框架内引线3的通孔，锁定部通过通孔穿过框架内引线。通过在导线的两侧均设置通孔，使锁定卡的锁定部穿过通孔，并卡在框架内引线3的侧面，可以很好的将导线紧紧的箍在导线内引线上。此外，也可以在框架内引线的边缘处设置有凹槽，锁定部通过凹槽穿过所述框架内引线。该凹槽例如但不限于为半圆形的通孔。
实际使用中，按压部上同向向外悬伸有两个锁定部，两锁定部的悬伸末端相向弯折。相向弯折占用框架内引线侧面的空间小，可以尽量利用框架内引线侧面的空间。作为其中一种优选的实现方式，锁定卡可以采用各边大体呈直线的直边C形结构。另外，作为一种可实现方案，两锁定部的悬伸末端也可以相背弯折。
实际使用中，导线可以为铝线4、铝带5或铝线4与铝带5的组合。
在导线采用铝线4时，铝线4背离框架内引线3的一侧具有弧形凸起，按压部具有弧形拱起，弧形凸起与弧形拱起吻合配合，使锁定卡7与导线接触更加紧密，提高了锁定卡7与铝线4连接的稳定性。以锁定卡7采用直边C形结构为例，正对锁定卡7开口的大体呈直线的部分为按压部9，在该大体呈直线的部分的中部设置了弧形拱起，在按压部9的两侧，分别向下延伸形成锁定部10，锁定部10的悬伸末端弯折卡在框架内引线3的下侧面。
在导线采用铝带5时，按压部11朝向铝带5的一侧为平面，平面与铝带5的表面吻合配合，使锁定卡8与导线接触更加紧密，提高了锁定卡8与铝带5连接的稳定性。以锁定卡8采用直边C形结构为例，正对锁定卡8开口的直线的部分为按压部11。在按压部11的两侧，分别向下延伸形成锁定部12，锁定部12的悬伸末端弯折卡在框架内引线3的下侧面。
实际使用中，该半导体器件的导线焊点强化结构还包括框架载片台1，框架载片台1上固定连接有芯片2，可以采用装片胶6将芯片2粘接在框架载片台1上，导线远离框架内引线3的一端与芯片2焊接。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (8)

1.一种半导体器件的导线焊点强化结构，包括框架内引线，所述框架内引线的表面具有焊接区，所述焊接区焊接有导线，其特征在于，还包括：
锁定卡；
所述锁定卡包括按压部，所述按压部向外悬伸有锁定部，所述按压部压在所述导线上，所述锁定部穿过所述框架内引线，且卡在所述框架内引线背离所述导线的一侧，
所述框架内引线的边缘处设置有凹槽，所述锁定部通过所述凹槽穿过所述框架内引线。
2.根据权利要求1所述的半导体器件的导线焊点强化结构，其特征在于，所述锁定部具有远离所述按压部的悬伸末端，所述悬伸末端弯折扣于所述框架内引线背离所述导线的一侧。
3.根据权利要求2所述的半导体器件的导线焊点强化结构，其特征在于，所述按压部上同向向外悬伸有两个锁定部，两所述锁定部的所述悬伸末端相向或相背弯折。
4.根据权利要求1-3任一项所述的半导体器件的导线焊点强化结构，其特征在于，所述导线为铝线，所述铝线背离所述框架内引线的一侧具有弧形凸起，所述按压部具有弧形拱起，所述弧形凸起与所述弧形拱起吻合配合。
5.根据权利要求4所述的半导体器件的导线焊点强化结构，其特征在于，还包括框架载片台，所述框架载片台上固定连接有芯片，所述导线远离所述框架内引线的一端与所述芯片焊接。
6.根据权利要求1-3任一项所述的半导体器件的导线焊点强化结构，其特征在于，所述导线为铝带，所述按压部朝向所述铝带的一侧为平面，所述平面与所述铝带的表面吻合配合。
7.根据权利要求6所述的半导体器件的导线焊点强化结构，其特征在于，还包括框架载片台，所述框架载片台上固定连接有芯片，所述导线远离所述框架内引线的一端与所述芯片焊接。
8.根据权利要求1-3任一项所述的半导体器件的导线焊点强化结构，其特征在于，所述导线的两侧均设置有贯穿所述框架内引线的通孔，所述锁定部通过所述通孔穿过所述框架内引线。
CN201410308072.2A 2014-06-30 2014-06-30 半导体器件的导线焊点强化结构 Active CN104064540B (zh)

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Application Number Priority Date Filing Date Title
CN201410308072.2A CN104064540B (zh) 2014-06-30 2014-06-30 半导体器件的导线焊点强化结构
US15/106,774 US9837371B2 (en) 2014-06-30 2014-11-07 Structure and method of reinforcing a conductor soldering point of semiconductor device
PCT/CN2014/090580 WO2016000377A1 (zh) 2014-06-30 2014-11-07 半导体器件的导线焊点强化结构与方法

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04192588A (ja) * 1990-11-27 1992-07-10 Sony Corp プリント基板における一方の面の回路パターンと他方の面の回路パターンとの接続方法
WO2004077901A2 (de) * 2003-02-27 2004-09-10 Endress+Hauser Gmbh+Co. Kg Leiterplatte und verfahren zur fixierung von bedrahteten bauteilen auf der leiterplatte
JP2005252006A (ja) * 2004-03-04 2005-09-15 Sumitomo Electric Ind Ltd 集積回路モジュール
JP2013058553A (ja) * 2011-09-07 2013-03-28 Nikon Corp シールド付き信号線及びこれに用いられる片面フレキシブル基板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030049955A1 (en) * 2001-09-13 2003-03-13 Bel-Fuse, Inc. Clip for replaceable surface mounted devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04192588A (ja) * 1990-11-27 1992-07-10 Sony Corp プリント基板における一方の面の回路パターンと他方の面の回路パターンとの接続方法
WO2004077901A2 (de) * 2003-02-27 2004-09-10 Endress+Hauser Gmbh+Co. Kg Leiterplatte und verfahren zur fixierung von bedrahteten bauteilen auf der leiterplatte
JP2005252006A (ja) * 2004-03-04 2005-09-15 Sumitomo Electric Ind Ltd 集積回路モジュール
JP2013058553A (ja) * 2011-09-07 2013-03-28 Nikon Corp シールド付き信号線及びこれに用いられる片面フレキシブル基板

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