TW523888B - Semiconductor device package and lead frame with die overhanging lead frame pad - Google Patents
Semiconductor device package and lead frame with die overhanging lead frame pad Download PDFInfo
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- TW523888B TW523888B TW090130895A TW90130895A TW523888B TW 523888 B TW523888 B TW 523888B TW 090130895 A TW090130895 A TW 090130895A TW 90130895 A TW90130895 A TW 90130895A TW 523888 B TW523888 B TW 523888B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
- H01L2924/13034—Silicon Controlled Rectifier [SCR]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
五、發明説明(1 ) 本申請案請求2_年12月14日申請之第6〇/25號 美國專利臨時申請案的權利。 本發明係有關於半導體裝置封裝體,尤有關於一種新 穎的封裝體,乃可減少半導體晶粒上的機械應力者。 半導體裝置係為公知者,其中有一薄而易碎的石夕晶粒 會被以焊接’或使用導電或非導電的黏劑例如環氧樹脂 等’來固設於-引線框架上。該引線框架一般係為導電材 料例如扁薄的鍍銅合金條帶,㈣有許多相同的紋路圖案 會被沖壓在該條帶上。該等圖案會形成較大的接墊區域可 供固設-對應的晶粒,以及許多—體連結的端子部或引線 或導銷”(接腳)等,按序地與該接塾隔離,它們會被接線 而由该等引線連接至晶粒頂面上的電極。在接線之後,個 別的引線框架裝置部份會被以—適當的塑膠外殼來成型包 封。該等個別的封裳體嗣會被分開,且各種不同的端子將 會互相隔離’而使該等引線或導銷由該等端子區部及接墊 連接件等突伸穿出該殼壁’以供電連接被包封在該封裝體 内的晶粒。 承裝該石夕晶粒的接墊在以往係具有比該晶粒更大的面 積,俾使該晶粒的整個底部表面能被牢固地連結於接塾表 面上。由於該矽晶粒與金屬或其它的接墊基材具有不同的 熱脹係數,故在焊接或其它的生熱接合過程中,以及在測 試或操作的減環過程中,該晶粒會在整個表面區域產生 機械應力。該等應力會使該晶粒造成損害或破裂。 依據本發明,該矽晶粒的尺寸係被設成,至少在一方
本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) A7 ' ------— B7 _ 五、發明説明(2 ) ~~" --- 向而最好是全部各方向,合 Π 會比承裝該晶粒的接墊更大。因 此,该晶粒會以一較小却彳八ΑΑ I i i 4伤的面積來固接於接墊,故施加 於該晶粒的總應力將可減少。 在一較佳實施例中,、 至夕有一小面積但外伸的晶粒會 與二更小面積的接墊來一法击 木趣使用。故,該二較小的晶粒能 與一以在使用的單-晶粒具有相同的總面積,而該二晶粒 皆會具有較小的接墊接觸面積。因此,在該二(或更多)晶 粒上的應力會被大大地減少。 在本叙明之一較佳實施例中,二個外伸的m〇sfet(金 屬氧化物半導體場效應電晶體)乃可被用來形成一 6引線的 TSOT式封裝體。該等晶粒可按須要來被互相連接(成並聯 或串如)。其它裝置的晶粒組合物,例如,一 晶粒 與Schottky二極體晶粒亦可被設在同一封裝體内,而其 兩者皆會突伸於它們各自的引線框架接墊外部。 本發明的重大優點係,其可在一標準外廓規格之塑膠 封衣體内谷納該更大許多的矽晶粒面積,而不必增加該外 靡尺寸。 圖式之簡單說明·· 第1圖示出可與本發明一起使用之一引線框架的一小 部份; 第2圖示出第1圖中的引線框架具有二晶粒設於定位, 而各伸出所對應的引線框架接墊外部; 第3圖為一 6導銷封裝體在以一塑膠殼體包封成型,並 將該封裝體與該引線框架分開之後的頂視示意圖; 本紙張尺度翻中關家標準(CNS) A4規格(21GX297公爱) _ 5 - (請先閲讀背面之注意事項再填寫本頁) 訂— 523888 A7 B7 五、發明説明(3 ) 第4圖為第3圖的封裝體之側視圖。 (請先閱讀背面之注意事項再填寫本頁) 請參閱第1圖,乃示出一大的普通引線框架20之一小部 份,該引線框架20係被冲製形成許多相同的圖案,其中之 一即如第1圖所示。該圖案含有二承裝晶粒的接墊21與22, 其各分別具有一體延伸的銷23與24等。該引線框架更包含 閘極導銷25與26(供各MOSFETs的閘極使用),及源極導銷 27與28(供在接墊21與22上之各MOSFETs的源極電極使 用)。 、τ· 要陳明的是,雖其示出單一封裝體設有二接墊,但亦 可使用所需數目的接墊;且事實上,一晶粒亦可分占一個 以上的接墊。不同於M0SFET晶粒之其它晶粒亦能被使 用,只要適當地改變該引線框架中突出的導銷即可。 章 嗣如第2圖所示,二半導體晶粒30與3 1會分別被固設於 接墊21與22上。該晶粒30與3 1係為垂向導接的MOSFETs, 其皆具有一習知的底部汲極電極,而源極電極與閘極電極 則設於它們的頂面上。該等電極紋路係為習知而未示出。 任何其匕的半導體晶粒亦可被使用,包括二極體、IGbts、 半導體開關元件、及雙載子電晶體等。 依據本發明’该等晶粒3 0與3 1的面積係分別大於該等 接墊21與22,並伸出該等接墊21與22外部而環繞它們的整 個周邊。在本發明之一實施例中,該等晶粒3〇與31可皆為 0.99mmx:L092mm的尺寸,而該等接墊21與22則可皆為 0.79mmx0.89mm的尺寸。雖該二晶粒被示出具有相同尺 寸,及該二接墊亦具有相同尺寸,但請瞭解該二接墊21與
A7 _________B7 _ 五、發明説明(4 ) 22亦可具有不同的尺寸,且該二晶粒30與31亦可具有不同 尺寸。 該等晶粒30與31的底部汲極電極係如習知般地以焊接 或黏接來分別固接於接墊2丨與22的相對區域上。 明顯地,該等晶粒3〇與3 1伸出於各所對應的接墊2 j與 2外邛,將會減少接觸面積,因此當該矽晶粒與引線框架 材料的熱膨脹與收縮有所差變時,傳導至該晶粒3〇與3工的 應力值亦會減少。 在該等晶粒30與31被固設於接墊21與22之後,晶粒30 的頂部電極將會如習知般地被接線於導銷25與28,而晶粒 31的頂部電極則會被接線於導銷^與”。 請注意現在藉該殼體50乃可獲得更多的晶粒面積,而 不必增加其尺寸。 峒该引線框架會被以習知技術來包封成型一塑膠殼體 5〇如第3圖(虛線)及第4圖所示。該引線框架嗣會被修整, 以除掉在所形成之封裝體一側的端子或導銷、^了與 另一側的導銷24、26、28等之間的接橋。 各導銷23至28皆會突伸穿出該封裝體的側面,而形成 6腳的TSOT式裝置,其分別對應於M〇SFETs 3〇與31之各 V銷D!、D2、G2、Gi、S2、SJ,如第3與4圖所示。所有 的導銷以“1”來標附者係為M〇SFET 3〇的導銷,而以“2,,來 標附者則為M〇SFET31的導銷。請注意不同的導銷亦可依 而要來外部連接,或内部連接而形成該二晶粒之間的不同 連結。 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公贊) (請先閲讀背面之注意事項再填寫本頁) 、^τ— 523888
雖本發明係以其特定實施例來詳細說明,但專業人士 將可易知許多其它的變化、修正與不同用途。因此,最好 本發明係不受於此所揭之具體細節所限,而僅由 範圍來界定。 元件標號對照 20·.·引線框架 21、22…接墊 23、24···銷 25、26…閘極導銷 27、28…源極導銷 30、31··.半導體晶粒 50...殼體
本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)
Claims (1)
- ^ 伸溽的半導體晶粒,及一扁薄 的連接件其係供支撐該半導體晶㈣主要支架;該晶粒 係被設在該連接件頂面並與該頂面以面對面接觸地連 結’該晶粒具有至少-方向的尺寸大於該支撑件的對應 尺寸而使為曰曰粒至少在該方向會部份地伸出於該支撐 件外部。 如申請專利範圍第1頊夕壯 ^貞之衣置,其中該晶粒會向外伸出 於該支撐件的全部頂面區域外部。 其中該晶粒係以焊接來 其中該晶粒係以環氧樹 其中該支撐件係為一弓| 其中該裝置係被包封在 其中該晶粒會向外伸出 其中該晶粒會向外伸出 如申請專利範圍第1項之農置 連結於該支撐件。 如申请專利範圍第1項之裝置 脂黏劑來連結於該支撐件。 如申請專利範圍第1項之裝置 線框架的一片段部份。 如申請專利範圍第1項之裝置 一塑膠封裝體内。 如申請專利範圍第5項之裝置 該支撐件的整個頂面區域外部 如申請專利範圍第6項之裝置 該支撐件的整個頂面區域外部 如申請專利範圍第8項之裝置,其中該支撐件係為— 線框架的一片段部份。 如申請專利範圍第9項之裝置,其中該支撐件包含〜 線框架接墊;該引線框架接墊係被容納於一體掃向延伸 523888 A8 B8 C8 D8 、申請專利範園 部中’該延伸部會突伸穿出該封裝體之壁,而可供外部 連接該封裝體。 一種半導體裝置封裝體,包含一扁平的導電引線框架其 具有至少一引線框架接墊;至少一扁薄的半導體裝置被 擇設在該引線框架接墊上並緊密連結於該接墊;及一塑 膠封襄體包封該引線框架接墊與晶粒;該晶粒會在至少 一方向伸出該引線框架接墊外部,而使該接墊與晶粒因 熱脹冷縮之差變所產生的應力減少。 12.如申請專利範圍第U項之封裝體,其中該晶粒會在全部 各方向伸出該接墊外部。 如申請專利範圍第U項之封裝體,其中該晶粒係為一金 屬氧化物半導體場效應電晶體(MOSFET)。 14·如申請專利範圍第U項之封裝體,其中該引線框架接墊 具有一橫向延伸的一體導銷會突伸穿出該封裝體之壁。 15. 如申請專利範圍第u項之封裝體,乃包含一第二引線框 架接墊於該塑膠封裝體内,及一第二晶粒固設在該第二 接塾上,且該第二晶粒至少有—部份會伸出該第二㈣外部。 16. 如申請專利範圍第15項之封裝體,其中該第一與第二 粒會各在所有方向分別伸出該第—與第二接塾外部。 如申請專利範圍第16項之封裝體,其中該第一與二一 粒皆為MOSFETs 〇 11 (請先閱讀背面,5注意事項再填寫本頁) 訂· t a曰 曰曰 本紙張尺度適财哪標準(⑽)M規格(繼297公楚)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US25547000P | 2000-12-14 | 2000-12-14 | |
US10/002,252 US6433424B1 (en) | 2000-12-14 | 2001-10-26 | Semiconductor device package and lead frame with die overhanging lead frame pad |
PCT/US2001/046676 WO2002049108A1 (en) | 2000-12-14 | 2001-12-06 | Semiconductor device package and lead frame with die overhanging lead frame pad |
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TW523888B true TW523888B (en) | 2003-03-11 |
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Application Number | Title | Priority Date | Filing Date |
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TW090130895A TW523888B (en) | 2000-12-14 | 2001-12-13 | Semiconductor device package and lead frame with die overhanging lead frame pad |
Country Status (6)
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US (1) | US6433424B1 (zh) |
JP (1) | JP3801989B2 (zh) |
CN (1) | CN100423251C (zh) |
AU (1) | AU2002228825A1 (zh) |
TW (1) | TW523888B (zh) |
WO (1) | WO2002049108A1 (zh) |
Cited By (1)
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TWI423417B (zh) * | 2007-09-28 | 2014-01-11 | Renesas Electronics Corp | 半導體裝置 |
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US6927482B1 (en) * | 2003-10-01 | 2005-08-09 | General Electric Company | Surface mount package and method for forming multi-chip microsensor device |
US7602050B2 (en) * | 2005-07-18 | 2009-10-13 | Qualcomm Incorporated | Integrated circuit packaging |
US7274089B2 (en) * | 2005-09-19 | 2007-09-25 | Stats Chippac Ltd. | Integrated circuit package system with adhesive restraint |
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-
2001
- 2001-10-26 US US10/002,252 patent/US6433424B1/en not_active Expired - Lifetime
- 2001-12-06 AU AU2002228825A patent/AU2002228825A1/en not_active Abandoned
- 2001-12-06 WO PCT/US2001/046676 patent/WO2002049108A1/en active Application Filing
- 2001-12-06 CN CNB01820533XA patent/CN100423251C/zh not_active Expired - Fee Related
- 2001-12-06 JP JP2002550316A patent/JP3801989B2/ja not_active Expired - Fee Related
- 2001-12-13 TW TW090130895A patent/TW523888B/zh not_active IP Right Cessation
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TWI423417B (zh) * | 2007-09-28 | 2014-01-11 | Renesas Electronics Corp | 半導體裝置 |
Also Published As
Publication number | Publication date |
---|---|
JP3801989B2 (ja) | 2006-07-26 |
JP2004516654A (ja) | 2004-06-03 |
AU2002228825A1 (en) | 2002-06-24 |
CN100423251C (zh) | 2008-10-01 |
CN1630945A (zh) | 2005-06-22 |
US20020047198A1 (en) | 2002-04-25 |
US6433424B1 (en) | 2002-08-13 |
WO2002049108A1 (en) | 2002-06-20 |
WO2002049108A8 (en) | 2002-11-28 |
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