TW451366B - Power device chip package and method for manufacturing the same - Google Patents

Power device chip package and method for manufacturing the same Download PDF

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Publication number
TW451366B
TW451366B TW089110374A TW89110374A TW451366B TW 451366 B TW451366 B TW 451366B TW 089110374 A TW089110374 A TW 089110374A TW 89110374 A TW89110374 A TW 89110374A TW 451366 B TW451366 B TW 451366B
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Taiwan
Prior art keywords
electrode
conductive frame
wafer
chip
patent application
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TW089110374A
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Chinese (zh)
Inventor
Shr-Guan Chen
Guang-Han Lin
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Gen Semiconductor Of Taiwan Lt
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Priority to TW089110374A priority Critical patent/TW451366B/en
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Publication of TW451366B publication Critical patent/TW451366B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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    • H01—ELECTRIC ELEMENTS
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/4005—Shape
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The present invention relates to a power device chip package and a method for manufacturing the same. The power device chip (11) has a first surface (111) including a first electrode (10) and a second electrode (20), and a second surface (112) including a third electrode (30). The first electrode (10) and second electrode (20) of the chip (11) are electrically connected to a first portion (151) and a second portion (152), respectively, of a first leadframe (15). The first leadframe (15) extends from the place over the first electrode (10) and second electrode (20) of the chip to the place outside the chip. The third electrode (30) of the chip is electrically connected to a second leadframe (16), and the second leadframe (16) extends from the place over the third electrode (30) of the chip to the place outside the chip. The present invention provides a power device chip package in which the die area can be utilized efficiently and the capability of heat dissipation is excellent. In addition, the present invention has the advantages of easy fabrication and high productivity.

Description

A7 451366 五、發明說明（1 ) 發明領域 本發明係有關一種功率元件晶片封裝及製造方法，特別 是關於一種功率金氧半導髏場效電晶體（p〇WER mosfet)積體電路之封裝及製造方法，其可以有效利用 晶片面積、且具有相當良好的散熱性。用本發明所完成之 晶片封裝，可以相當接近晶片尺寸封scale package, CSP)之封裝方式。 發明皆景 為符合目前電腦、通訊及消費市場小型化以及可攜性的 需求，半導體晶片尺寸日益縮小、而線路的設計也曰趨複 雜。因此’半導體晶片的封裝技術也必須隨之發生變革， 晶片封裝不只需符合更小、更快、更便宜的要求，同時也 必須有更佳的散熱能力以及穩定度等優點。傳統的晶片的 封裝技術中，最常用的三種分別為：引線焊接（wire bonding)，帶狀自動焊接（tape automated b〇nding， TAB)以及倒裝晶片（fiip_cijip)等方式。上述方式各有 其優缺點’然而在有效運用晶片面積的考量下，已逐漸發 展出晶片尺寸封裝（chip scale package，以下簡稱CSP) 之封裝方式。CSP的主要理念在於提供一種封裝尺寸縮小 至幾乎是一裸晶尺寸大小的封裝，且其穩定度較倒裝晶片 更為優異。典型的CSP封裝可以達到晶片面積的15倍左 右。 本發明係關於功率元件晶片的封裝及其製造方法。習知 的功率元件封裝，以一功率金氧半導體場效電晶體之封裝A7 451366 V. Description of the invention (1) Field of the invention The present invention relates to a power element chip packaging and manufacturing method, and more particularly to a power metal oxide semiconductor field effect transistor (POWER mosfet) integrated circuit package and A manufacturing method which can effectively utilize a chip area and has a relatively good heat dissipation property. The chip package completed by the present invention can be quite close to the package mode of the chip size package (CSP). All inventions To meet the current miniaturization and portability requirements of the computer, communications, and consumer markets, the size of semiconductor chips is shrinking, and the design of circuits is becoming more complex. Therefore, the packaging technology of 'semiconductor wafers must also be changed. Chip packages need not only meet the requirements of smaller, faster, and cheaper, but also have better heat dissipation capabilities and stability. In traditional chip packaging technology, the three most commonly used methods are: wire bonding, tape automated bonding (TAB), and flip chip (fiip_cijip). The above methods each have their own advantages and disadvantages. However, in consideration of effective use of the chip area, a chip scale package (hereinafter referred to as CSP) packaging method has been gradually developed. The main idea of CSP is to provide a package with a package size reduced to almost a die size, and its stability is better than flip chip. A typical CSP package can reach about 15 times the chip area. The present invention relates to a package of a power element wafer and a manufacturing method thereof. The conventional power device package is a power metal oxide semiconductor field effect transistor package.

0：\62\62449.D〇qwCK 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公》 \sf --In —--I I I i — — — — —— ^iln . - (請先閲讀背面之注意事項再填寫本頁) fr 經濟部智慧財產局員工消費合作社印製 -4 451366 A7 經濟部智慧財產局員工消费合作社印製 Β7 五、發明說明（2 ) 為例，如美國專利第5,767,567號案所揭示者。請參照圖 式ΙΑ、1B及1C，圖ία為一功率金氧半導體場效電晶體之 凡件電路不意圖。該元件為一N通道増強模式（Nchannel enhancement m〇de)的金氧半導體場效電晶體，其中該 電晶體的第一電極1〇(即閘極，gate)係電氣連接至接腳 4(ριη 4) ’第二電極2〇(即源極，s〇urce)係連接至接腳 l-3(pins 1-3)，而第三電極3〇(即汲極，drain)則電氣 連接至接卿5-8(pins5-8)。參看圖1B所示之該功率晶片 接線頂部視圖，其中功率元件晶片1 1呈一長方形，該晶片 11具有一閘極10與一源極2〇位於該晶片的同一表面，而 沒極3 0則位於與閘極丨〇與源極2 〇所在晶片表面對侧的另 一表面。由於功率元件必須容許極大的電流通過源極2〇與 汲極30，因此可以看出源極2〇與汲極之面積已相當近 似於該晶片1 1的尺寸。至於閘極1 〇，作為一個控制電極本 身並不會有大電流流過，所以由圖1 B可以看出閘極1 〇只 占晶片表面積的一小部分。習知功率金氧半導體場效電晶 艘封裝係應用兩片金屬導電框架（lead frame，通常是銅 導電框架）。頂部導電框架13(top leadfrarne)係透過導 線1 2分別與源極2 〇、及閘極〗〇互相連接，而分別形成接 腳I-3、及接腳4。另外，底部導電框架14(b〇u〇m lead frame)係直接（未透過導線）與晶片底部表面的汲極 30互相連接’而形成接腳5-8。 習知功率金氧半導體場效電晶想之晶片封裝之一個特 徵’在於其連接源極2〇及閘極丨〇之導線12(wires 〇r 0:\62^2449 D〇C\WCIC . C _ 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 2听公釐〉 I ------- ----^ i 1---I— ---111 . - {請先w讀背面之注意事項再填窝本頁) 451366 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（3 ) lead wires)焊接的方式，如圖1B所示其係使用引線焊接 (wire bonding)的方法將許多導線12焊接以連接源極20 及閘極10至該頂部導電框架13。同樣的，源極20有大電 流流過故需要許多的導線12以供連接之用，而閘極1〇用一 根導線連接則已足夠。現參照圖1 C，由該習知功率金氧半 導體場效電晶體之晶片封裝外觀示意圖可看出，晶片、各 導電框架、各接腳以及導線之外觀，特別值得注意的是用 以連接閘極10與接脚4的一根導線12，至於連接源極20及 接腳1-3的許多導線在圖1C中則已被覆蓋而未顯示。 習知的功率金氧半導體場效電晶體之晶片封裝方法具有 許多缺點。首先，由於是採用引線焊接的方法，所以晶片 面積的利用效率不佳，無法達成前述晶片尺寸封裝（CSP) 之尺寸縮小的功效》此外，由於頂部導電框架13之面積不 大，且其係利用引線焊接來與晶片相連接，故封裝的散熱 性不佳，而此為功率晶片致命的缺點。最後，由於習知的 封裝方式需焊接許多根的引線，其製程相當繁複，生產效 率很低，且該晶片之閘極只透過一根導線與接腳連接，穩 固性亦差。因此，有需要研究出一種既能具備CSP之概 念、散熱性良好且兼具製作效率及穩固性之功率元件晶片 封裝及製造方法。本發明提供此一需求。 發明簡述 本發明的一目的，在於提供一種有效利用晶片面積的功 率元件晶片封裝及其製造方法。 本發明的另一目的，在於提供一種散熱性優良之功率元 _______ •一 ' 0:V62\62449.P〇aWCK - 6 · (請先閲讀背面之注意事項再填寫本頁)0: \ 62 \ 62449.D〇qwCK This paper size is applicable to China National Standard (CNS) A4 (210 X 297) \ sf --In —-- III i — — — — — ^ iln.-(Please (Please read the notes on the back before filling this page) Disclosed in No. 5,767,567. Please refer to Figures IA, 1B, and 1C. Figure αα is a circuit of a power metal oxide semiconductor field effect transistor. This component is an N-channel enhancement mode (Nchannel enhancement mode). de) metal-oxide-semiconductor field-effect transistor, wherein the first electrode 10 (ie, the gate) of the transistor is electrically connected to pin 4 (ριη 4) 'the second electrode 20 (ie, the source, source) is connected to pins l-3 (pins 1-3), and the third electrode 30 (ie, drain) is electrically connected to pins 5-8 (see Figure 1B). The top view of the power chip wiring shown, wherein the power element chip 11 is a rectangle, the chip 11 has a gate electrode 10 and The source 20 is located on the same surface of the wafer, while the non-electrode 30 is located on the other side of the wafer opposite to the gate where the gate and source 20 are located. Because the power element must allow a large current to pass through the source 2 〇 and the drain electrode 30, so we can see that the area of the source 20 and the drain electrode is quite similar to the size of the wafer 11. As for the gate electrode 10, as a control electrode itself, no large current flows, Therefore, it can be seen from Figure 1B that the gate electrode 10 occupies only a small part of the surface area of the wafer. The conventional power metal-oxide semiconductor field effect transistor package uses two metal conductive frames (lead frames, usually copper conductive frames). The top conductive frame 13 (top leadfrarne) is connected to the source electrode 20 and the gate electrode 12 through wires 12 to form pins I-3 and 4 respectively. In addition, the bottom conductive frame 14 ( b〇u〇m lead frame) is connected directly (without the wires) to the drain 30 on the bottom surface of the chip to form pins 5-8. One of the chip packages known in the field of power metal-oxide semiconductor field effect transistors Characteristic 'lies in its connection source 20 and gate丨 〇 of the wire 12 (wires 〇r 0: \ 62 ^ 2449 D〇C \ WCIC. C _ This paper size applies to the Chinese National Standard (CNS) A4 specification (21〇χ 2 mm) I ----- ----- ^ i 1 --- I-- --- 111.-(Please read the precautions on the back before filling in this page) 451366 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Description of the invention (3) The method of lead wires welding, as shown in FIG. 1B, uses a wire bonding method to weld a plurality of wires 12 to connect the source 20 and the gate 10 to the top conductive frame 13. Similarly, a large current flows through the source electrode 20 and therefore many wires 12 are needed for connection, and the gate electrode 10 is sufficient to connect with one wire. Referring now to FIG. 1C, the appearance of the chip package of the conventional power metal oxide semiconductor field effect transistor can be seen. The appearance of the chip, each conductive frame, each pin, and the wire is particularly noteworthy for connecting the gate. One wire 12 of the electrode 10 and the pin 4, and many wires connecting the source electrode 20 and the pins 1-3 are covered and not shown in FIG. 1C. The conventional wafer packaging method of a power MOSFET has many disadvantages. First, because the wire bonding method is used, the utilization efficiency of the chip area is not good, and the aforementioned effect of reducing the size of the chip size package (CSP) cannot be achieved. In addition, because the area of the top conductive frame 13 is not large, and it is used Wire bonding is used to connect to the chip, so the heat dissipation of the package is not good, which is a fatal disadvantage of power chips. Finally, because the conventional packaging method requires soldering many leads, the manufacturing process is quite complicated, the production efficiency is very low, and the gate of the chip is connected to the pin through only one wire, which also has poor stability. Therefore, there is a need to develop a power device chip packaging and manufacturing method that not only has the concept of CSP, has good heat dissipation, but also has manufacturing efficiency and stability. The present invention provides this need. SUMMARY OF THE INVENTION An object of the present invention is to provide a chip package for a power device which effectively utilizes a chip area and a manufacturing method thereof. Another object of the present invention is to provide a power element with excellent heat dissipation _______ • 1 '0: V62 \ 62449.P〇aWCK-6 · (Please read the precautions on the back before filling this page)

• Λ 裝-----丨—訂-----—II 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 461366 經濟部智慧財產局員工消费合作社印製 A7 1 11 ------- B7 五、發明說明（4 ) "-- 件晶片封裝及其製造方法。 本發明的又一目的，在於提供一簠製程簡化且能大幅 提高封裝之生產效率之功率元件晶片封裝及其製造方法。 本發明的再-目的’在於提供一種可以容易延伸為多晶 片模組（multiple-chip㈣心，MCM)之封裝裝置的: 率元件晶片封裝及其製造方法。 依據本發明之一種功率元件晶片封裝之方法與裝置其 中該晶片具有一第一表面含有該晶片之第一電極與第二電 極，以及一第二表面含有該晶片之第三電極。將一第一導 電框架之一第一部分電氣連接至該第一電極，該第一導電 框架之一第二部分電氣連接至該功率元件之第二電極以 及將一第二導電框架電氣連接至該功率元件之第三電極； 其中該第一導電框架係自該第一電極與該第二電極處向晶 片外延伸’且該第二導電框架係自該第三電極處向晶片外 延伸。 由於本發明上述之功率元件晶片封裝並不採用引線焊 接’所以晶片面積的利用效率極高，可以有趨近晶片尺寸 封裝（CSP)的功效。由於本發明之功率元件晶片封裝，其 第一導電框架的面積很大，故封裝的散熱性極佳。同時本 發明之功率元件晶片封裝方法，其製程簡化、生產效率極 高，而且穩固性亦佳。 依據本發明之一種功率元件晶片封裝之方法與裝置，由 於其中該第一導電框架及第二導電框架可以向晶片外延 伸，而至少三者其中之一可進一步與其他晶月之電極電氣 —〇^\fi2449.D〇rvwrif______________- 7 - _ ___ 本紙張尺度適用尹國國家標準（CNS)A4規格（210 X 297公釐） - (請先《讀背面之注意事項再填寫本頁> 451 366 經濟部智慧財產局員工消费合作社印製 A7 B7 五、發明說明（5 ) 連接，如此可以容易形成多晶片模組（MCM)之封裝裝置。 為使本發明之技術内容及特點更易於瞭解，茲藉由之較 佳實施例，配合圖式說明如下》 圖示簡述 本發明將依照後附圖示來說明，其中： 圖1Α係一功率金氧半導體場效電晶體之元件電路示意 131 囲， 圖1 Β係一習知功率金氧半導體場效電晶體之晶片接線組 裝頂部視圖； 圖1C係一習知功率金氧半導體場效電晶體之晶片封裝外 觀示意圖； 圖2Α係係根據本發明之較佳實施例的功率金氧半導體場 效電晶體之晶片組裝側視圖； 圖2Β係係根據本發明之較佳實施例的功率金氧半導體場 效電晶體之晶片組裝頂部視圖； 圖2C係係根據本發明之較佳實施例的功率金氧半導體場 效電晶體之晶片組裝底部視圖； 主要元件符號說明 1-8 接腳（p iη) II 功率元件晶片 III 功率元件晶片第一表面 1 12 功率元件晶月第二表面 10 第一電極 20 第二電極 _Q:\62N62449.D〇qwaC_- 8 -_ 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐) ---II ----if 裝------ 訂-----I ni^cl - - (請先Μ讀背面之注意事項溽填寫本I) 4 513 6 6 A7 B7 五、發明說明（6 ) 30 第三電極 12 導線（wires or lead wires) 13 頂部導電框架（top leadframe) 14 底部導電框架（bottom leadframe) 15 第一導電框架（first leadframe) 15 1 第一部分（first portion) 1 52 第二部分（second portion) 1 53 導電接點（conductive contacts) 1 6 第一導電框架（s e c ο n d 1 e a d f r a m e ) 163 導電接點（conductive contacts) 發明詳述 以下將參考圊示說明本發明的實施例。圖示中相同的元 件具有相同的參考符號。 參看圖2A ’圊2A係根據本發明之一較佳實施例的功率 金氧半導趙場效電晶體之晶片封裝側視圖，其中該功率元 件晶片11具有一第一表面111及一第二表面。該第一 表面111與第一導電框架15電氣連接，而第二表面112係 與一第二導電框架16電氣連接。將導電框架與晶片連接的 方式，主要為焊接（利用焊錫）或是利用導電膠來黏著等。 此外’圖2A中可以看出在本發明此一較佳實施例中，第一 導電框架15與第二導電框架丨6上各有複數個導電接點153 與163(conductive contacts)»導電接點}53係用以與 晶片11之第一表面111直接接觸，而導電接點163係用以 與第二表面1 12直接接觸。 0:\&2\62449.D〇gwCK _ 9 _ 本紙張尺度遇用中國國家標準（CNS)A4規格（210 X 297公爱） (锖先閱讀背面之注意事項再填寫本頁) 裝 ii — 丨— 訂 i! 經濟部智慧財產局員工消费合作社印製 經濟部智慧財產局負工消費合作社印製 A7 __________B7___ 五、發明說明（7 ) 參看围2B，為根據本發明該較佳實施例的功率金氧半導 體場效電晶體晶片組裝之頂部視圖，圖23揭示本發明主要 特徵之一的第一導電框架15。該第一導電框架15含有—第 一部分151(first P〇rti〇n)以及一第二部分 152(sec〇nd portion)。第一部分151係電氣連接至晶片n之一第一電 極1 0 (或閘極），而第二部分丨5 2則電氣連接至該晶片之一 第二電極20(或源極）。由前述的討論知道，源極之面積遠 大於閘極之面積’所以’在晶片i 1上方的第一部分〗5 1的 面積遠小於在晶片i 1上方的第二部分丨5 2之面積。較佳 的，該第一導電框架15的材質為銅，而導電框架圖案的形 成主要是經由沖壓或蝕刻的方式β而第一導電框架15向晶 片外延伸的部分則是用以形成接腳，其步驟為將該延伸部 分經過二次折彎的手續（參見圖2 Α較為清楚），再將該延伸 部分延著aa1線切割，則可以形成圊1 c中的四個接腳（Jjins 1 - 4 ) 〇 比較本發明之圊2B以及習知技藝之圖的封裝方式， 可以清楚看出本發明的優點。由於本發明晶片封裝並不採 用引線焊接’所以晶片面積的利用效率極高，可以有相當 趨近晶片尺寸封裝（CSp)。另一方面，由於本發明之功率 το件晶片封裝’其第一導電框架15的面積很大，因此封裝 的散熱性遠較習知技藝為佳。同時本發明並不需要焊接許 多根的引線’因此製程簡化，易於自動化而生產效率極 高，而且穩固性亦較佳。 圖2C係係根據本發明該較佳實施例的功率金氧半導體場 O:\62tf3449.DOawCK 1〇 本&尺度適財關家標準（CNS)A4規格⑽χ 297公- ---II------—^1- ^---»111! ---— ml^ci - - (锖先閱讀背面之注意Ϋ項再填寫本頁) 451366 A7 _______ B7 _ 五、發明說明（8 ) (請先W讀背面之注意事項再填寫本頁> 效電晶體晶片組裝之底部視圓❶該第二導電框架16係電氣 連接至晶片11之一第三電極3〇(或汲極），第三電極之面積 近似於晶片的面積。如同該第一導電框架15，該第二導電 框架16的材質可以為銅’而導電框架圖案主要是經由沖壓 或蝕刻的方式而形成。而第二導電框架16向晶片外延伸的 部分則經過折彎及切割的手續用以形成接腳。圖2 C中的實 施例是形成四個接腳（pins 5-8)。 依據本發明之另一個實施例（囷未顯示），若將圖2A、 2B、2C中第一導電框架15的第一部分151、第二部分 152或第二導電框架16 ’三者中的至少一個，向晶片外延 伸而進一步與其他晶片之電極電氣連接，如此則可以形成 多晶片模組（MCM)之封裝裝置。 至於其後封裝的各必要手續，由於並非本發明之特徵， 故在此不予討論。然而’熟悉本行技藝人士，在瞭解上述 本發明之技術内容後，當可容易完成一功率元件晶片的封 裝。 經濟部智慧財產局貝工消费合作社印製 依據本發明之功率元件晶片封裝方法，晶片面積的利用 效率極高’且導電框架的面積很大，故封裝的散熱性極 佳。同時本發明之功率元件晶片封聢方法，其製程易於自 動化，可大幅提高生產效率。另外，本發明之封裝穩固性 較佳’同時富有彈性，可以擴充成為多晶片模組之封裝。 本創作之特點及技術内容已充分揭示如上，任何熟於本 項技藝之士可依據本創作之揭示及教示而作各種不背離本 創作精神之替換或修飾’因此本創作之保護範圍不應限於 Q:\62\62449.D〇awrK__ _ 1 1 - 私紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） 451 366 A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明（9 ) 所揭示之實施例，而應涵蓋這些替換及修飾。• Λ Installation ----- 丨 —Order -----— II This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 461366 Printed by A7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs 1 11 ------- B7 V. Description of the Invention (4) "-A chip package and its manufacturing method. Still another object of the present invention is to provide a power device chip package and a manufacturing method thereof that simplify the manufacturing process and can greatly improve the production efficiency of the package. The re-objective of the present invention is to provide a high-density component chip package and a manufacturing method thereof that can be easily extended to a multi-chip module (MCM) packaging device. A method and apparatus for packaging a power element wafer according to the present invention, wherein the wafer has a first electrode including a first electrode and a second electrode on the wafer, and a third electrode including a second surface on the wafer. Electrically connecting a first portion of a first conductive frame to the first electrode, electrically connecting a second portion of a first conductive frame to a second electrode of the power element, and electrically connecting a second conductive frame to the power A third electrode of the element; wherein the first conductive frame extends outward from the wafer from the first electrode and the second electrode, and the second conductive frame extends outward from the wafer from the third electrode. Since the above-mentioned power device chip package of the present invention does not use wire bonding, the utilization efficiency of the chip area is extremely high, and the effect of approaching the chip size package (CSP) can be achieved. Since the power element chip package of the present invention has a large area of the first conductive frame, the heat dissipation of the package is excellent. At the same time, the power device chip packaging method of the present invention has a simplified manufacturing process, extremely high production efficiency, and excellent stability. According to a method and device for packaging a power device chip according to the present invention, since the first conductive frame and the second conductive frame can extend outside the chip, and at least one of them can further be electrically connected to other electrodes of the crystal moon— ^ \ fi2449.D〇rvwrif ______________- 7-_ ___ This paper applies Yin National Standard (CNS) A4 specification (210 X 297 mm)-(Please read the "Cautions on the back side before filling out this page"> 451 366 Printed by A7 B7 of the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. The description of the invention (5) is connected so that a multi-chip module (MCM) packaging device can be easily formed. In order to make the technical content and characteristics of the present invention easier to understand, With a preferred embodiment, the description with the drawings is as follows. The diagram briefly describes the present invention will be explained in accordance with the following drawings, in which: Figure 1A is a schematic diagram of the element circuit of a power metal oxide semiconductor field effect transistor. Figure 1B is a top view of a conventional power metal oxide semiconductor field effect transistor wafer assembly; Figure 1C is a conventional power metal oxide semiconductor field effect wafer package appearance 2A is a side view of a wafer assembly of a power MOSFET according to a preferred embodiment of the present invention; FIG. 2B is a power MOSFET according to a preferred embodiment of the present invention; Top view of the wafer assembly of the wafer; Figure 2C is a bottom view of the wafer assembly of the power metal-oxide semiconductor field effect transistor according to a preferred embodiment of the present invention; the description of the main component symbols 1-8 pin (p iη) II power component wafer III The first surface of the power element wafer 1 12 The second surface of the power element crystal 10 The first electrode 20 The second electrode _Q: \ 62N62449.D〇qwaC_- 8 -_ This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) --- II ---- if equipment ------ order ----- I ni ^ cl--(please read the notes on the back first, fill in this I) 4 513 6 6 A7 B7 V. Description of the invention (6) 30 Third electrode 12 wires or lead wires 13 top conductive frame 14 bottom conductive frame 15 first conductive frame 15 first conductive frame 15 1 first portion 1 52 second p ortion) 1 53 conductive contacts 1 6 first conductive frame (s e c ο n d 1 e a d f r a m e) 163 conductive contacts DETAILED DESCRIPTION OF THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to illustrations. Identical components in the illustration have the same reference symbols. 2A is a side view of a chip package of a power metal-oxide semiconductor field-effect transistor according to a preferred embodiment of the present invention, wherein the power element wafer 11 has a first surface 111 and a second surface. . The first surface 111 is electrically connected to the first conductive frame 15, and the second surface 112 is electrically connected to a second conductive frame 16. The method of connecting the conductive frame to the chip is mainly soldering (using solder) or using conductive adhesive for adhesion. In addition, it can be seen in FIG. 2A that in this preferred embodiment of the present invention, the first conductive frame 15 and the second conductive frame 丨 6 each have a plurality of conductive contacts 153 and 163 (conductive contacts) »conductive contacts. } 53 is used for direct contact with the first surface 111 of the wafer 11, and the conductive contact 163 is used for direct contact with the second surface 112. 0: \ & 2 \ 62449.D〇gwCK _ 9 _ This paper size meets China National Standard (CNS) A4 specifications (210 X 297 public love) (锖 Please read the precautions on the back before filling this page) — 丨 — Order i! Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by A7 __________B7___ V. Description of the Invention (7) Refer to Section 2B, according to A top view of a power metal oxide semiconductor field effect transistor wafer assembly. FIG. 23 discloses a first conductive frame 15 which is one of the main features of the present invention. The first conductive frame 15 includes a first portion 151 (first Portion) and a second portion 152 (secon portion). The first part 151 is electrically connected to one of the first electrodes 10 (or gates) of the chip n, and the second part 5 2 is electrically connected to one of the second electrodes 20 (or sources) of the chip. From the foregoing discussion, it is known that the area of the source is much larger than the area of the gate ', so the area of the first part 51 above the wafer i 1 is much smaller than the area of the second part 5 52 above the wafer i 1. Preferably, the material of the first conductive frame 15 is copper, and the formation of the conductive frame pattern is mainly by a method of stamping or etching β, and the portion of the first conductive frame 15 extending outside the wafer is used to form a pin. The steps are the procedure of second bending the extension (see Figure 2A), and then cutting the extension along the line aa1 to form four pins in 圊 1 c (Jjins 1- 4) 〇 Comparing the packaging method of 2B of the present invention and the drawing of the conventional art, the advantages of the present invention can be clearly seen. Since the chip package of the present invention does not use wire bonding, the utilization efficiency of the chip area is extremely high, and a chip size package (CSp) can be approximated. On the other hand, since the power το chip package of the present invention has a large area of the first conductive frame 15, the heat dissipation of the package is much better than that of conventional techniques. At the same time, the present invention does not need to solder many leads, so the process is simplified, it is easy to automate, the production efficiency is extremely high, and the stability is also good. Fig. 2C is a power metal-oxide semiconductor field O: \ 62tf3449.DOawCK according to the preferred embodiment of the present invention. The & standard suitable financial standards (CNS) A4 specification ⑽χ 297 public---- II- ----— ^ 1- ^ --- »111! ----- ml ^ ci--(锖 Please read the note on the back before filling in this page) 451366 A7 _______ B7 _ V. Description of the invention (8) (Please read the precautions on the back before filling in this page> The bottom view of the wafer assembly of the FET is round. The second conductive frame 16 is electrically connected to one of the third electrodes 30 (or the drain) of the chip 11, The area of the third electrode is similar to the area of the wafer. Like the first conductive frame 15, the material of the second conductive frame 16 can be copper, and the conductive frame pattern is mainly formed by stamping or etching. The second conductive The portion of the frame 16 extending outward from the wafer is bent and cut to form pins. The embodiment in FIG. 2C is formed with four pins (pins 5-8). According to another embodiment of the present invention (囷 Not shown), if the first part 151, the second part 152, or the second guide of the first conductive frame 15 in FIG. 2A, 2B, 2C At least one of the electrical frames 16 'extends out of the wafer and is further electrically connected to the electrodes of other wafers, so that a multi-chip module (MCM) packaging device can be formed. As for the necessary procedures for subsequent packaging, since It is not a feature of the present invention, so it will not be discussed here. However, 'familiar skilled artisans, after understanding the technical content of the present invention, can easily complete the packaging of a power component chip. Intellectual Property Bureau of the Ministry of Economic Affairs Shellfish Consumption The cooperative prints the power device chip packaging method according to the present invention, the utilization efficiency of the chip area is extremely high, and the area of the conductive frame is large, so the heat dissipation of the package is excellent. At the same time, the power device chip sealing method of the present invention has a manufacturing process It is easy to automate and can greatly improve production efficiency. In addition, the package of the present invention has better stability and is flexible, and can be expanded into a multi-chip module package. The characteristics and technical content of this creation have been fully disclosed above, and anyone familiar with this According to the disclosure and teaching of this creation, a person of skill can make various substitutions without departing from the spirit of this creation. Replacement or modification 'Therefore, the scope of protection of this creation should not be limited to Q: \ 62 \ 62449.D〇awrK__ _ 1 1-The private paper size applies the Chinese National Standard (CNS) A4 specification (21〇x 297 mm) 451 366 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. The embodiment disclosed in the description of invention (9) shall cover these substitutions and modifications.

O:\62\62449OOOWCK -12- (請先閱讀背面之注意事項再填寫本頁) 裝--------訂----- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）O: \ 62 \ 62449OOOWCK -12- (Please read the precautions on the back before filling out this page) Loading -------- Order ----- This paper size applies to China National Standard (CNS) A4 specifications ( 210 X 297 mm)

Claims (1)

451366 A6 B8 C8 -----—___— D8 六、申請專利範圍 1- 一種功率元件晶片封裝裝置，包含： 一功率70件晶片（11)，其具有一第一表面（111)含有 該晶片之第一電極（10)與第二電極（2 0)，以及-第二表 面（112)含有該晶片之第三電極（3〇); 第一導電框架（15) ’其具有第一邵分（151)，該第 一部分（151)與第一電極（1〇)電氣連接，並自該第一電 極（1 〇)處向晶片外延伸；以及第二部分（丨5 2 )，該第二 部分（152)與第二電極（2〇)電氣連接，並自該第二電極 (20)處向晶片外延伸；以及 一第二導電框架（16)，其與第三電極（3〇)電氣連接， 並自該第三電極（3〇)處向晶片外延伸。 2. 如申請專利範圍第1項的封裝裝置，其中該功率元件晶 月為一金氧半導體場效電晶體（MOSFET)晶片。 3. 如申請專利範圍第1項的封裝裝置，其中該晶片之第一 電極’第二電極與第三電極分別是一閘極（gate)，源極 (drain)與汲極（source)。 4. 如申請專利範圍第1項的封裝裝置，其中該第一導電框 架及該第二導電框架為銅導電框架。 5. 如申請專利範圍第1項的封裝裝置，其中該第一導電框 架之第一部分向晶片外延伸，進一步形成該第一電極之 接腳。 6 .如申請專jjp圍第5項的封裝裝置，該第一電極之接腳 數目為一 7,如申請專]圍第1項的封裝裝置，其中該第一導電框 O:\62\62449,D0C\WCK ， - 10 * 本紙張尺度逋用中國國家揉率（CNS > A4规格（210X297公釐1 ~~ (請先聞讀背面之注意事項再填寫本頁) 訂 .4 經濟部智慧財產局員工消費合作社印製 4S1366 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範囷 架之第二部分向晶片外延伸，進一步形成該第二電極之 接腳》 8. 如申請專利範圍第7項的封裝裝置，該第二電極之接腳 數目為三個。 9. 如申請專利範圍第i項的封裝裝置，其中該第二導電框 架向晶片外延伸，進一步形成該第三電極之接腳。 10. 如申請專利範圍第9項的封裝裝置，該第三電極之接脚 數目為四個β 11. 如f請專利範圍第1項的封裝裝置，其中該第一導電框 架之第一部分，第二部分以及第二導電框架向晶片外延 伸，且至少三者其中之一進一步與其他晶片之電極電氣 連接’以形成多晶片模組（MCM)之封裝裝置。 12. 如申請專利範圍第i項的封裝裝置，其申該第一導電框 架之第一部分上包含一用以與該第一電極電氣連接之導 電接點。 13. 如申請專利範圍第〗項的封裝裝置，其中該第一導電框 架之第二部分上包含複數個用以與該第二電極電氣連接 之導電接點（153)。 14. 如申請專利範圍第i項的封裝裝置，其中該第二導電框 架上包含複數個用以與該第三電極電氣連接之導電接點 (163 卜 15. —種功率元件晶片封裝之裳造方法，用以封裝一功率 元件晶片（11)，該晶片具有：一第一表面（ιη)，其含 有該晶片之第一電極（10)與第二電極（20);以及—第 〇A62\S2449.D〇awCK - 14 " 本紙張认適财關家標準（CNS ) ( 2〖GX297公兼） ----- --------d------IT------A - (請先W讀背面之注意事項再填寫本頁) Λ8 ΒΒ C8 OS 六、申請專利範園 二表面（112)，其含有該晶片之第三電極（3〇)，該方法 包含以下步驟： 將一第一導電框架（15)之一第一部分（151)電氣連接 至該晶月之第一電極（10)，並將該第一導電框架（15)之 一第二部分（152)電氣連接至該晶片之第二電極（2 ， 並將第一導電框架（15)自該晶片之第一電極（1〇)與第二 電極（2 0 )處向晶片外延伸；以及 將一第二導電框架（16)電氣連接至該晶片之第三電極 (30)，且將該第二導電框架（16)自該晶片之第三電極 (3 0 )處向晶片外延伸。 16. 如申請專利範圍第15項的製造方法，尚包含將該第一 導電框架之第一部分向晶片外延伸，進一步形成該第一 電極之接腳的步驟。 17. 如申請專利範圍第15項的製造方法，尚包含將該第一 導電框架之第二部分向晶片外延伸，進—步形成該第二 電極之接腳的步驟。 18. 如申請專利範圍第15項的製造方法，尚包含將該第二 導電框架向晶片外延伸’進一步形成該第三電極之接腳 的步驟。 19. 如申請專利範圍第15項的製造方法，尚包含將該第— 導電框架之第一部分，第二部分以及第二導電框架向晶 片外延伸，且進一步電氣連接至少三者其中之—到其他 晶片之電極’以形成多晶片模組（MCM)的步驟。 20. 如申請專利範圍第15項的製造方法，尚包含在該第一 O:\62\62449-DOC\WCK _ 1 5 _ 本紙張又度逍用宁國國家揉牟（CNS ) A4規格（210 X 297公釐） --------裝-- •- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 451366 A8 B8 C8 D8 六、申請專利範圍 導電框架之第一部分上形成一用以蛊 、該第一電極電麁邊 接之導電接點的步驟。 既連 21. 如申請專利範圍第15項的製造方 ’尚包含在該第— 導電框架之第二部分上形成複數個用以與該第二電極電 氣連接之導電接點（153)的步驟。 22. 如申請專利範圍第15項的製造方法，尚包含在該第二 導電框架上形成複數個用以與該第三電極電氣連接之導 電接點（1 6 3 )的步驟。 (請先聞讀背面之注意事項再填寫本頁) .裝· 經濟部智慧財產局員工消費合作社印製 0:\«M2449.D〇aWCK 16- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）451366 A6 B8 C8 -----—___— D8 6. Scope of Patent Application 1-A power device chip packaging device including: a power 70 chip (11) with a first surface (111) containing the chip The first electrode (10) and the second electrode (20), and the second surface (112) contains the third electrode (30) of the wafer; the first conductive frame (15) 'which has a first component (151), the first part (151) is electrically connected to the first electrode (10), and extends from the first electrode (10) to the outside of the wafer; and the second part (5, 2), the second The part (152) is electrically connected to the second electrode (20) and extends outside the wafer from the second electrode (20); and a second conductive frame (16) is electrically connected to the third electrode (30) Are connected and extend from the third electrode (30) to the outside of the wafer. 2. For the package device according to item 1 of the patent application scope, wherein the power element crystal is a metal oxide semiconductor field effect transistor (MOSFET) chip. 3. For example, the package device of the scope of patent application, wherein the first electrode ', the second electrode and the third electrode of the chip are a gate, a drain, and a source, respectively. 4. The packaging device according to item 1 of the patent application, wherein the first conductive frame and the second conductive frame are copper conductive frames. 5. The packaging device according to item 1 of the patent application scope, wherein the first portion of the first conductive frame extends outward from the wafer to further form the pins of the first electrode. 6. If you apply for the packaging device of the 5th item of the JJP, the number of pins of the first electrode is one, and if you apply for the packaging device of the 1st item, the first conductive frame O: \ 62 \ 62449 , D0C \ WCK ，-10 * This paper size is based on China's national kneading rate (CNS > A4 size (210X297 mm 1 ~~ (Please read the precautions on the back before filling this page)) Order. 4 Ministry of Economy Wisdom Printed by the Consumer Cooperative of the Property Bureau 4S1366 A8 B8 C8 D8 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 6. The second part of the patent application fan frame is extended outside the chip to further form the pin of the second electrode. 8. For example, the number of pins of the second electrode is three for the package device of the scope of patent application. 9. For the package device of the scope i of the patent application, the second conductive frame is extended to the outside of the wafer to further form the package. Pins of the third electrode. 10. If the package device of the ninth scope of the patent application is applied, the number of pins of the third electrode is four β 11. If f, the package device of the first scope of the patent application, wherein the first The first part and the second part of the conductive frame And the second conductive frame extends outside the wafer, and at least one of them is further electrically connected with the electrodes of other wafers to form a multi-chip module (MCM) packaging device. The device includes that the first part of the first conductive frame includes a conductive contact for electrically connecting with the first electrode. 13. The packaging device according to item 1 of the patent application scope, wherein the first conductive frame The second part includes a plurality of conductive contacts (153) for electrically connecting with the second electrode. 14. For a package device in the scope of application for item i, wherein the second conductive frame includes a plurality of contacts for connecting with the Conductive contact for the third electrode electrical connection (163.15. A method for packaging a power device chip, for packaging a power device chip (11), the chip has: a first surface (ιη), which contains The first electrode (10) and the second electrode (20) of the wafer; and—the 〇A62 \ S2449.D〇awCK-14 " This paper is recognized as a financial standard (CNS) (2 〖GX297) ----- -------- d ------ IT ------ A-(Please read the precautions on the back before filling in this page) Λ8 ΒΒ C8 OS VI. Patent application Fanyuan Second Surface (112), which contains the chip The third electrode (30), the method includes the following steps: electrically connecting a first part (151) of a first conductive frame (15) to the first electrode (10) of the crystal moon, and A second portion (152) of one of the conductive frames (15) is electrically connected to the second electrode (2) of the wafer, and the first conductive frame (15) is removed from the first electrode (10) and the second electrode (2) of the wafer 20) extend outside the wafer; and a second conductive frame (16) is electrically connected to the third electrode (30) of the wafer, and the second conductive frame (16) is from the third electrode of the wafer ( 3 0) to the outside of the wafer. 16. The manufacturing method according to item 15 of the scope of patent application, further comprising the step of extending the first portion of the first conductive frame outside the wafer to further form the pins of the first electrode. 17. The manufacturing method according to item 15 of the scope of patent application, further comprising the step of extending the second part of the first conductive frame to the outside of the wafer to further form the pins of the second electrode. 18. The manufacturing method according to item 15 of the scope of patent application, further comprising the step of extending the second conductive frame outside the wafer 'to further form a pin of the third electrode. 19. If the manufacturing method of the scope of application for patent No. 15 further includes extending the first part, the second part and the second conductive frame of the first conductive frame to the outside of the chip, and further electrically connecting at least three of them to other The step of electrode of the wafer to form a multi-chip module (MCM). 20. If the manufacturing method of item 15 of the scope of patent application is still included in the first O: \ 62 \ 62449-DOC \ WCK _ 1 5 _ This paper is again used in Ningguo National Kneading (CNS) A4 specifications ( 210 X 297 mm) -------- Installation-•-(Please read the notes on the back before filling this page) Order printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs 451366 A8 B8 C8 D8 A step of forming a conductive contact on the first part of the conductive frame of the patent application for the conductive contact of the first electrode. Both the 21. The manufacturer of item 15 of the scope of patent application ′ further includes the step of forming a plurality of conductive contacts (153) on the second part of the first conductive frame for electrical connection with the second electrode. 22. The manufacturing method according to item 15 of the scope of patent application, further comprising the step of forming a plurality of conductive contacts (16 3) on the second conductive frame for electrical connection with the third electrode. (Please read the precautions on the back before filling out this page). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 0: \ «M2449.D〇aWCK 16- This paper size applies to China National Standard (CNS) A4 (210X297 mm)
TW089110374A 2000-05-29 2000-05-29 Power device chip package and method for manufacturing the same TW451366B (en)

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