TW511262B - Chip scale package for power semiconductor device - Google Patents

Abstract

This invention provides a chip scale package structure for power semiconductor device, which is characterized by performing a vertical package of the power semiconductor device. The inventive package device contains a power semiconductor chip having a first side face and an opposite second side face, in which the two side faces are electrically connected to two metal leadframes in a vertical fashion. Then, a molding resin encapsulation process is utilized to perform a chip scale package on the entire structure. This invention can greatly reduce cross-section of the packaged product and place many chips on a printed circuit board to fulfill current trend for products being light weight and small and thin in size.

Description

FIELD OF THE INVENTION The present invention relates to a wafer-size package for a power semiconductor, and more particularly to a wafer-level package for placing a wafer in a vertical position. BACKGROUND OF THE INVENTION In order to meet the current trend of miniaturization of computers and communication components and the need for portable convenience, how to place more chips on the same printed circuit board, moving parts, passive parts, and semiconductor chips The reduction in size has become the research and development direction of the industry. In response to this trend, the packaging technology of semiconductor wafers has also become quite important-it must simplify the evolution of technology to develop packages that occupy less space, have faster packaging speeds, and are cheaper. The general chip packaging method, whether it is wire bonding (wh bonding), tape bonding (TAB), or flip-chip (fUp_chip), etc., the entire package includes the chip, metal lead frame, packaging gel, etc. The components are placed horizontally. As shown in Figure 丨 P is a side view of Bai Zhi's power semiconductor chip package, wherein the power element wafer 10 has an upper surface 102 and a lower surface ι04. The upper surface 102 of the chip is electrically connected to a first metal lead frame 12 using a solder n, while the lower surface 104 is also electrically connected to a second metal lead frame 14 using a solder u, (the entire component is later Use gel 丨 3 for final packaging. In addition to soldering, metal wire wood and wafers can also be fixed with conductive glue. After the packaging glue system is completed, the size of this package is usually smaller than the chip itself. The size is much larger, which does not meet the trend of shrinking package size. Then, in order to effectively reduce the size of the package, the chip size package (CSP) technology was developed. The so-called chip size package (csp) refers to packaging in various ways.

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V. Description of the invention (2) The size of the packaged product after assembly is not more than the volume of W itself. Because the package size of the chip size package is larger than the original chip size, it is quite in line with the recent trend of short and thin consumer products. It is expected that it will be used in a large number of electronic communication products. The chip size package still places the wafer horizontally, making it impossible to advance within the fixed U area of the γ brush circuit board-making a more efficient profit. To sum up, how to reduce the volume of the package to facilitate printing "Better use of circuit boards" has become an important issue at the moment. Brief description of the invention 2 The first-objective of the invention is to provide a chip size package for power semiconductors that vertically packages a chip to reduce the area of a positive package. The present invention <Second purpose is to provide a chip size package for power semiconductors, which can place more components in a limited area on a printed circuit board for more efficient use. In order to achieve the above purpose, the present invention discloses a Wafer size package structure for power semiconductors! It includes: a power element wafer, which is placed in an upright position. And-the opposite second side;-spear: a metal lead frame and a second metal lead frame are electrically connected to the -side and the second side of the power element chip; and the first metal lead frame and the second side Two or more lead frames extend outward from the bottom end of the chip. Since the power element wafer of the present invention is a vertical package, rather than a traditional horizontal package, the pin pitch of the entire package is a power element chip Thickness, rather than the length / width of the power device chip as traditional pins. This paper size applies towel @ g * Standard (CNS) A4 specification (规格> &lt; 297 public love) A7

The degree is the pitch; ^ r is less than t, and the area occupied by the package when it is placed on the surface of the printed circuit board is non-trivial... Hanging ^ ′ allows more semiconductor components to be mounted on the printed circuit board. According to the present invention &lt; wafer size package for power semiconductors, which can be widely applied to P / N diodes, dual monolithic elements (duai m0lithic), and metal oxide half field effect transistors (M 〇s F e τ) and so on power semiconductor components can greatly improve the efficiency and application range of power semiconductors. Brief description of the affiliate formula _ The present invention will be described in accordance with the following drawings, in which FIG. 1 is a side view of a conventional power semiconductor chip package. Fig. 2A is a top view of a wafer assembly of a wafer size package structure of a power semiconductor device according to a first embodiment of the present invention. Fig. 2B is a side view of a wafer assembly of a wafer size package structure of a power semiconductor device according to a first embodiment of the present invention. FIG. 3A is a top view of a wafer assembly of a wafer size package structure of a power semiconductor device according to a second embodiment of the present invention. Fig. 3B is a side view of a wafer assembly of a wafer size package structure of a power semiconductor device according to a second embodiment of the present invention. FIG. 4A is a side view of a wafer assembly of a power semiconductor device wafer size package structure according to a third embodiment of the present invention. FIG. 4B is a bottom view of a wafer assembly of a power semiconductor device wafer size package structure according to the third embodiment of the present invention. Fig. 4C is a top plan view taken along line A-A of Fig. 4A. Component symbol description This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 511262 A7 _ B7 V. Description of the invention (4) 10 Power component wafer 1 02 Upper surface 104 Lower surface 11 Solder 12 First metal Lead frame 13 Encapsulant 14 Second metal lead frame 20 Wafer 2 1 First metal lead frame 22 First side 23 Second metal lead frame 24 Second side 2 5 Solder 26 Encapsulant 3 3 Double monolithic wafer 3 1 First Metal lead frame 32 first side 3 3 second metal lead frame 3 4 second side 3 22% one electrode 3 24 second electrode 3 10 first part 3 12 second part 3 5 solder 3 6 encapsulant 40 chip 4 1 First metal lead frame 42 First side 43 First metal lead frame 44 Second side 4 11 First part 4 13 Second part 422 First electrode 424 Second electrode 45 Solder 46 Explanation Hereinafter, the first embodiment of the present invention will be described with reference to the drawings. Note that the dimensional ratios of the components in the drawings are not expressed by the actual ratio. ___ _7_ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ^-Α7

The bottom of the glue m 2 6 is on the same plane, so that the two bent feet can be used to fix the printed circuit board. The entire device is then packaged at the wafer level using a wafer size packaging process. FIG. 2A shows a power semiconductor device wafer according to another embodiment of the present invention. Construction top view of tablet assembly. Figure 2B is a side view of the wafer assembly. In this embodiment, the power semiconductor element is a ρ / N diode. The chip 20 is a vertical speaker, and has a first side 22 and a second side 2 4. It is gas-connected to a first metal lead frame 2 with a solder 25, and the second side 24 is air-tightly connected to a second metal lead frame 23 to the metal lead frame and the chip is fixed. Conductive glue can also be used. The C-link system is a method using solder as shown in this embodiment. Referring to FIG. 2B, after the metal lead frame 21 and the second metal lead frame η are extended from the bottom of the wafer, the bent pins will be closed. Referring to FIG. 3A, it is a second embodiment according to the present invention. Top view of wafer assembly of power semiconductor device wafer size package structure. Figure 3B is a side view. The power semiconductor device in this embodiment is a hal monolithic wafer 30, which has a first side surface 32 and a second side surface 34. The first side 3 2 0 includes a first electrode 3 2 2 and a second electrode 324, which are respectively connected to the first portion 3 1 0 and the second portion 3 1 2 of a first metal lead frame 31. Electrical connection; and the second side 34 is electrically connected to a second metal lead frame 3 3. The connection method is as shown in the previous embodiment, and solder 35 is also used for connection. Referring to FIG. 3B, as in the first embodiment, after the metal lead frame and the wafer are connected, the first metal lead frame 31 and the second metal lead frame 33 are extended from the bottom of the wafer. CNS) A4 size (210X 297 mm)

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A7 B7 V. Description of the invention (6) The spoon knife is folded and bowed, and the bent pins (pins) will be on the same plane as the bottom of the packaging gel 3 6 &lt; It is fixed on the printed circuit board. Thereafter, the entire device is packaged at the wafer level using a wafer size packaging process. Referring to FIG. 4A 'is a side view of a wafer assembly of a wafer size package structure of a power semiconductor device according to a third embodiment of the present invention. Fig. 4B is a bottom view and Fig. 4C is a top view of the A-A cross section of Fig. 4A. The power semiconductor wafer of this embodiment is a metal-oxide-semiconductor field-effect transistor (MOS FET) wafer. As shown in FIGS. 4A and 4C, the wafer 40 has a first side surface 4 2 and a second side surface 44. The first side surface 4 2 has a first electrode 4 2 2 (or source) and a First electrode 4 2 4 (or gate); the first electrode 4 2 2 is electrically connected to the first portion 411 of a first metal lead frame 41, and the second electrode 424 is connected to the first metal lead The second portion 413 of the rack 41 is electrically connected. The second side 4 4 (or the drain) of the chip 40 is electrically connected to a second metal lead frame 4 3. As in the previous two embodiments, this embodiment also uses a solder (solder 45) to bond the metal lead frame and the wafer, so that the chip area can be fully applied. Referring to FIG. 4A, after the connection between the metal lead frame and the wafer is completed, the portions of the first metal lead frame 41 and the second metal lead frame 43 extending from the bottom of the wafer are bent, and the bent pins are bent. Together with the encapsulants 4 and 6 will be on the same plane, so that the bent feet can be fixed to the printed circuit board. Finally, the entire device is packaged at the wafer level using a wafer size packaging process. Referring to FIG. 4B, even if the wafer of the present invention is packaged in an upright wafer-level package, the various electrodes can be properly arranged without affecting the performance of the component, and .. -9 · This Paper size is suitable for T S household materials (CNS) A4 (21GX297 mm) * &quot; '— 511262 A7

And make the overall volume smaller.

&quot; From the above embodiments, it can be known that the most important feature of the present invention is that the Japanese-theta tablets of power and other semiconductors are directly packaged, which can greatly reduce the cross-section of the package; csp), so the volume of the entire body is also controlled to a relatively small level. Therefore, more chips can be placed on the same printed circuit board to make the product more powerful or to reduce the size of the product. It is in line with the current development trend of portable, thin, light and short electronic products. Furthermore, the structure of the present invention is applicable to various semiconductor wafer size packages, such as diodes, monolithic wafers, or metal-oxide-semiconductor half-effect transistors, etc., and has an extremely wide range of applications. Binding The technical content and technical features of the present invention are disclosed as above. However, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the invention without departing from the spirit of the present invention. @This, the scope of protection of the present invention should not be limited to those described in the embodiments, but should include various substitutions and modifications that do not depart from the present invention, and are covered by the scope of patent application below. -10-

Claims (1)

A8 B8 C8 D8 Patent Application Scope • ~ A wafer size package structure for power semiconductor devices, including: ~ a power element wafer, including a first side and an opposite second side; ^ a first metal lead frame, and The first side of the power element chip is electrically connected; and the first metal lead frame is electrically connected to the second side of the power element; and characterized in that the power semiconductor chip is placed in an upright position, so the entire package structure is also Upright. 2. The packaging structure according to item 2 in claim 2, wherein the first side of the power element wafer has a first electrode and a second electrode, which are respectively connected to a first portion and a second electrode of the second metal lead frame. Partial electrical connection. 3 · If the scope of patent application is the first! The package structure of item, wherein the power element wafer is a diode or a pair of monolithic wafers or a metal oxide half field effect transistor. 4. The package structure according to item 丨 of the application, wherein the first metal lead, spring wood, and second metal lead frame extend outward from the bottom end of the chip to form pins. 5. The package structure according to item 4 of the scope of patent application, wherein the pins of the first metal lead spring and the second metal lead frame are bent on the same plane. 6. The package structure according to the scope of the patent application, wherein the package system is a chip-size package. —11-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)