CN100435328C - 模塑封装件 - Google Patents
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- CN100435328C CN100435328C CNB2006101425856A CN200610142585A CN100435328C CN 100435328 C CN100435328 C CN 100435328C CN B2006101425856 A CNB2006101425856 A CN B2006101425856A CN 200610142585 A CN200610142585 A CN 200610142585A CN 100435328 C CN100435328 C CN 100435328C
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Abstract
本发明提供一种模塑封装件,使散热性以及高频率特性提高,从而可分离进行电接地和散热。包括:半导体芯片;焊接了半导体芯片的厚膜引线电极;比厚膜引线电极薄的薄膜引线电极;电连接半导体芯片和薄膜引线电极的线材;以及封止半导体芯片以及线材的模塑材料,厚膜引线电极的下表面的一部分在封装件下表面露出而作为散热电极使用,薄膜引线电极的上表面的一部分在封装件上表面露出而作为输入、输出电极使用,厚膜引线电极的上表面的一部分在封装件上表面露出而作为接地电极使用。
Description
技术领域
本发明涉及以高频率或高输出进行动作的模塑封装件,尤其涉及使散热性及高频率特性提高,可分离进行电接地和散热的模塑密封件.
背景技术
在图12中表示以高频率或高输出进行动作的已有模塑封装件的一例(例如,参考专利文献1).如图所示,向下方弯曲薄膜引线电极51而构成了输入、输出引线电极52.此外,向上方弯曲薄膜引线电极51以构成芯片焊盘部53,通过焊锡等焊接半导体芯片54.半导体芯片54经金属线材56与输入、输出引线电极52相连接.半导体芯片54以及金属线材56由塑料等模塑材料57封止.而且,通过在芯片焊盘部53上使引线电极51露出,从而构成接地电极55.由此降低接地电感,使散热性提高.
在图13中表示与上述的例子相同地使用了薄膜引线电极51的已有模塑封装件的其它例.如图所示,在同一平面上形成有输入、输出引线电极52和接地电极55.
但是,在这些模塑封装件中,因为引线电极的厚度通常为0.2mm左右,比较薄,热容量较小,所以散热性较低,因而需要热容量较大的散热板(heat sink),以防止半导体芯片的温度上升.此外,寄生电感以及寄生电容变大,所以不能使高频率特性提高.
为此,在图14中表示使散热性以及高频率特性提高的已有模塑封装件的一例的截面图,图15表示上表面图(例如,参考专利文献2).如图所示,在由厚膜引线电极构成的接地电极58上焊接半导体芯片54,从模塑材料57露出接地电极58的上表面,从而使散热性提高.
在图16中表示提高了散热性以及高频率特性的已有模塑封装件的其它例(例如,参考专利文献3).如图所示,在薄膜引线电极59的下表面粘附分别切制的厚膜的散热电极60,以提高散热性.
(专利文献1)特开平8-213536号公报
(专利文献2)特开平4-174547号公报
(专利文献3)特开平6-61396号公报
但是,在已有的模塑封装件中,分离进行电接地和散热是较困难的.
发明内容
本发明正是为了解决上述课题而提出来的,其目的是得到一种模塑封装件,使散热性以及高频率特性提高,可分离进行电接地和散热.
本发明所述的模塑封装件包括:半导体芯片;中央部具有凹部,并且半导体芯片焊接在凹部上的厚膜引线电极;比厚膜引线电极薄的薄膜引线电极;电连接半导体芯片和薄膜引线电极的线材;以及封止半导体芯片以及线材的模塑材料,厚膜引线电极的下表面的一部分在封装件下表面露出而作为散热电极使用,薄膜引线电极的上表面的一部分在封装件上表面露出而作为输入、输出电极使用,厚膜引线电极的上表面的一部分在封装件上表面露出而作为接地电极使用.本发明的其它特征显示如下.
通过本发明,使散热性以及高频率特性提高,可分离进行电接地和散热.
附图说明
图1是表示本发明的实施方式所述的模塑封装件的立体图.
图2是使图1的上下颠倒后的图.
图3是表示本发明的实施方式所述的模塑封装件的上表面图.
图4是表示本发明的实施方式所述的模塑封装件的下表面图.
图5是表示本发明的实施方式所述的模塑封装件的侧视图.
图6是表示引线框体状态的厚膜引线电极以及薄膜引线电极的上表面图.
图7是沿着图6的a-a’的截面图.
图8是沿着图6的b-b’的截面图.
图9是表示以覆盖半导体芯片的表面的方式涂敷了涂料状态的截面图.
图10是图8的厚膜引线电极的弯曲部分的放大图.
图11是表示本发明的实施方式2所述的模塑封装件的截面图.
图12是表示已有模塑封装件的一例的截面图.
图13是表示已有模塑封装件的其它例的截面图.
图14是表示使散热性提高的已有模塑封装件的一例的截面图.
图15是表示使散热性提高的已有模塑封装件的一例的上表面图.
图16是表示使散热性提高的已有模塑封装件的其它例的截面图.
附图标记说明:
10模塑封装件
11半导体芯片
12、21厚膜引线电极
13、22薄膜引线电极
14金属线材
15模塑材料
16接地电极
17散热电极
18输入、输出引线电极
24镀层
25止动槽
26涂料
27氧化铜覆膜
具体实施方式
实施方式1
图1是表示本发明的实施方式所述的模塑封装件的立体图,图2是使图1的上下颠倒后的图.如图所示,半导体芯片11通过焊锡等被焊接在将厚度为0.4~1.0mm左右的厚膜引线电极12的中央部弯曲的凹部上.而且,厚度为0.05~0.2mm左右的薄膜引线电极13向下方弯曲成接近半导体芯片11,并通过金属线材14与半导体芯片11电连接.这些半导体芯片11以及金属线材14通过塑料等模塑材料15封止,从而构成了模塑封装件10.
在图3中表示该模塑封装件的上表面图,图4表示下表面图,图5表示侧视图.如图所示,厚膜引线电极12的上表面的一部分在模塑封装件10上表面露出而作为接地电极16使用.此外,厚膜引线电极12的下表面的一部分在模塑封装件10下表面露出而作为放出在半导体芯片11中产生的热量的散热电极17使用.而且,薄膜引线电极13的上表面的一部分在模塑封装件10上表面露出而作为输入、输出引线电极18使用.
另外,该模塑封装件在图2的状态下使用.为了不使散热电极17电接地而仅实施散热,所以在散热板(未图示)和散热电极17之间插入由绝缘体形成的散热板19.
接下来,对于引线框体状态的厚膜引线电极12以及薄膜引线电极13进行说明.图6是表示引线框体状态的厚膜引线电极以及薄膜引线电极的上表面图,图7是沿着图6的a-a’的截面图,图8是沿着图6的b-b’的截面图.
引线框体状态的厚膜引线电极21以及薄膜引线电极22使用铜(Cu)类材料作成,通过设置于不形成半导体芯片11的位置的铆接部23将两引线框体结合.而且,厚膜引线电极21呈凹字型弯曲,薄膜引线电极22向下方弯曲成与半导体芯片11的焊接距离为最佳.
此外,在作为通过焊锡等焊接半导体芯片11的区域的厚膜引线电极21的凹部,由银(Ag)等形成镀层24.由此,可以缓和由于焊接时的热量和半导体芯片11的动作时的发热而对半导体芯片11所施加的热应力.例如,当芯片焊接中使用银类(Ag)焊锡的情况下,通过银(Ag)形成镀层24.
此外,在厚膜引线电极21上,在半导体芯片11的装载部的周围设置有止动槽25.由此,如图9所示,在以覆盖半导体芯片11的表面的方式涂敷了树脂类的涂料26时,可以防止涂料26向着厚膜引线电极21侧面和下表面流出.
图10是图8的厚膜引线电极的弯曲部分的放大图.如图所示,厚膜引线电极21被弯曲成多阶梯状,从而在封装件的上下表面附近处相对于上下表面垂直.由此,在随后通过模塑材料15封止时,可以防止如下现象发生,即在厚膜引线电极12的上下表面的一部分所露出的接地电极16或散热电极17上固定附着不要的模塑材料15(飞边).
如上所述,通过由厚膜引线电极12形成接地电极16,由厚膜引线电极12形成散热电极17,由此使散热性提高,即使在与散热电极17接触的散热板的热容量较低的情况或接触不够充分的情况下,也可防止半导体芯片的温度上升.
此外,与通过薄膜引线电极13形成了接地电极16的情况相比,可降低接地电感、接地电阻,使高频率下的动作成为可能.
此外,在封装件上表面形成接地电极16,在封装件下表面形成散热电极17,由此可以分离进行电接地和散热.
另外,优选的情况是,在模塑封装件10的上表面露出的接地电极16的形状是コ字形或U字形.由此,因为可降低切断(连杆切断)厚膜引线电极12的引线框体时的切断面积,所以可以在与已有的切断薄膜引线电极同样的条件下进行切断.此外,因为在切入部分中填充模塑材料,所以模塑材料和厚膜电极的剥离强度得以增加.
此外,在焊接等高温处理时,优选的情况是:氧化厚膜引线电极21以及薄膜电极22表面而形成氧化铜覆膜.因为氧化铜与模塑材料之间的贴紧性良好,所以可以阻止水分从引线框体和模塑材料的界面侵入.
此外,在本实施方式中对于输入、输出电极各为一条的情况进行了说明,但是在具有多个电极的封装件中也会获得同等的效果.此外,半导体芯片的种类并无特别限制,硅基板或GaAs、InP等化合物基板的任一半导体芯片也会获得同等的效果.
实施方式2
图11是表示本发明的实施方式2所述的模塑封装件的截面图.与图1~10同样的构成要素采用相同的附图标记,省略说明.
在本实施方式所述的模塑封装件中,在根据芯片焊接区域的银(Ag)等的镀层24上析出了氧化铜覆膜27.由此,由于半导体芯片11附近处的厚膜引线电极21和模塑材料15的贴紧性得以提高,所以半导体11的可靠性进一步被提高.
作为使氧化铜覆膜27析出在镀层24上的方法,有如下方法,即在氮(N2)等惰性气体的比率较高的气氛下,氧化厚膜电极21表面,使在厚膜引线电极21表面上形成的氧化铜扩散到镀层24,从而在镀层24表面析出.
Claims (7)
1.一种模塑封装件,其特征在于,
包括:半导体芯片;中央部具有弯曲的凹部,并且上述半导体芯片焊接在上述凹部上的厚膜引线电极;比上述厚膜引线电极薄的薄膜引线电极;电连接上述半导体芯片和上述薄膜引线电极的线材;以及封装上述半导体芯片以及上述线材的模塑材料,
上述厚膜引线电极的下表面的一部分在封装件下表面露出而作为散热电极使用,
上述薄膜引线电极的上表面的一部分在封装件上表面露出而作为输入、输出电极使用,
上述厚膜引线电极的上表面的一部分在封装件上表面露出而作为接地电极使用。
2.如权利要求1所述的模塑封装件,其特征在于,
还具有以覆盖上述半导体芯片的方式涂敷的涂料,
在上述厚膜引线电极上,在焊接上述半导体芯片的区域的周围设置有止动槽。
3.如权利要求1所述的模塑封装件,其特征在于,上述厚膜引线电极被弯曲成在封装件上下表面附近处相对于上下表面垂直。
4.如权利要求1所述的模塑封装件,其特征在于,在上述封装件上表面露出的上述接地电极的形状是コ字形或U字形。
5.如权利要求1所述的模塑封装件,其特征在于,上述厚膜引线电极使用铜类材质作成,表面上形成有氧化铜覆膜。
6.如权利要求1所述的模塑封装件,其特征在于,上述厚膜引线电极使用铜类材质作成,在焊接上述半导体芯片的区域形成有镀层。
7.如权利要求6所述的模塑封装件,其特征在于,在上述厚膜电极的表面上形成有氧化铜覆膜,在上述镀层的表面上析出有上述氧化铜覆膜。
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JP4617209B2 (ja) * | 2005-07-07 | 2011-01-19 | 株式会社豊田自動織機 | 放熱装置 |
GB2451077A (en) * | 2007-07-17 | 2009-01-21 | Zetex Semiconductors Plc | Semiconductor chip package |
JP5572890B2 (ja) | 2010-06-08 | 2014-08-20 | ミヨシ電子株式会社 | 半導体モジュールおよび半導体装置 |
US8937374B2 (en) * | 2011-12-22 | 2015-01-20 | Panasonic Corporation | Semiconductor package, method and mold for producing same, input and output terminals of semiconductor package |
CN103400816B (zh) * | 2013-06-26 | 2016-08-10 | 三星半导体(中国)研究开发有限公司 | 封装件及其制造方法 |
JP6345583B2 (ja) * | 2014-12-03 | 2018-06-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2017041541A (ja) * | 2015-08-20 | 2017-02-23 | 三菱電機株式会社 | 高周波高出力用デバイス装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04174547A (ja) * | 1990-11-07 | 1992-06-22 | Nec Corp | 表面実装型電力用半導体装置 |
JPH0661396A (ja) * | 1992-08-07 | 1994-03-04 | Fujitsu Ltd | 放熱板付リードフレームとそれを用いた半導体装置 |
JPH08213536A (ja) * | 1994-11-14 | 1996-08-20 | Texas Instr Inc <Ti> | パッケージの一面に露出した半導体ダイ取付けパッドを有するダウンセットされたリードフレームおよびその製造方法 |
CN1144403A (zh) * | 1995-08-28 | 1997-03-05 | 戴超智 | 以槽形外壳构件组构的半导体二极管及其封装方法 |
US6153924A (en) * | 1998-02-23 | 2000-11-28 | Micron Technology, Inc. | Multilayered lead frame for semiconductor package |
JP2001144229A (ja) * | 1999-11-17 | 2001-05-25 | Nec Corp | 樹脂封止型半導体装置 |
CN1357919A (zh) * | 2000-12-11 | 2002-07-10 | 台湾通用器材股份有限公司 | 功率型半导体芯片的封装装置及封装方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57139917A (en) * | 1981-02-23 | 1982-08-30 | Matsushita Electric Ind Co Ltd | Chip type solid electrolytic condenser and method of producing same |
US4974057A (en) * | 1986-10-31 | 1990-11-27 | Texas Instruments Incorporated | Semiconductor device package with circuit board and resin |
JPH03222465A (ja) * | 1990-01-29 | 1991-10-01 | Mitsubishi Electric Corp | リードフレームおよびその製造方法 |
US6326678B1 (en) * | 1993-09-03 | 2001-12-04 | Asat, Limited | Molded plastic package with heat sink and enhanced electrical performance |
JPH0786460A (ja) * | 1993-09-17 | 1995-03-31 | Toshiba Corp | 半導体装置 |
JPH08330477A (ja) * | 1995-05-31 | 1996-12-13 | Mitsumi Electric Co Ltd | 半導体装置 |
KR100266726B1 (ko) * | 1995-09-29 | 2000-09-15 | 기타지마 요시토시 | 리드프레임과 이 리드프레임을 갖춘 반도체장치 |
JP2907186B2 (ja) * | 1997-05-19 | 1999-06-21 | 日本電気株式会社 | 半導体装置、その製造方法 |
EP0895287A3 (en) * | 1997-07-31 | 2006-04-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and lead frame for the same |
US6075283A (en) * | 1998-07-06 | 2000-06-13 | Micron Technology, Inc. | Downset lead frame for semiconductor packages |
US6211462B1 (en) * | 1998-11-05 | 2001-04-03 | Texas Instruments Incorporated | Low inductance power package for integrated circuits |
US6198163B1 (en) * | 1999-10-18 | 2001-03-06 | Amkor Technology, Inc. | Thin leadframe-type semiconductor package having heat sink with recess and exposed surface |
US6246111B1 (en) * | 2000-01-25 | 2001-06-12 | Siliconware Precision Industries Co., Ltd. | Universal lead frame type of quad flat non-lead package of semiconductor |
JP2002110888A (ja) * | 2000-09-27 | 2002-04-12 | Rohm Co Ltd | アイランド露出型半導体装置 |
TW469609B (en) * | 2000-10-11 | 2001-12-21 | Ultratera Corp | Chipless package semiconductor device and its manufacturing method |
JP2002170917A (ja) * | 2000-11-30 | 2002-06-14 | Goto Seisakusho:Kk | 半導体装置用リードフレームの製造方法 |
JP3895570B2 (ja) * | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
JP4308528B2 (ja) | 2001-01-31 | 2009-08-05 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
-
2005
- 2005-12-12 JP JP2005357517A patent/JP5103731B2/ja active Active
-
2006
- 2006-06-13 US US11/451,372 patent/US8569871B2/en active Active
- 2006-10-30 CN CNB2006101425856A patent/CN100435328C/zh active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04174547A (ja) * | 1990-11-07 | 1992-06-22 | Nec Corp | 表面実装型電力用半導体装置 |
JPH0661396A (ja) * | 1992-08-07 | 1994-03-04 | Fujitsu Ltd | 放熱板付リードフレームとそれを用いた半導体装置 |
JPH08213536A (ja) * | 1994-11-14 | 1996-08-20 | Texas Instr Inc <Ti> | パッケージの一面に露出した半導体ダイ取付けパッドを有するダウンセットされたリードフレームおよびその製造方法 |
CN1144403A (zh) * | 1995-08-28 | 1997-03-05 | 戴超智 | 以槽形外壳构件组构的半导体二极管及其封装方法 |
US6153924A (en) * | 1998-02-23 | 2000-11-28 | Micron Technology, Inc. | Multilayered lead frame for semiconductor package |
JP2001144229A (ja) * | 1999-11-17 | 2001-05-25 | Nec Corp | 樹脂封止型半導体装置 |
CN1357919A (zh) * | 2000-12-11 | 2002-07-10 | 台湾通用器材股份有限公司 | 功率型半导体芯片的封装装置及封装方法 |
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