JP5103731B2 - モールドパッケージ - Google Patents
モールドパッケージ Download PDFInfo
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- JP5103731B2 JP5103731B2 JP2005357517A JP2005357517A JP5103731B2 JP 5103731 B2 JP5103731 B2 JP 5103731B2 JP 2005357517 A JP2005357517 A JP 2005357517A JP 2005357517 A JP2005357517 A JP 2005357517A JP 5103731 B2 JP5103731 B2 JP 5103731B2
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/491—Disposition
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- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Description
図1は、本実施の形態に係るモールドパッケージを示す斜視図であり、図2は図1の上下を反転させたものである。図示のように、半導体チップ11は、厚さ0.4〜1.0mm程度の厚膜リード電極12の中央部を折り曲げた凹部に半田等でダイボンドされている。そして 厚さ0.05〜0.2mm程度の薄膜リード電極13が半導体チップ11に近づくよう下方に曲げられ、金属ワイヤ14により半導体チップ11と電気的に接続されている。これらの半導体チップ11及び金属ワイヤ14がプラスチック等のモールド材15により封止されて、モールドパッケージ10が構成されている。
図11は、本発明の実施の形態2に係るモールドパッケージを示す断面図である。図1〜10と同様の構成要素には同じ番号を付し、説明を省略する。
11 半導体チップ
12,21 厚膜リード電極
13,22 薄膜リード電極
14 金属ワイヤ
15 モールド材
16 接地電極
17 放熱電極
18 入力・出力リード電極
24 メッキ層
25 ストッパー溝
26 コート材
27 酸化銅被膜
Claims (6)
- 半導体チップと、
前記半導体チップがダイボンドされた厚膜リード電極と、
前記厚膜リード電極よりも薄い薄膜リード電極と、
前記半導体チップと前記薄膜リード電極とを電気的に接続するワイヤと、
前記半導体チップ及び前記ワイヤを封止するモールド材とを有し、
前記厚膜リード電極の下面の一部は、パッケージ下面で露出して放熱電極として用いられ、
前記薄膜リード電極の上面の一部がパッケージ上面で露出して入力・出力電極として用いられ、
前記厚膜リード電極の上面の一部がパッケージ上面で露出して接地電極として用いられ、
前記厚膜リード電極は、銅系材質を用いて作成され、前記半導体チップがダイボンドされる領域及びその近傍にメッキ層が形成され、
前記厚膜リード電極の表面に酸化銅被膜が形成され、前記半導体チップがダイボンドされる領域の近傍において前記メッキ層の表面に前記酸化銅被膜が析出していることを特徴とするモールドパッケージ。 - 前記半導体チップは、前記厚膜リード電極の中央部を折り曲げた凹部にダイボンドされていることを特徴とする請求項1に記載のモールドパッケージ。
- 前記半導体チップを覆うように塗布されたコート材を更に有し、
前記厚膜リード電極には、前記半導体チップがダイボンドされる領域の周囲にストッパー溝が設けられていることを特徴とする請求項1に記載のモールドパッケージ。 - 前記厚膜リード電極は、パッケージ上下面近傍において上下面に対し垂直になるように曲げられていることを特徴とする請求項1に記載のモールドパッケージ。
- 前記パッケージ上面で露出した前記接地電極の形状は、コの字又はU字であることを特徴とする請求項1に記載のモールドパッケージ。
- 前記厚膜リード電極は、銅系材質を用いて作成され、表面に酸化銅被膜が形成されていることを特徴とする請求項1に記載のモールドパッケージ。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005357517A JP5103731B2 (ja) | 2005-12-12 | 2005-12-12 | モールドパッケージ |
US11/451,372 US8569871B2 (en) | 2005-12-12 | 2006-06-13 | Semiconductor device having a molded package |
CNB2006101425856A CN100435328C (zh) | 2005-12-12 | 2006-10-30 | 模塑封装件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005357517A JP5103731B2 (ja) | 2005-12-12 | 2005-12-12 | モールドパッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007165442A JP2007165442A (ja) | 2007-06-28 |
JP5103731B2 true JP5103731B2 (ja) | 2012-12-19 |
Family
ID=38138483
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005357517A Active JP5103731B2 (ja) | 2005-12-12 | 2005-12-12 | モールドパッケージ |
Country Status (3)
Country | Link |
---|---|
US (1) | US8569871B2 (ja) |
JP (1) | JP5103731B2 (ja) |
CN (1) | CN100435328C (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4617209B2 (ja) * | 2005-07-07 | 2011-01-19 | 株式会社豊田自動織機 | 放熱装置 |
GB2451077A (en) * | 2007-07-17 | 2009-01-21 | Zetex Semiconductors Plc | Semiconductor chip package |
JP5572890B2 (ja) | 2010-06-08 | 2014-08-20 | ミヨシ電子株式会社 | 半導体モジュールおよび半導体装置 |
CN104025292B (zh) * | 2011-12-22 | 2018-03-09 | 松下知识产权经营株式会社 | 半导体封装、其制造方法及模具、半导体封装的输入输出端子 |
CN103400816B (zh) * | 2013-06-26 | 2016-08-10 | 三星半导体(中国)研究开发有限公司 | 封装件及其制造方法 |
JP6345583B2 (ja) * | 2014-12-03 | 2018-06-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2017041541A (ja) * | 2015-08-20 | 2017-02-23 | 三菱電機株式会社 | 高周波高出力用デバイス装置 |
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JPS57139917A (en) * | 1981-02-23 | 1982-08-30 | Matsushita Electric Ind Co Ltd | Chip type solid electrolytic condenser and method of producing same |
US4974057A (en) * | 1986-10-31 | 1990-11-27 | Texas Instruments Incorporated | Semiconductor device package with circuit board and resin |
JPH03222465A (ja) * | 1990-01-29 | 1991-10-01 | Mitsubishi Electric Corp | リードフレームおよびその製造方法 |
JPH04174547A (ja) | 1990-11-07 | 1992-06-22 | Nec Corp | 表面実装型電力用半導体装置 |
JP3109267B2 (ja) | 1992-08-07 | 2000-11-13 | 富士通株式会社 | 放熱板付リードフレームとそれを用いた半導体装置 |
US6326678B1 (en) * | 1993-09-03 | 2001-12-04 | Asat, Limited | Molded plastic package with heat sink and enhanced electrical performance |
JPH0786460A (ja) * | 1993-09-17 | 1995-03-31 | Toshiba Corp | 半導体装置 |
US5594234A (en) | 1994-11-14 | 1997-01-14 | Texas Instruments Incorporated | Downset exposed die mount pad leadframe and package |
JPH08330477A (ja) * | 1995-05-31 | 1996-12-13 | Mitsumi Electric Co Ltd | 半導体装置 |
CN1043173C (zh) * | 1995-08-28 | 1999-04-28 | 智威科技股份有限公司 | 以槽形外壳构件组构的半导体二极管及其封装方法 |
KR100266726B1 (ko) * | 1995-09-29 | 2000-09-15 | 기타지마 요시토시 | 리드프레임과 이 리드프레임을 갖춘 반도체장치 |
JP2907186B2 (ja) * | 1997-05-19 | 1999-06-21 | 日本電気株式会社 | 半導体装置、その製造方法 |
EP0895287A3 (en) * | 1997-07-31 | 2006-04-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and lead frame for the same |
US6002165A (en) * | 1998-02-23 | 1999-12-14 | Micron Technology, Inc. | Multilayered lead frame for semiconductor packages |
US6075283A (en) * | 1998-07-06 | 2000-06-13 | Micron Technology, Inc. | Downset lead frame for semiconductor packages |
US6211462B1 (en) * | 1998-11-05 | 2001-04-03 | Texas Instruments Incorporated | Low inductance power package for integrated circuits |
US6198163B1 (en) * | 1999-10-18 | 2001-03-06 | Amkor Technology, Inc. | Thin leadframe-type semiconductor package having heat sink with recess and exposed surface |
JP2001144229A (ja) | 1999-11-17 | 2001-05-25 | Nec Corp | 樹脂封止型半導体装置 |
US6246111B1 (en) * | 2000-01-25 | 2001-06-12 | Siliconware Precision Industries Co., Ltd. | Universal lead frame type of quad flat non-lead package of semiconductor |
JP2002110888A (ja) * | 2000-09-27 | 2002-04-12 | Rohm Co Ltd | アイランド露出型半導体装置 |
TW469609B (en) * | 2000-10-11 | 2001-12-21 | Ultratera Corp | Chipless package semiconductor device and its manufacturing method |
JP2002170917A (ja) * | 2000-11-30 | 2002-06-14 | Goto Seisakusho:Kk | 半導体装置用リードフレームの製造方法 |
CN1357919A (zh) * | 2000-12-11 | 2002-07-10 | 台湾通用器材股份有限公司 | 功率型半导体芯片的封装装置及封装方法 |
JP3895570B2 (ja) * | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
KR100857161B1 (ko) | 2001-01-31 | 2008-09-05 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체장치 및 그 제조방법 |
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2005
- 2005-12-12 JP JP2005357517A patent/JP5103731B2/ja active Active
-
2006
- 2006-06-13 US US11/451,372 patent/US8569871B2/en active Active
- 2006-10-30 CN CNB2006101425856A patent/CN100435328C/zh active Active
Also Published As
Publication number | Publication date |
---|---|
CN1983580A (zh) | 2007-06-20 |
US20070132110A1 (en) | 2007-06-14 |
JP2007165442A (ja) | 2007-06-28 |
CN100435328C (zh) | 2008-11-19 |
US8569871B2 (en) | 2013-10-29 |
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