JP7037368B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
- Publication number
- JP7037368B2 JP7037368B2 JP2018000954A JP2018000954A JP7037368B2 JP 7037368 B2 JP7037368 B2 JP 7037368B2 JP 2018000954 A JP2018000954 A JP 2018000954A JP 2018000954 A JP2018000954 A JP 2018000954A JP 7037368 B2 JP7037368 B2 JP 7037368B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- resin
- semiconductor device
- end surface
- outer end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 121
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000000034 method Methods 0.000 title claims description 16
- 229920005989 resin Polymers 0.000 claims description 187
- 239000011347 resin Substances 0.000 claims description 187
- 230000002093 peripheral effect Effects 0.000 claims description 62
- 238000007789 sealing Methods 0.000 claims description 43
- 238000007747 plating Methods 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 description 26
- 238000012986 modification Methods 0.000 description 13
- 230000004048 modification Effects 0.000 description 13
- 239000000463 material Substances 0.000 description 12
- 239000010949 copper Substances 0.000 description 4
- 239000003963 antioxidant agent Substances 0.000 description 3
- 230000003078 antioxidant effect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
- H01L2224/49173—Radial fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
図1~図5は、本発明の第1実施形態に係る半導体装置を示している。本実施形態の半導体装置A1は、リード群1、めっき層2、半導体素子3、複数のワイヤ4および封止樹脂5を備えている。本実施形態の半導体装置A1は、いわゆるQFN(Quad Flat Non-leaded package)タイプのパッケージであるが、本発明に係る半導体装置はこれに限定されず、たとえばSON(Small Outline Non-leaded package)等の様々なタイプのパッケージを採用しうる。
図13は、半導体装置A1の第1変形例を示す要部断面図である。本変形例の半導体装置A11においては、リード外端面15が曲面である。より具体的には、リード外端面15は、x方向に緩やかに膨出する凸曲面にである。リード外端面15は、一対の樹脂内側面54に近づくほど、x方向内方に位置する形状である。
図14は、半導体装置A1の第2変形例を示す要部断面図である。本変形例の半導体装置A12は、リード外端面15がx方向に対して僅かに傾いている。より具体的には、リード外端面15は、y方向図中左側から図中右側に向かうほど、x方向内方に位置するように傾いている。
図17は、本発明の第2実施形態に係る半導体装置を示す要部断面図である。本実施形態の半導体装置A2は、周端リード12の構成が上述した実施形態と異なっている。
1 :リード群
2 :めっき層
3 :半導体素子
4 :ワイヤ
5 :封止樹脂
10 :リードフレーム
11 :アイランドリード
12 :周端リード
13 :リード主面
14 :リード裏面
15 :リード外端面
16 :リード内端面
17 :リード側面
18 :溝部
21,22:裏面部
23 :内側面部
24 :内天面部
25 :内側面部
26 :底面部
31 :主面
32 :裏面
39 :接合層
50 :樹脂体
51 :樹脂主面
52 :樹脂裏面
53 :樹脂端面
54 :樹脂内側面
55 :樹脂内天面
91 :基板
92 :配線パターン
99 :はんだ
111 :主面
112 :裏面
120 :リード部材
151 :リード内側面
152 :リード内天面
161 :第1部
162 :第2部
163 :第3部
164 :第4部
171,172:曲面部
181 :内側面
182 :底面
221 :突出部
222 :露出面
241 :突出部
242 :露出面
541,542:曲面部
Db :ダイシングブレード
Hb :ハーフカットブレード
Claims (15)
- 複数のリードを含むリード群と、
半導体素子と、
前記リード群および前記半導体素子の少なくとも一部ずつを覆う封止樹脂と、を備えた半導体装置であって、
前記封止樹脂は、厚さ方向において互いに反対側を向く樹脂主面および樹脂裏面と、前記樹脂主面および前記樹脂裏面の間に位置し且つ前記厚さ方向に沿う樹脂端面と、を有し、
前記リード群は、前記樹脂裏面から露出するリード裏面および前記樹脂端面から露出するリード外端面を有する周端リードを含み、
前記リード外端面は、前記厚さ方向と直角である方向において前記樹脂端面に対して内方に位置しており、
前記封止樹脂は、前記樹脂端面と前記リード外端面とに接し且つ前記厚さ方向において前記樹脂裏面と同じ側を向く樹脂内天面を有し、
前記リード裏面を覆う裏面部を有するめっき層を備えており、
前記リード外端面は、前記めっき層から露出しており、
前記めっき層は、前記厚さ方向において前記リード外端面に対して前記リード裏面側に位置し且つ前記リード外端面に対して突出する突出部を含み、
前記突出部の先端縁は、前記厚さ方向視において前記樹脂端面と重なることを特徴とする、半導体装置。 - 前記突出部は、前記リード外端面に接し且つ前記厚さ方向において前記樹脂主面と同じ側を向く露出面を有する、請求項1に記載の半導体装置。
- 前記封止樹脂は、前記樹脂端面、前記樹脂内天面および前記露出面に接し且つ前記厚さ方向と直角である方向に沿う一対の樹脂内側面を有する、請求項2に記載の半導体装置。
- 前記リード外端面は、前記厚さ方向に沿う平坦面である、請求項2または3のいずれかに記載の半導体装置。
- 前記周端リードは、前記樹脂主面と同じ側を向くリード主面を有しており、
前記リード外端面は、前記リード主面に繋がる、請求項2ないし4のいずれかに記載の半導体装置。 - 前記リード外端面は、前記リード裏面に繋がる、請求項5に記載の半導体装置。
- 前記突出部は、前記裏面部に繋がっている、請求項6に記載の半導体装置。
- 前記周端リードは、前記リード裏面に繋がり且つ前記厚さ方向に沿うリード内側面と、前記リード内側面と前記リード外端面との間に介在し且つ前記厚さ方向において前記リード裏面と同じ側を向くリード内天面と、を有する、請求項2ないし4のいずれかに記載の半導体装置。
- 前記めっき層は、前記裏面部に繋がり且つ前記リード内側面を覆う内側面部と、前記内側面部に繋がり且つ前記リード内天面を覆う内天面部と、を有する、請求項8に記載の半導体装置。
- 前記突出部は、前記内天面部に繋がっている、請求項9に記載の半導体装置。
- 前記周端リードは、Cuからなる、請求項1ないし10のいずれかに記載の半導体装置。
- 前記めっき層は、Snを含む、請求項1ないし11のいずれかに記載の半導体装置。
- 前記リード群は、前記半導体素子が搭載され且つ前記周端リードから離間したアイランドリードを含んでおり、
前記半導体素子は、ワイヤによって前記周端リードと接続されている、請求項1ないし12のいずれかに記載の半導体装置。 - 前記封止樹脂は、前記厚さ方向視において矩形状であり、4つの前記樹脂端面を有しており、
前記リード群は、前記4つの樹脂端面に沿って配置された複数の周端リードを含む、請求項13に記載の半導体装置。 - リード群を含むリードフレームに半導体素子を搭載する工程と、
前記リードフレームおよび前記半導体素子の少なくとも一部ずつを覆う樹脂体を形成する工程と、
前記リードフレームのうち前記樹脂体から露出する部分にめっき層を形成する工程と、
前記リードフレームおよび前記樹脂体を切断することにより、樹脂端面を有する封止樹脂および前記樹脂端面から露出するリード外端面を有する周端リードを含むリード群を形成する工程と、
前記封止樹脂および前記めっき層を除去する度合いよりも前記周端リードを除去する度合いが大きいエッチング処理によって、前記リード外端面を前記樹脂端面に対して奥方に凹ませる工程と、
を備え、
前記めっき層は、前記厚さ方向において前記リード外端面に対して前記リード裏面側に位置し且つ前記リード外端面に対して突出する突出部を含み、
前記突出部の先端縁は、前記厚さ方向視において前記樹脂端面と重なることを特徴とする、半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018000954A JP7037368B2 (ja) | 2018-01-09 | 2018-01-09 | 半導体装置および半導体装置の製造方法 |
US16/238,077 US10707154B2 (en) | 2018-01-09 | 2019-01-02 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018000954A JP7037368B2 (ja) | 2018-01-09 | 2018-01-09 | 半導体装置および半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019121698A JP2019121698A (ja) | 2019-07-22 |
JP7037368B2 true JP7037368B2 (ja) | 2022-03-16 |
Family
ID=67159817
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018000954A Active JP7037368B2 (ja) | 2018-01-09 | 2018-01-09 | 半導体装置および半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10707154B2 (ja) |
JP (1) | JP7037368B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021141235A (ja) * | 2020-03-06 | 2021-09-16 | 株式会社東芝 | 半導体装置 |
US20220359352A1 (en) * | 2021-05-10 | 2022-11-10 | Texas Instruments Incorporated | Electronic package with concave lead end faces |
US12021011B2 (en) * | 2021-08-27 | 2024-06-25 | Texas Instruments Incorporated | Solder surface features for integrated circuit packages |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001257304A (ja) | 2000-03-10 | 2001-09-21 | Matsushita Electric Ind Co Ltd | 半導体装置およびその実装方法 |
JP2006165411A (ja) | 2004-12-10 | 2006-06-22 | New Japan Radio Co Ltd | 半導体装置およびその製造方法 |
JP2008112961A (ja) | 2006-10-04 | 2008-05-15 | Rohm Co Ltd | 半導体装置の製造方法および半導体装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003158235A (ja) * | 2001-11-20 | 2003-05-30 | Mitsui High Tec Inc | 半導体装置の製造方法 |
JP2005191240A (ja) * | 2003-12-25 | 2005-07-14 | Renesas Technology Corp | 半導体装置及びその製造方法 |
CN102473651B (zh) * | 2009-07-06 | 2014-12-17 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
US8329509B2 (en) * | 2010-04-01 | 2012-12-11 | Freescale Semiconductor, Inc. | Packaging process to create wettable lead flank during board assembly |
JP5762081B2 (ja) * | 2011-03-29 | 2015-08-12 | 新光電気工業株式会社 | リードフレーム及び半導体装置 |
JP2013225595A (ja) * | 2012-04-20 | 2013-10-31 | Shinko Electric Ind Co Ltd | リードフレーム及び半導体パッケージ並びにそれらの製造方法 |
JP5959386B2 (ja) * | 2012-09-24 | 2016-08-02 | エスアイアイ・セミコンダクタ株式会社 | 樹脂封止型半導体装置およびその製造方法 |
KR102178587B1 (ko) * | 2014-03-27 | 2020-11-13 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 장치의 제조 방법 및 반도체 장치 |
CN105405823A (zh) * | 2014-08-20 | 2016-03-16 | 飞思卡尔半导体公司 | 具有可检查的焊接点的半导体装置 |
US10366948B2 (en) * | 2016-03-17 | 2019-07-30 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing the same |
US10388616B2 (en) * | 2016-05-02 | 2019-08-20 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing the same |
-
2018
- 2018-01-09 JP JP2018000954A patent/JP7037368B2/ja active Active
-
2019
- 2019-01-02 US US16/238,077 patent/US10707154B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001257304A (ja) | 2000-03-10 | 2001-09-21 | Matsushita Electric Ind Co Ltd | 半導体装置およびその実装方法 |
JP2006165411A (ja) | 2004-12-10 | 2006-06-22 | New Japan Radio Co Ltd | 半導体装置およびその製造方法 |
JP2008112961A (ja) | 2006-10-04 | 2008-05-15 | Rohm Co Ltd | 半導体装置の製造方法および半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US20190214334A1 (en) | 2019-07-11 |
US10707154B2 (en) | 2020-07-07 |
JP2019121698A (ja) | 2019-07-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7228063B2 (ja) | 半導体装置 | |
KR101645771B1 (ko) | 반도체 장치 및 그 제조 방법 | |
JP4173346B2 (ja) | 半導体装置 | |
US5652461A (en) | Semiconductor device with a convex heat sink | |
JP6129645B2 (ja) | 半導体装置および半導体装置の製造方法 | |
US10930581B2 (en) | Semiconductor package with wettable flank | |
US7348659B2 (en) | Semiconductor device and method of manufacturing thereof | |
JP5802695B2 (ja) | 半導体装置、半導体装置の製造方法 | |
JP5100967B2 (ja) | リードフレーム、これを利用した半導体チップパッケージ及びその製造方法 | |
KR20160136208A (ko) | 반도체 장치의 제조 방법 및 반도체 장치 | |
JP2014007363A (ja) | 半導体装置の製造方法および半導体装置 | |
JP7089388B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP7037368B2 (ja) | 半導体装置および半導体装置の製造方法 | |
US20230207432A1 (en) | Semiconductor device and method for manufacturing the same | |
JP2005244035A (ja) | 半導体装置の実装方法、並びに半導体装置 | |
JP5103731B2 (ja) | モールドパッケージ | |
JP2004363365A (ja) | 半導体装置及びその製造方法 | |
US20120086133A1 (en) | Semiconductor Device And Semiconductor Device Manufacturing Method | |
JP4243270B2 (ja) | 半導体装置の製造方法 | |
KR20120018756A (ko) | Ic 패키지용 리드프레임 및 제조방법 | |
JP2017183417A (ja) | 半導体装置 | |
KR20210000777U (ko) | 반도체 패키지 | |
JP4979661B2 (ja) | 半導体装置の製造方法 | |
WO2023228898A1 (ja) | リードフレーム及びその製造方法 | |
JP4747188B2 (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20201208 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20210906 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20210928 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20211116 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20220222 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20220304 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7037368 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |