CN110246823B - 包含结合垫和结合导线或夹子的半导体器件 - Google Patents

包含结合垫和结合导线或夹子的半导体器件 Download PDF

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CN110246823B
CN110246823B CN201910175642.8A CN201910175642A CN110246823B CN 110246823 B CN110246823 B CN 110246823B CN 201910175642 A CN201910175642 A CN 201910175642A CN 110246823 B CN110246823 B CN 110246823B
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bonding
semiconductor device
supplemental
supplemental structure
clip
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CN110246823A (zh
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A·毛德
H-J·舒尔策
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

半导体器件(500)包含结合垫(300)，结合垫(300)包含具有基底层(317)的基底部分(310)。结合导线或夹子(410)结合到结合垫(300)的主表面(301)的结合区域(305)。补充结构(350)与邻接结合区域(305)的基底部分(310)直接接触。补充结构(350)的比热容高于基底层(317)的比热容。

Description

包含结合垫和结合导线或夹子的半导体器件
技术领域
本发明涉及半导体领域，并且尤其是涉及半导体器件领域。
背景技术
诸如功率半导体二极管、IGFET(绝缘栅场效应晶体管)和IGBT(绝缘栅双极晶体管)的功率半导体器件的半导体封装典型地具有金属引线，金属引线允许功率半导体器件连接到电路板或别的电子器件。结合导线将金属引线与直接形成于半导体管芯上的接触垫电连接，并桥接功率半导体器件的芯片上布线与外部布线之间的尺度差异。对于导线结合，典型地将结合导线定位在结合垫上，并且尖端或楔形件迫使导线到结合垫上。同时，将热、超声能量或别的类型的辐射施加到结合垫和结合垫上的导线段，以在结合导线与结合垫之间形成冶金结合。结合垫必须足够耐用以适应在结合工艺期间施加到半导体芯片上的机械应变。此外，希望结合垫和结合导线的高的热容和/或耐用性以改善半导体器件的短路和雪崩耐用性。
US2014/0367859A1描述了一种用于具有铜结构的半导体芯片的半导体壳体。在焊料掩模的开口中设有含锡层，并且在含锡层与铜结构之间设有由镍制成的阻挡层。在含锡层上结合有导线。阻挡层防止在含锡层中的锡与含铜层的铜之间形成金属间化合物。US2017/0 092 562A1描述了一种铜板，其以“管芯结合材料”与半导体芯片的表面连接。结合导线穿过铜板中的开口引导。
存在对具有高的热和机械耐用性的可靠半导体器件的需要。
发明内容
本公开涉及一种半导体器件，其包含结合垫，结合垫包含基底部分和主表面。基底部分具有基底层。主表面具有结合区域。结合导线或夹子结合到结合区域。补充结构与邻接结合区域的基底部分直接接触。补充结构的比热容高于基底层的比热容。
本公开还涉及制造半导体器件的方法。该方法包含在半导体部分上形成结合垫基底部分。基底部分包含基底层。形成包含结合区域的结合垫主表面。将结合导线或夹子结合到结合区域。直接于基底部分上形成补充结构。补充结构的比热容高于基底层的比热容。
本公开还涉及一种半导体器件，其包含包含掺杂区域的半导体部分。结合垫包含与掺杂区域直接连接的基底部分。补充结构与基底部分直接接触。补充结构包含芯部分和衬里部分。芯部分含有银。衬里部分将芯部分与基底部分分开。
在阅读以下具体实施方式和查看附图之后，本领域技术人员将认识到另外的特征和优点。
附图说明
包含附图以提供对实施例的进一步理解，并且附图并入于本说明书中并构成本说明书的一部分。附图示出了本公开的实施例，并且与描述一起用于解释实施例的原理。将易于意识到其它实施例和意图的优点，因为通过参考以下详细描述，它们变得更好理解。
图1A是根据实施例的半导体器件的部分的示意性平面视图，该半导体器件包含结合到结合垫上的结合导线或夹子以及邻接结合导线或夹子的结合脚的具有高的热容的补充结构。
图1B是图1A的半导体器件部分的垂直横截面视图。
图2A是根据实施例的半导体器件的部分的示意性水平横截面视图，该实施例组合了楔形结合和由酚醛树脂制成的补充结构。
图2B是图2A的半导体器件部分的垂直横截面视图。
图3A是根据实施例的半导体器件的部分的示意性水平横截面视图，该实施例将带状结合与包含芯部分和层部分的补充结构相结合。
图3B是图3A的半导体器件部分的垂直横截面视图。
图4A是根据实施例的半导体器件的部分的示意性水平横截面视图，该实施例将包含直接在基底部分与帽部分之间的补充结构的结合垫与球结合组合。
图4B是图4A的半导体器件部分的垂直横截面视图。
图5A是根据实施例的半导体器件的部分的示意性平面视图，该实施例涉及在结合导线的垂直投影中具有缝隙的补充结构。
图5B是根据实施例的半导体器件的部分的示意性平面视图，该实施例涉及具有开口的补充结构。
图5C是根据实施例的半导体器件的部分的示意性平面视图，该实施例涉及在相邻的结合脚之间具有分开的垫区段(section)的补充结构。
图5D是根据实施例的半导体器件的部分的示意性平面视图，该实施例涉及在结合导线的纵向投影中具有分开的垫区段的补充结构。
图6A是根据涉及TO-220封装的另一实施例的具有补充结构的半导体器件的部分的示意性平面视图。
图6B是根据实施例的半导体器件的部分的示意性平面视图，该实施例涉及在导线结合之后形成的补充结构。
图6C是根据实施例的半导体器件的部分的示意性垂直横截面视图，该实施例涉及包裹结合脚的补充结构。
图7A是半导体衬底的部分的示意性横截面视图，用于示例制造根据实施例的半导体器件的方法，该半导体器件包含邻接结合脚的补充结构，该实施例中，在导线结合之前，在形成结合垫之后，形成补充结构。
图7B是图7A的半导体衬基底分的在形成补充结构之后的示意性垂直横截面视图。
图7C是从图7B的半导体衬基底分获得的半导体器件的部分的，在将半导体管芯密封在保护外壳中之后的示意性垂直横截面视图。
图8A是半导体器件的部分的示意性横截面视图，用于示例制造根据在导线结合之后形成补充结构的实施例的半导体器件的方法。
图8B是图8A的半导体器件部分的，在将半导体器件密封在保护外壳中之后的示意性垂直横截面视图。
图9是根据另一实施例的具有结合垫的半导体器件的部分的示意性横截面视图，该结合垫包含补充结构，该补充结构具有含银芯部分。
图10是根据包含由铝合金制成的帽部分的实施例的具有结合垫的半导体器件的部分的示意性横截面视图，该结合垫包含含银芯部分。
图11是根据涉及半导体二极管的实施例的具有结合垫的半导体器件的部分的示意性垂直横截面视图，该结合垫包含含银芯部分。
图12A是根据实施例的半导体器件的部分的示意性垂直横截面视图，该实施例中，结合垫的帽部分仅(exclusively)沿着结合垫的横向外表面形成。
图12B是根据实施例的半导体器件的部分的示意性垂直横截面视图，该实施例中，帽部分独立于结合垫的基底部分形成。
图12C是根据实施例的半导体器件的部分的示意性垂直横截面视图，该实施例中，帽部分和结合垫的基底部分在相同的工艺中被图案化。
图13A是半导体衬底的部分的示意性垂直横截面视图，用于示例根据实施例的形成具有补充结构的结合垫的方法，该补充结构具有由银制成的芯部分，该实施例中，帽部分和基底部分形成于图案化补充结构的芯部分之后的相同的图案化步骤中。
图13B是图13A的半导体衬基底分的在形成盖帽(capping)层之后的示意性垂直横截面视图。
图13C是图13B的半导体衬基底分的在图案化帽层和基底层之后的示意性垂直横截面视图。
图14A是半导体器件的部分的示意性垂直横截面视图，用于示例制造根据实施例的半导体器件的方法，该实施例中，在形成芯层之后彼此独立地图案化结合垫的帽部分和基底部分。
图14B是图14A的半导体衬基底分的在形成盖帽层之后的示意性垂直横截面视图。
图14C是图14B的半导体衬基底分的在图案化帽层之后的示意性垂直横截面视图。
具体实施方式
在以下具体实施方式中，参考了附图，附图形成了具体实施方式的一部分，并且附图中通过示例的方式示出了其中可以实践实施例的特定实施例。应当理解，在不脱离本公开的范围的情况下，可以利用其它实施例并且可以进行结构或逻辑上的改变。例如，针对一个实施例示例或描述的特征能够用于其它实施例或与其它实施例结合，以产生又一个实施例。意图本公开包含这些修改和变化。使用特定语言描述范例，其不应被解释为限制所附权利要求的范围。附图未按比例缩放，并且仅用于示例性目的。如果没有另外说明，相应的元件在不同的附图中由相同的参考标记表示。
术语“具有”，“含有”，“包含”，“包括”等是开放的，并且术语指示陈述的结构、元件或特征的存在，但不排除附加元件或特征。除非上下文清楚地另外指示，否则意图冠词“一”，“一个”和“该”包含复数以及单数。
附图通过邻接掺杂类型“n”或“p”指示“-”或“+”来示例相对掺杂浓度。例如，“n-”意指掺杂浓度低于“n”掺杂区域的掺杂浓度，而“n+”掺杂区域具有比“n”掺杂区域更高的掺杂浓度。具有相同相对掺杂浓度的掺杂区域不必然具有相同的绝对掺杂浓度。例如，两个不同的“n”掺杂区域可以具有相同或不同的绝对掺杂浓度。
图1A示出了在结合连接的区域中的半导体器件500的平面视图。图1B是沿图1中的线B-B的半导体器件500的垂直横截面视图。
半导体器件500适合用于功率应用，例如功率半导体二极管、IGFET(例如，通常意义上的MOSFET(金属氧化物半导体FET)，包含具有金属栅极的IGFET以及具有多晶硅栅极的IGFET)、IGBT、MCD(MOS控制的二极管)或智能功率半导体器件，其包含CMOS(互补金属氧化物半导体)电路，诸如除功率半导体单元之外的传感器电路和/或控制电路。
半导体器件500基于由诸如硅(Si)、锗(Ge)、硅锗(SiGe)、碳化硅(SiC)或AIIIBV半导体的单晶半导体材料制成的半导体部分100。
半导体部分100的前侧处的第一表面101是平面的或由共面表面区段限定，并且平行于半导体部分100背面上的第二表面。在图1A的平面中，半导体部分100可以具有矩形形状，边缘长度在几毫米的范围中。第一表面101的法线限定垂直方向，正交于垂直方向的方向是水平方向。
半导体部分100的前侧处的结合垫300电连接到半导体部分100中的一个或多个掺杂区域111。
例如，掺杂区域111可以是功率半导体二极管的阳极区域，并且结合垫300可以直接毗连第一表面101以与掺杂区域111形成欧姆接触。根据其它实施例，层间电介质可以将结合垫300与半导体部分100分开并且结合垫300的接触部分延伸穿过层间电介质中的开口并且将结合垫300与多个分开的掺杂区域111电连接，该多个分开的掺杂区域111可以包含晶体管单元的源极区带(zone)和体区域。
结合垫300包含基底部分310，其可以是同质(homogeneous)结构，例如，由含铝合金制成，例如AlCu、AlSi、AlSiCu，或者其可以具有分层结构，该分层结构包含不同金属的子层，例如，具有硅化物区段的接触层、含有钛和钽中的至少一种的阻挡层、用于填充窄接触部分的填充层(例如钨层)和/或由铝或铝合金(例如AlCu、AlSi或AlSiCu)制成的基底层。
结合导线或夹子410在结合区域305中结合在结合垫300的主表面301的水平部分上。
结合导线或夹子410可以是直径在从例如25是直至500直径范围中的圆形导线，具有近似矩形横截面形状的扁带状导线，其中横截面的长边截面至少是短边的两倍大。圆形或扁导线可以含有金(Au)、银(Ag)、铜(Cu)和铝(Al)中的至少一种作为主成分(单种或多种)，例如，含有Al、Au、Ag和Cu中的一种、两种或更多种的合金。结合导线或夹子410可以是铜夹子，其厚度为至少50μm并且横截面积为至少0.5mm2。
结合工艺可在一定程度上使直接结合到主表面301上的结合导线或夹子410的部分变形，其中结合的部分形成结合脚415。结合脚415可以是结合导线或夹子410的机械弄扁的区段或结合导线或夹子410的暂时熔化并再凝固的材料的锥形或球。
结合导线或夹子410的环形部分411将结合垫300上的结合脚415与结合导线或夹子410的在金属引线或承载板或相同或另一半导体管芯上的另一结合脚连接。
在楔形结合的情况下，结合脚415在平行于结合导线或夹子410的纵向方向的方向上具有第一长度y1，并且在与结合导线或夹子410的纵向方向正交的方向上具有第一宽度x1。结合导线或夹子410还可包含尾部部分419，尾部部分419形成在与环形部分411相对的侧从结合脚415突出的线头(stub)。
在球结合的情况下(图1A和图1B中未示出)，结合脚415可以具有基本上圆形的形状，导致相等的第一长度y1和第一宽度x1。在结合导线或夹子410朝向相同或另一半导体管芯的金属引线或承载板上的另外的结合脚引导之前，结合导线或夹子410可具有环形部分411的垂直起点。在结合导线或夹子410包含铜夹子的情况下，结合工艺可以包含回流焊接。
结合区域305是保留用于铜夹子的导线结合或回流焊接的结合垫300的主表面301的部分。结合区域305的尺寸取决于诸如结合技术、结合导线或夹子410的横截面面积以及结合工具的放置精度的参数。结合区域305可以具有平行于结合导线或夹子410的纵向轴线的第二长度y2和与结合导线或夹子410的纵向轴线正交的第二宽度x2。第二长度y2可以是结合脚415的第一长度y1的至少150％或者至少200％。第二宽度x2可以是第一宽度x1的至少150％或至少200％，例如，至少2，例或至少5至少。
邻接主表面301上的结合脚415的补充结构350具有比基底部分310的基底层317更高的比热容。例如，补充结构350的比热容至少为3.5J/cm3K，例如，大于3.7J/cm3K。
补充结构350邻接结合导线或夹子410形成，其中结合导线和夹子410以及补充结构350都形成于结合垫300的与半导体部分100相对的同一侧。补充结构350可以直接毗连结合导线和夹子410的部分，例如，结合脚415，或者可以与结合导线和夹子410以及结合脚415水平地分开些许微米，例如，至多50μm、至多30μm，例或至多5μm至多并且至少0.5μm，例如至少1μm。
补充结构350可以是同质的，或者可以包含芯部分和至少覆盖芯部分的衬里部分。补充结构350可以由导电材料制成，诸如比热容约为3.95J/cm3K的镍(Ni)，或者由无机电介质材料制成，诸如比热容约为4.9J/cm3K的碳化钨、钴镍氧化物、比热容约为4.44J/cm3K的黄玉(Al2 [6][(F，OH)2|SiO4])和比热容约为4.01J/cm3K的氟化锂(LiF)，其中对于每种提到的材料，热容的精确值取决于其它物理变量，诸如沉积条件和密度。
补充结构350可以是连续的或精细图案化的，例如，可以形成窄的规则网格，或者可以包含隔离子结构，例如岛，的密集的规则图案。例如，补充结构350包含窄的镍网格。
根据实施例，补充结构350包含具有至少3.0J/cm3K的比热容的酚醛树脂，例如，约3.77J/cm3K。除酚醛树脂外，补充结构350可包含导热率高于酚醛树脂的材料。
在补充结构350在结合工艺之前形成的情况下，补充结构350仅形成于结合区域305外部的空白区域306中，其被保留用于结合工艺。空白区域306还可以排除沿着基底部分310的横向外表面313延伸的垫边缘区域307，其中垫边缘区域307的宽度y3可以是至少1少m。
补充结构350可以覆盖整个空白区域306或仅覆盖其部分。例如，补充结构350可以仅形成于每个结合脚415的一侧、两侧、三侧上或结合脚415的所有四侧上。
在补充结构350形成于结合工艺之后的情况下，空白区域306可以向上延伸到基底部分310的横向外表面313，并且补充结构350可以包裹并直接涂覆包含结合脚415的结合导线或夹子410的部分。
如发明人所观察到的，在一些功率半导体器件中，在一定的电过应力期间发生的热应力导致邻接结合脚415而不是直接在结合脚415以下的结合垫300部分熔化。局部熔化指示邻接结合脚415但不直接在结合脚415以下的局部温度最大值，其中结合导线或夹子410耗散热能。补充结构350局部地增加了结合脚415周围的热容，暂时吸收在重复的雪崩或短路事件期间局部过量的热能，并且在雪崩与短路事件之间逐渐释放所存储的热能。
补充结构350形成局部暂时热存储器，其作为靠近结合脚415的局部热沉是有效的，从而防止结合垫的局部熔化，并增加半导体器件500的雪崩和短路耐用性。
由于负载电流直接从结合垫300流到结合导线或夹子410，所以负载电流避开了补充结构350。因此，补充结构350的材料的比电阻可能是无关紧要的并且可以比对于结合垫300的更高。具有高比电阻的高欧姆材料和电介质材料对器件性能没有不利影响。可以考虑到热容和机械强度而仅选择用于补充结构的材料，并且用于补充结构的材料可以适应半导体部分100的温度膨胀系数。
图2A至2B组合楔形结合与形成于结合垫300上的补充结构350，其可以形成与具有平面栅极结构150的晶体管单元TC电连接的第一负载电极。
半导体器件500可以是IGFET、IGBT或MCD，并且包含彼此并联电连接的多个晶体管单元TC。
晶体管单元TC沿着半导体部分100的第一表面101形成于半导体器件500的前侧。晶体管单元TC可以控制在前侧的两个负载电极之间的负载电流流动。示例的实施例涉及垂直器件，其中负载电流流动在前侧的第一负载电极与背面的第二负载电极之间，其中在晶体管单元TC与和第一表面101相对的第二表面102之间，半导体部分100包含漂移结构130。漂移结构130可以包含轻掺杂漂移区带131和沿着第二表面102的重掺杂接触部分139。接触部分139中的掺杂剂浓度足够高以形成与直接毗连第二表面102的第二负载电极390的欧姆接触。在半导体器件500是IGFET的情况下，接触部分139可以与漂移区带131具有相同的导电类型，在半导体器件500是IGBT的情况下，接触部分139可以是相反导电类型的层，并且在半导体器件500是RC-IGBT的情况下，接触部分139可以包含沿着至少一个水平方向交替的两种导电类型的区带。场阻止(field stop)或缓冲层137可以直接形成于(夹在)漂移区带131与接触部分139之间，其中场阻止或缓冲层137与漂移区带131形成单极结且与接触部分139形成单极结或pn结。场阻止或缓冲层137中的平均掺杂剂浓度至少是漂移区带131中的两倍高，并且至多是接触部分139中的一半高。
晶体管单元TC包含体区域120，体区域120与漂移结构130形成第一pn结pn1并且与直接形成于第一表面101与体区域120之间的源极区带110形成第二pn结pn2，其中体区域120沿第一表面101分开源极区带110与漂移结构130。
晶体管单元TC还包含栅极结构150，栅极结构150包含导电栅极电极155，导电栅极电极155可以包含重掺杂多晶硅层或含有金属的层或由重掺杂多晶硅层或含有金属的层构成。栅极电介质159将栅极电极155与半导体部分100分开，其中栅极电介质159沿着第一表面101将栅极电极155电容性地耦合到体区域120的沟道部分。
栅极电介质159可以包含以下或由以下构成：半导体氧化物，例如，热生长或沉积的氧化硅；氮化硅，例如，沉积或热生长的氮化物；半导体氮氧化物，例如，氮氧化硅；或其组合。
栅极结构150是沿着第一表面101形成于半导体部分100外部的横向栅极，其中栅极结构150可以包含多个栅极条纹或者可以形成栅极网格。
对于以下描述，漂移区带131和源极区带110是n型的，且体区域120是p型的。如下面针对n沟道晶体管单元TC概述的类似考虑适用于具有基于n型体区域120、p型漂移区带131和p型源极区带110的p沟道晶体管单元的实施例。
当施加到栅极电极155的电压超过预设的阈值电压时，电子在体区域120的沟道部分中累积并沿着栅极电介质159形成反转沟道。反转沟道使第一pn结pn1对电子短路，并且单极负载电流在源极区带与接触部分139之间流动。在IGBT的情况下，单极负载电流在由体区域120、漂移区带131和接触部分139的p型区段形成的pnp结构中触发双极电流。
层间电介质210将栅极电极155与结合垫300分开。结合垫300可以形成用于负载电流的第一负载电极。结合垫300的接触部分309延伸穿过层间电介质210和栅极结构150中的开口到达或进入半导体部分100并直接毗连源极区带110和体区域120。接触部分309是结合垫300的基底部分310的部分。
结合垫300的基底部分310至少包含由铝(Al)或铝合金，例如AlCu、AlSiCu或AlSi，制成的基底层317。基底层317可以直接毗连半导体部分100。
根据示例的实施例，基底部分310可以包含一个或多个另外的层，例如形成硅化物的金属的接触层311，例如钽(Ta)或钛(Ti)。接触层311可以包含形成与半导体部分100的低欧姆接触的硅化物部分和沿着层间电介质210的非硅化部分。由钛、钽、氮化钛(TiN)和氮化钽(TaN)中的至少一种制成的阻挡层312可以直接形成于接触层311上，并防止掺杂剂扩散出半导体部分100和/或金属原子从结合垫300扩散到半导体部分100中。由例如钨(W)制成的填充层315可以形成接触部分309的芯，并且还可以与栅极结构150和接触部分309以上的水平顶表面形成连续层。基底层317可以直接毗连填充层315。
金属间电介质220可以在横向方向上直接毗连结合垫300，并且可以覆盖邻接结合垫300的层间电介质210和/或半导体部分100的区段。金属间电介质220可以将结合垫300与相邻的结合垫和/或与半导体部分100的横向外表面分开。例如，金属间电介质220可以含有聚酰亚胺、硅酮或氮化硅。
结合导线或夹子410结合到结合垫300的主表面301上。结合导线或夹子410的直径d1可以在从25μm到500μm的范围中。结合脚415直接毗连主表面301。
楔形结合可以通过使结合导线或夹子410的部分变扁而形成结合脚415，其中尾部部分419可以在环形部分411的相对侧处从结合脚415突出。球结合可以形成结合脚415，其形状近似于没有尾部部分的平底球。环形部分411将半导体器件500的结合垫300上的结合脚415与半导体器件500的金属引线上的另一结合脚连接。结合导线或夹子410可包含以下至少一种作为主成分：铝(Al)、金(Au)、银(Ag)和铜(Cu)。
在结合区域305之外并且与结合导线或夹子410间隔开，由酚醛树脂制成的补充结构350与主表面301直接接触。补充结构350可以在结合导线或夹子410的纵向投影中，在环形部分411以下和/或在结合脚415的至少一侧上。
酚醛树脂具有约3.77J/cm3K的相对高的比热容，是半导体工业中常用的材料并且显示出高的热稳定性。可以通过使用沉积在酚醛树脂层上的光阻掩模或通过添加光活性基团对酚醛树脂进行改性以使得改性的酚醛树脂层可以通过光刻图案化而无需另外的光致抗蚀剂层来图案化酚醛树脂层。替代地或另外，酚醛树脂可与具有较高导热率的组分混合。补充结构350从酚醛树脂的垂直延伸可以在从5μm至几百μm的范围中，例如在从10μm至100μm的范围中。
补充结构350具有比结合垫300的主要部分更大的比热容，并且避免了局部过热，该局部过热否则在重复雪崩和/或短路事件的情况下在结合脚415附近发生。
密封结构490将半导体部分100和结合导线或夹子410密封在保护外壳中。密封结构490可包含模塑料。例如，密封结构490可包含环氧树脂、诸如硅酮凝胶的灌封凝胶、玻璃或陶瓷凝胶。模塑料典型地被选择以确保半导体部分100的电阻隔能力和/或半导体部分100的电绝缘和/或保护半导体部分100免受湿气影响。典型地，模塑料的选择源于权衡考虑机械耐用性、重量、材料成本和制造效率。硅酮的比热容为约1.6J/cm3K至约1.7J/cm3K，且环氧树脂的比热容在从1.2J/cm3K至2.0J/cm3K的范围中。相反，例如酚醛树脂的补充结构350的比热容典型地比密封结构490的模塑料的比热容高至少30％，例如至少50％或甚至超过100％，例如，至少3.0J/cm3K。
图3A至3B组合了带状结合与补充结构350，补充结构350包含与功率半导体二极管组合的包封芯部分355。
代替晶体管单元TC，半导体部分100可以包含形成阳极区域112的单个掺杂区域，阳极区域112与漂移结构130形成二极管结pn0。结合垫300的基底部分310直接毗连半导体部分100的第一表面101。基底部分310包含由铝或铝合金制成的基底层317，其中基底层317可以直接毗连阳极区域112。基底部分310还可以包含接触层311，接触层311在至半导体部分100的界面处含有形成金属硅化物的金属，例如，硅化钛(TiSi)。
结合导线或夹子410可以是具有近似矩形横截面区域的夹子或带，其中结合导线或夹子410的宽度b1是结合导线或夹子410的厚度b2的至少两倍或至少三倍。
补充结构350包含由辅助材料制成的芯部分355，该辅助材料具有比基底层317高的比热容。辅助材料具有高比热容，例如高于铜。辅助材料可以是含有金属的材料。芯部分355可以由以下中的一种制成或可以含有以下中的至少一种作为主成分：银、钨、钼、钴、镍、氧化镍、镍合金、碳化钨、黄玉、氟化锂或酚醛树脂。
补充结构350还可包含衬里部分359，衬里部分359可至少覆盖芯部分355的顶表面351，其中顶表面351平行于第一表面101。另外，衬里部分359可覆盖芯部分355的侧壁353，其中侧壁353相对于第一表面101倾斜。
衬里部分359可以使至少抵靠包封结合导线或夹子410和结合垫300的密封结构490的辅助材料钝化，并且可以由稳定的阻挡材料制成或可以含有稳定的阻挡材料作为主成分，稳定的阻挡材料诸如是钛、钽或钯、或金。例如，衬里部分359可以与含有Cu和Ag中的至少一种的芯部分355组合。
图4A和4B将球结合与补充结构350组合，其中补充结构350位于半导体器件500的结合垫300的帽部分320与基底部分310之间，其中半导体器件包含具有场板电极165的沟槽栅极结构150。
沟槽栅极结构150从第一表面101延伸到漂移区带131中。栅极电极155形成于沟槽栅极结构150的面向第一表面101的部分中。栅极电介质159将栅极电极155与半导体部分100分开，并且将栅极电极155电容性耦合到体区域120的垂直沟道部分。在栅极电极155与第二表面102之间，沟槽栅极结构150包含导电场板电极165。场电介质169将场板电极165与漂移区带131分开，且分开电介质156将栅极电极155与场板电极165分开。
结合脚415由结合导线或夹子410的尖端上的熔化部分形成，并且可具有近似椭圆形的水平和垂直横截面区域，该区域具有平行于纵向轴线的近似相等的第一长度l1和与结合导线或夹子410的纵向轴线正交的第一宽度x1。
补充结构350可以完全围绕结合区域305并且可以限定结合区域305的边界。在结合区域305外部，补充结构350可以位于结合垫300的帽部分320与基底部分310之间。帽部分320可包含铝或诸如AlCu、AlSi或AlSiCu的铝合金的主帽部分。
衬里部分359可将补充结构350的芯部分355与基底部分310和帽部分320均分开。
在结合区域305中，帽部分320可以直接毗连基底部分310，或者衬里部分359的空闲(idle)区段可以直接形成于帽部分320与基底部分310之间。
芯部分355可以由银(Ag)制成。芯部分355的垂直延伸可以在从5μm至100μm的范围中，例如在5μm至20μm的范围中。衬里部分359可以由钛(Ti)制成，其中衬里部分359作为粘合层是有效的并且抑制银枝晶(silver dendrite)的形成。衬里部分359的厚度可以在从20nm至100nm的范围中。
补充结构350可以在结合垫300的在结合区域305外部，并且可选地在垫边缘区域307外部的整个空白区域306上延伸，或者可以仅形成于空白区域306的子部分中，如图5A至5D中示例的。
在图5A中，补充结构350形成于完整的空白区域306中，除结合区域305的在环形部分411的方向上的水平投影之外，使得补充结构350示出在结合导线或夹子410的垂直投影中打开的缝隙。
在图5B中，补充结构350覆盖垫边缘区域307和结合区域305外部的完整空白区域306。
在图5C中，补充结构350包含在结合脚415的相对侧的若干分开部分，其中补充结构350的分开部分形成于与结合导线或夹子410的纵向轴线正交的方向上。
在图5D中，补充结构350包含在结合导线或夹子410的水平投影中在环形部分411的相对侧的分开或互连部分。
图5A至5D主要涉及可在导线结合之前形成的补充结构350。以下图图6A至6C主要涉及在导线结合之后形成的补充结构350。
图6A示意性地示出了具有半导体管芯501以及用于诸如TO-220(晶体管轮廓)封装或类似封装的分立器件的典型封装中的引线组件710的半导体器件500，半导体管芯501包含半导体部分100和形成源极电极的结合垫300。引线组件710可包含栅极引线715、源极引线711和漏极引线712，栅极引线715、源极引线711和漏极引线712是通过将栅极引线715和源极引线711与漏极引线712机械分开而从公共引线框架形成的，例如，在封装工艺期间。
半导体管芯501可以背面向下焊接到引线组件710的形成漏极引线712的部分上。第一结合导线或夹子410将半导体管芯501的前侧的栅极垫380与栅极引线715电连接。一个、两个或更多个第二结合导线或夹子410可以将结合垫300与源极引线711电连接。可以通过分配器尖端施加补充结构350，分配器尖端主要接近结合导线和夹子410的结合脚415但与结合导线和夹子410的结合脚415分开，并且在第二结合导线与夹子410的末端部分之间。替代地，补充结构350可以与结合导线和夹子410接触，并且可以部分地或完全地覆盖结合脚415。
在图6B中，分配器尖端可以形成补充结构350，其中分配器尖端可以直接位于结合导线或夹子410的结合脚415上或紧邻结合脚415，例如，在相邻的结合脚415之间，使得补充结构350直接接触结合脚415。根据示例的实施例，一个连续补充结构350包裹几个结合导线或夹子410的包含结合脚415的部分。
图6C的半导体器件500与图2A至2B中的半导体器件不同，因为补充结构350在导线结合之后形成，其中补充结构350可以主要形成于结合区域305中。补充结构350可以与结合脚415直接接触并且可以部分地或完全地包覆在结合导线或夹子410的环形部分411的毗连区段周围以及在尾部部分419周围。在球结合的情况下，补充结构350可以包覆球结合脚415的至少部分。如示例的，补充结构350可以与金属间电介质220间隔开，或者可以与金属间电介质220重叠。
图7A至7C涉及形成具有补充结构350的结合垫300的方法，其中补充结构350形成于晶片级。
图7A示出了在半导体晶片900(例如，硅晶片)的器件区域610中形成的多个半导体管芯中的一个半导体管芯的部分。每个半导体管芯可以包含晶体管单元TC以及至少结合垫的与半导体管芯的半导体部分100中的源极区带110和体区域120电连接的基底部分310。金属间电介质220可以分开相邻的结合垫300，例如，相邻器件区域690的源极电极的结合垫300或者用于相同器件区域690的源极电极和栅极电极的结合垫300。
补充层可以沉积在基底部分310的顶部和金属间电介质220上，例如通过例如酚醛树脂的模板(stencil)印刷或丝网印刷。根据另一实施方案，通过光刻对补充层进行图案化，其中，例如，补充层可以由镍、氧化镍、镍合金、碳化钨、钨、钼或银制成。
例如，抗蚀剂层可以沉积在补充层上。通过掩模曝光于抗蚀剂材料的光敏基团被改性的波长的辐射来图案化抗蚀剂层，并且去除或显影工艺选择性地去除抗蚀剂层的改性部分或未改性部分。然后将抗蚀剂层的图案成像到下面的补充层中。去除图案化的光致抗蚀剂掩模的残余物。
根据另一实施例，补充结构350由酚醛树脂制成，其中酚醛树脂可以通过添加光活性基团而被改性，使得可以通过光刻直接图案化补充结构350。
图7B示出了通过图案化补充层而获得的补充结构350。补充结构350覆盖器件区域610中的结合垫300的基底部分310的区段。补充结构350暴露结合垫300的主表面301的结合区域305。
切割半导体晶片900，其中将半导体管芯彼此分开。每个半导体管芯可以附接到例如引线框架，并且每个半导体管芯的结合垫300通过导线结合电连接到引线框架的引线。然后用包封半导体管芯、结合导线或夹子410和引线框架的部分的模塑料密封半导体管芯和结合导线或夹子410。
图7C示出了半导体器件500，其包含密封结构490，该密封结构490包围结合导线或夹子410以及具有半导体部分100和结合垫300的半导体管芯。
图8A至8B涉及在管芯结合之后在器件级上施加补充结构350的方法，其中管芯结合可以包含焊接、粘接结合或烧结。
通过在没有如图7A中示例的补充结构350的情况下切割半导体晶片900来形成半导体管芯501。半导体管芯501的结合垫300导线结合到引线框架的引线。
图8A示出了导线结合到结合垫300的主表面301上的结合导线或夹子410。补充结构350可以是在导线结合工艺之前模板印刷的或丝网印刷的。在结合工艺之后，可以通过结合垫300的主表面301的空白区域306中的分配器尖端分配补充结构350。密封工艺形成包封半导体管芯501、引线的部分以及结合导线或夹子410的密封结构490。
图8B示出了补充结构350，其可以例如由酚醛树脂制成。
在图9至11中，结合垫300包含具有芯部分355的补充结构350，芯部分355可以独立于如先前实施例中描述的结合区域305的存在而形成。
图9涉及具有多个晶体管单元TC的半导体器件500，如以上参照图2B描述的，该多个晶体管单元TC并联电连接并且具有平面栅极结构150。结合垫300的基底部分310可以包含接触层311、阻挡层312、填充层315和由铝或铝合金制成的基底层317，如以上参照图2A和2B描述的。
补充结构350直接形成于基底部分310上。补充结构350包含由银制成的芯部分355或由主成分是银的材料制成的芯部分355。补充结构350可以延伸越过基底部分310的整个顶表面或跨越顶表面的子区域。结合垫300可以通过具有或不具有补充结构350的结合垫300的区域中的结合导线、压接触部、或焊接接触部电连接到另外的导电结构。
芯部分355的垂直延伸a5可以在从5μm至100μm的范围中，例如从5μm至20μm。第一衬里部分3591可以直接形成于芯部分355与基底部分310之间。第一衬里部分3591改善了基底部分310与芯部分355之间的粘合。第一衬里部分3591的垂直延伸a51可以是例如，在从20nm至100nm的范围中。第一衬里部分3591可以由钛和钽中的至少一种制成或可以包含钛和钽中的至少一种，并且还抑制沿着与芯部分355的界面的银枝晶的形成。
第二衬里部分3592可以覆盖芯部分355的水平顶表面351。第二衬里部分3592可以是氧化保护层，例如，由金(Au)、铝(Al)或诸如AlCu、AlSi或AlSiCu的铝合金制成。
具有由银制成的芯部分355的补充结构350增大了结合垫300的机械强度，并保护半导体部分100免受在导线结合期间施加在结合垫300上的机械应力。包含由银制成的芯部分355的补充结构350可以完全取代典型地为相同目的提供的厚铜层。
铜在例如硅的半导体中具有高扩散系数，并且还易于通过诸如钨、铝、诸如AlCu和AlSiCu的铝合金的其它金属层扩散。半导体器件的半导体部分100被铜污染会对器件特性和器件可靠性产生不利影响。因此，传统上，半导体部分100与铜金属化之间的扩散阻挡层防止铜原子从铜金属化扩散到半导体部分100中。
扩散阻挡部相对较薄，并因此容易形成裂缝、漏洞和泄漏。但即使是没有裂缝、泄漏和漏洞的完美的扩散阻挡部，也仍然可以在某种程度上渗透铜原子。
另外，相对厚的铜金属化在处理期间在半导体晶片上和在最终的半导体器件中的半导体部分上都施加显著的热机械应变。
在硅中，银在硅中的扩散系数显著低于铜的扩散系数约五个数量级，并且任何显著的银扩散仅在700℃以上的温度发生，而铜在低于175℃的通常的半导体器件的标称工作范围内的温度扩散。
结果，在没有昂贵的扩散阻挡衬里的情况下得到了其中具有由银制成的芯部分355的补充结构350取代铜金属化的结合垫300，并且与包含铜层的结合垫相比，结合垫300导致显著提高的长期器件可靠性。
图10的半导体器件500将晶体管单元TC与包含银层的结合垫300组合，如参考图4A至4B描述的，晶体管单元TC具有包含场板电极165的沟槽栅极结构150。
结合垫300包含帽部分320，其可包含铝或诸如AlCu、AlSiCu或AlSi的铝合金的主帽层或由其构成。帽部分320的厚度a2可以在从2μm至200μm的范围中。如参考图2A和图2B描述的帽部分320和基底部分310将补充结构350夹在中间。
补充结构350包含由银或由作为主成分的含银材料制成的芯部分355、直接形成于芯部分355与基底部分310之间的第一衬里部分3591和直接形成于帽部分320与芯部分355之间的第二衬里部分3592。第二衬里部分3592的厚度a52可以与第一衬里部分3591的厚度a51相同或者可以在与第一衬里部分3591的厚度a51相同的范围内。第一和第二衬里部分3591、3592均可以由钽和/或钛制成。
在图11中，半导体器件500是功率半导体二极管，其中结合垫300的基底部分310与半导体部分100的水平第一表面101直接接触。
图12A至12C涉及部分图案化的结合垫300。
在图12A中，补充结构350延伸越过结合垫300的整个水平横截面区域。帽部分320仅形成于沿着结合垫300的横向外表面303的垫边缘区域中。帽部分320不存在于结合垫300的中心部分中，补充结构350(例如，芯部分355)在该中心部分被暴露。帽部分320抑制氧化和枝晶的形成。暴露的补充结构350允许在半导体器件500的前侧的烧结或压接触。
银的杨氏模量为82.7GPa，显著低于为130GPa的铜的杨氏模量，使得由银制成的芯部分355施加的热机械应力显著低于由相同的垂直延伸的固体铜结构施加的热机械应力。
在图12B中，补充结构350仅形成于结合垫300的中心部分中。帽部分320的横向外表面323相对于结合垫的基底部分310的横向外表面313被拉回。在芯部分355的垂直投影之外，基底部分310和帽部分320可以将第一和/或第二衬里部分3591、3592的空闲部分夹在中间。根据其它实施例，帽部分320可以直接毗连芯部分355的垂直投影之外的基底部分310。
在图12C中，基底部分310的横向外表面313与帽部分320的横向外表面323共面。对于进一步的细节，参考图12B的描述。
图13A至13C涉及在相同的图案化步骤中图案化帽部分320和基底部分310的方法。
可以将可以包含如以上描述的接触层、阻挡层、填充层和含铝层的基底层叠层810沉积在半导体部分100的第一表面101上或沉积到具有暴露半导体部分100的接触区段的开口的层间电介质210上。例如由钛或钽制成的第一补充层8591沉积在基底层叠层810上。银层沉积在第一补充层8591上，并通过光刻图案化，例如通过使用HNO3和H3PO4的含水混合物的湿法蚀刻。
在图13A中，由银层形成的图案化芯部分355覆盖基底层810的中心部分。在示例的实施例中，与银层同时图案化第一补充层8591。根据其它实施例，可以在干法蚀刻工艺中或通过使用低浓度HF(例如，0.1％HF)的湿法蚀刻去除第一补充层8591的暴露部分。
可以相继地沉积第二补充层8592和盖帽层叠层820，其中盖帽层叠层820直接形成于第二补充层8592上。
图13B示出了共形盖帽层叠层820，其可以包含含铝层，其覆盖由第一和第二补充层8591、8592包封的芯部分355。然后，可以通过干法蚀刻工艺或通过使用不同蚀刻溶液但是相同蚀刻掩模的一系列湿法蚀刻工艺来形成结合垫300。
图13C示出了结合垫300，其具有由图13B的基底层叠层810的部分形成的基底部分310、由图13B的盖帽层叠层820的剩余部分形成的帽部分320、第一衬里部分3591和第二衬里部分3592。帽部分320的横向外表面323和基底部分310的横向外表面313是共面的。
图14A至14C涉及一种方法，其中在不同图案化工艺中形成结合垫300的基底部分310和帽部分320。
沉积并图案化基底层叠层以形成基底部分310。第一补充层8591可沉积在图案化基底部分310上。银层855沉积在第一补充层8591上。
图14A示出了覆盖基底部分310的银层855。作为范例，通过干法蚀刻或使用HNO3和H3PO4的含水混合物的湿法蚀刻来图案化银层855。第二补充层8592沉积在从银层855获得的图案化芯部分355上。盖帽层叠层820沉积在第二补充层8592上。
图14B示出了覆盖芯部分355和基底部分310的盖帽层叠层820。第二湿法蚀刻工艺可去除盖帽层叠层820到芯部分355一距离的部分。
如图14C中示例的，从图14B的盖帽层叠层820获得的帽部分320的横向外表面323相对于基底部分310的横向外表面313被拉回。
尽管已经于此示例和描述了特定实施例，但是本领域技术人员将意识到，在不脱离本公开的范围的情况下，可以用各种替换和/或等同的实现来代替所示出和描述的特定实施例。本申请意图涵盖于此讨论的具体实施例的任何改编或变化。因此，其意图本公开仅由权利要求及其等同物限制。

Claims (23)

1.一种半导体器件，包括：
结合垫(300)，包括：
基底部分(310)，具有基底层(317)；以及
主表面(301)，具有结合区域(305)；
结合导线或夹子(410)，结合到所述结合区域(305)；以及
补充结构(350)，与邻接所述结合区域(305)的所述基底部分(310)直接接触，其中，所述补充结构(350)与所述结合导线或夹子(410)直接邻接或者与所述结合导线或夹子(410)水平地间隔开，其中，所述补充结构(350)的体积比热容高于所述基底层(317)的体积比热容，
其中，所述基底层(317)由铝或铝合金制成。
2.如权利要求1所述的半导体器件，其中，
所述结合垫(300)还包括帽部分(320)，并且其中，所述补充结构(350)位于所述帽部分(320)与所述基底部分(310)之间。
3.如权利要求1所述的半导体器件，其中，
所述补充结构(350)限定所述结合区域(305)的边界。
4.如权利要求1所述的半导体器件，还包括：
密封结构(490)，至少部分地包封所述结合导线或夹子(410)，其中，所述补充结构(350)位于所述密封结构(490)与所述结合垫(300)之间，其中，所述补充结构(350)的所述体积比热容高于所述密封结构(490)的体积比热容。
5.如权利要求4所述的半导体器件，其中，
所述密封结构(490)包括硅凝胶和环氧树脂中的至少一种。
6.如权利要求4和5中的任一项所述的半导体器件，其中，
所述密封结构(490)将所述补充结构(350)与所述结合导线或夹子(410)分开。
7.如权利要求1至5中的任一项所述的半导体器件，其中，
所述补充结构(350)包括含有辅助材料的芯部分(355)，所述辅助材料的体积比热容高于铜。
8.如权利要求7所述的半导体器件，其中，
所述辅助材料是含金属材料。
9.如权利要求8所述的半导体器件，其中，
所述含金属材料包括镍、氧化镍、镍合金、钴、银、碳化钨、黄玉和氟化锂中的至少一种。
10.如权利要求7所述的半导体器件，其中，
所述辅助材料包括酚醛树脂。
11.如权利要求7所述的半导体器件，其中，
所述补充结构(350)包括包封所述芯部分(355)的衬里部分(359)。
12.一种制造半导体器件的方法，其中，所述方法包括：
在半导体部分(100)上形成结合垫基底部分(310)，其中，所述基底部分(310)还包括基底层(317)；
形成包括结合区域(305)的结合垫主表面(301)；
将结合导线或夹子(410)结合到所述结合区域(305)；以及
直接在所述基底部分(310)上形成补充结构(350)，其中，所述补充结构(350)与所述结合导线或夹子(410)横向地邻接或者与所述结合导线或夹子(410)横向地间隔开，其中，所述补充结构(350)的体积比热容高于所述基底层(317)的体积比热容，
其中，所述基底层(317)由铝或铝合金制成。
13.如权利要求12所述的方法，其中，
在所述结合导线或夹子(410)的结合之前形成所述补充结构(350)。
14.如权利要求13所述的方法，其中，
所述补充结构(350)通过丝网印刷、通过模版印刷或通过光刻形成。
15.如权利要求12所述的方法，其中，
在所述结合导线或夹子(410)的结合之后形成所述补充结构(350)。
16.如权利要求15所述的方法，其中，
通过分配器将所述补充结构(350)局部地施加在所述基底部分(310)上。
17.一种半导体器件，包括：
半导体部分(100)，包括掺杂区域(111)；
结合垫(300)，包括与所述掺杂区域(111)直接连接的基底部分(310)，并且所述基底部分具有由铝或铝合金制成的基底层(317)；
补充结构(350)，与所述基底部分(310)直接接触，其中，所述补充结构(350)还包括：
包括银的芯部分(355)；以及
衬里部分(359)，将所述芯部分(355)与所述基底部分(310)分开。
18.如权利要求17所述的半导体器件，其中，
所述结合垫(300)包括帽部分(320)，并且所述补充结构(350)位于所述基底部分(310)与所述帽部分(320)之间。
19.如权利要求18所述的半导体器件，其中
所述帽部分(320)包括由铝或铝合金制成的主帽层。
20.如权利要求18和19中的任一项所述的半导体器件，其中，所述衬里部分(359)还包括：
第一衬里部分(3591)，将所述芯部分(355)与所述基底部分(310)分开；以及
第二衬里部分(3592)，将所述芯部分(355)与所述帽部分(320)分开。
21.如权利要求17至19中的任一项所述的半导体器件，其中，
所述衬里部分(359)包括钛和钽中的至少一种。
22.如权利要求17至19中的任一项所述的半导体器件，其中，
所述芯部分(355)含有银作为主成分。
23.如权利要求17至19中的任一项所述的半导体器件，还包括：
结合导线或夹子(410)，在所述结合垫(300)的主表面(301)的结合区域(305)中结合到所述结合垫(300)。
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