CN101771049A - 基于底部源极金属氧化物半导体场效应管的真实芯片级封装功率金属氧化物半导体场效应管 - Google Patents

基于底部源极金属氧化物半导体场效应管的真实芯片级封装功率金属氧化物半导体场效应管 Download PDF

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CN101771049A
CN101771049A CN200910266257.0A CN200910266257A CN101771049A CN 101771049 A CN101771049 A CN 101771049A CN 200910266257 A CN200910266257 A CN 200910266257A CN 101771049 A CN101771049 A CN 101771049A
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CN101771049B (zh
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弗兰茨娃·赫尔伯特
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Chongqing Wanguo Semiconductor Technology Co ltd
Alpha and Omega Semiconductor Ltd
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Alpha and Omega Semiconductor Ltd
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Abstract

一种半导体封装可以包含一个半导体衬底、一个带有形成在衬底上的多个单元的金属氧化物半导体场效应管器件、以及一个和设置在衬底底面上的所有单元共用的源极区。每个单元包含一个在半导体器件顶面上的漏极区、一个用于控制源极和漏极区之间电流流量的栅极、一个邻近栅极的源极接触点，以及源极接触点和源极区之间的电接触。至少一个漏极接触点电耦合到漏极区域上。源极、漏极和栅极垫分别电连接到器件的源极区、漏极区和栅极。漏极、源极和栅极垫形成在半导体封装的一个表面上。单元通过衬底分布，因此每个器件的源极接触点和源极区之间的电连接分布也通过衬底。本发明允许在晶片等级上进行处理，降低成本和缩小独立器件的尺度，并使接触点遍及晶粒，降低电子干扰和阻抗。

Description

基于底部源极金属氧化物半导体场效应管的真实芯片级封装功率金属氧化物半导体场效应管
技术领域
本发明涉及半导体功率器件，具体涉及一种底部-源极金属氧化物半导体场效应管结构与一种芯片级封装的低成本工艺。
背景技术
目前，对于进一步降低半导体功率器件例如场效应管、金属氧化物半导体场效应管以及结型场效应管器件等的源极电感和阻抗，传统技术常常遇到许多技术上的难题和局限。由于越来越多的功率器件在使用过程中，都被要求高效、高增益以及高频率，因此对降低半导体功率器件的源极电感和阻抗的要求也不断增加。可以通过除去半导体功率器件封装过程中的接合线，来降低源极电感。我们已经做了多种尝试，比如可以将半导体衬底配置为半导体功率器件的源极接线，以便除去接合线。但由于典型的垂直半导体器件是将漏极电极置于衬底之上，因此使用这些方法仍有困难。在器件封装过程中，顶部源极电极的电接触通常要使用接合线，这就增加了源极电感。
过去十几年中，硅工艺技术突飞猛进，主要是同一种久远的封装技术仍然作为主要的封装手段大行其道。沿铝或金线贴装环氧或焊锡芯片，连接到引线框上，仍然是主流的半导体封装技术。在半导体处理技术上的进步使得传统的封装技术产生很多寄生现象(例如阻抗、电容和电感)，而不仅仅是一个性能限制因素。对于传统的倒装晶片技术，就有很多不足，比如(垂直半导体的)晶片背部的电接触不易加工。这些局限在功率转换器件等高电流装置中尤为明显。
美国专利号为6,767,820的专利和美国申请号为20010048116的专利提出了一种半导体金属氧化物半导体栅极器件的芯片级封装。金属氧化物半导体栅极器件晶片的源极一边覆盖有钝化层，最好使用光敏液体环氧树脂或氮化硅层，或其他相似物。然后烘干材料，曝光被覆盖的晶片，使用标准光刻蚀技术在晶片上形成图案，钝化层上形成的开口，用于为下面的源极金属，制造多个隔开的曝光顶面，以及一个类似的开口用于曝光晶片上每个晶粒下面的栅极电极。钝化层上的开口用于制作传统的下部可软焊的顶部金属，例如钛、钨、镍或银等。开口形成后，将晶片锯成或者分成单个独立的晶粒。使用导电环氧树脂、焊锡或其他类似材料，将晶粒的底部漏极电极与漏极晶片相连，这样一来，晶粒可软焊的漏极边缘就被连接到了U-形或杯形漏极晶片上。漏极晶片的边角底部同晶粒的源极边缘顶面(也就是接触投影的顶部)共面。通常由铜合金与至少部分设置的银表面组成U-形晶片，而且U-形晶片实际上非常薄。但是，与晶片等级处理相比，要将晶粒连接到单个晶片上，是有些浪费时间的。另外，不同的U-形晶片适用于不同的晶粒尺寸，而且晶片要在PC板上占据额外的空间。
美国公开号为2003/0052405的专利提出了一种垂直功率金属氧化物半导体场效应管器件，在硅衬底的底面上带有漏极电极连接它上面的引线框，但栅极电极和源极电极却裸露在器件底面。用环氧树脂或硅有机树脂等树脂密封金属氧化物半导体场效应管，这样就能覆盖金属氧化物半导体场效应管器件以及引线框的内部结构。在金属氧化物半导体场效应管器件的底面上，树脂的表面与引线框和栅极/源极电极的表面大致齐平。也就是说，在半导体器件的底面上，引线框外面引线部分的底面与栅极/源极电极的底面都裸露出来，以便连接贴装基板的导电部分(贴装面)。然后用树脂覆盖这些栅极/源极电极的周围。
美国专利号为6,133,634的专利提出了一种倒装晶片封装功率金属氧化物半导体场效应管器件的方法，包含一个漏极端、一个源极端和一个栅极端。其中漏极端连接导电载流子和外面的一排焊锡球。源极端和栅极端连接里面的一排焊锡球。导电载流子和外面的一排焊锡球为印刷电路板和漏极端之间提供电接触。
美国专利号为6,469,384的专利提出了一种封装类似于金属氧化物半导体场效应管等半导体器件的方法，此方法并不需要模制体。金属氧化物半导体场效应管器件耦合到衬底上，因此晶粒的源极和栅极区域也就耦合到了衬底上。将金属氧化物半导体场效应管器件置于印刷电路板上，印刷电路板上带有焊锡膏或适当的导电互联，以使晶粒的表面直接耦合上去，并作为漏极接线。耦合到衬底上的晶粒表面构成了晶粒的栅极区域和源极区域。因此，衬底栅极区域中的焊锡球用于将晶粒的栅极区域耦合到印刷电路板上，同时剩余的焊锡球将晶粒的源极区域通过衬底耦合到印刷电路板上。
美国专利号为6,646,329的专利提出了一种半导体器件，包含一个带有源极垫的引线框、在源极垫周围的至少两个源极引线轨道、在源极垫附件的一个栅极垫，以及在栅极垫周围的一个栅极引线轨道。晶粒耦合到源极垫和栅极垫上，以至于晶粒上与垫相反的表面，同引线轨道的末端齐平或共面。并将增强板耦合到引线框上，从此处电绝缘。
上述所有的原有技术器件都要求外部封装，以便连接到垂直半导体晶粒的背面。通常而言，封装连接到晶粒的背面，并缠绕起来，以便和晶粒正面共面。然而，这种结构实际上导致引脚(footprint)比晶粒本身的引脚(footprint)要大，因此它并不是一个真实的芯片级封装。另外，封装所需的其他材料增加了器件的成本。
美国专利号为6,653,740的专利提出一种含有“倒装晶粒”的半导体晶粒封装，这种晶粒可以通过其表面装配在电路板上或其他电子接口上。特别之处在于，这种封装方式在封装的同一侧，具有栅极、源极和漏极电极等接触点(用于接触金属氧化物半导体场效应管)，而且可以通过在晶粒表面上形成焊锡球接触点，这些接触点分别同电路板上的外部栅极、源极和漏极垫相互连接。外部电路元件可以通过晶粒源极上的焊锡球，与晶粒电接触，焊锡球之所以在晶粒源极上，是为了能够同电路板上的合适的源极电接触点互相连接。这种封装方式，可以使漏极电极处在与源极分离的区域中的同一个表面上。高度掺杂的扩散区或“下沉区”从顶部漏极下面延伸，通过比衬底载流子浓度低的层。扩散区的载流子浓度和类型，都与衬底相同。因此，建立了这样一条电路通路：从源极电极出发，通过有源元件，进入衬底，并通过扩散区，到达顶部漏极电极。和源极、栅极在同一表面上的漏极可以使用焊锡球安装在电路板上，这些焊锡球相当于合适的外部漏极接触点。
以上所述的原有技术封装旨在为垂直功率金属氧化物半导体场效应管器件，提供功率器件的源极、栅极和漏极与单个金属氧化物半导体场效应管晶粒前端的电接触。但是，有些技术要求使用另外的衬底或封装材料，以便与顶面进行背部接触，又或者要求使用不同尺寸的焊锡球。另外，还有些技术要求通过另外的处理工序，以形成“下沉区扩散”，又或者要求通过漂浮漏极的接触沟道。另外，使用带有漏极下沉区的垂直双极型金属氧化物半导体结构，要求在下沉扩散区和有源区之间为高压结构(也就是说N-漂移区中的本体区域的耗尽层)留有很大的空间。而且，在这些“下沉区扩散”技术中，接触点并没有遍及晶粒，这就使得整体阻抗更高(源于扩散阻抗)，工作效率更低。
发明内容
本发明提供一种基于底部-源极场效应管的真实芯片级封装功率场效应管，允许在晶片等级上进行处理，降低成本和缩小独立器件的尺度，并使接触点遍及晶粒，降低电子干扰和阻抗。
为实现上述目的，本发明提供一种基于底部-源极场效应管的真实芯片级封装功率场效应管，其特征是，包含：
一个半导体衬底；
一个半导体器件包含一个分立的金属氧化物半导体场效应管，具有多个形成在该半导体衬底一有源区中的单元；
一个设置在全部单元共用的衬底底部的源极区域，其中每个单元都包含：
一个设置在半导体器件顶部的漏极区域；
一个栅极，用于当栅极外加电压时，控制源极区域和漏极区域之间的电流；
一个位于栅极附近的源极接触点；
一个通过衬底在源极接触点和源极区域之间形成的电接触；
至少一个漏极垫电耦合到漏极区域；
至少一个源极垫电连接到源极区域，其中源极垫向衬底施加偏置；
至少一个栅极垫电耦合到栅极上；
一个漏极金属覆盖整个有源区；
一个连接到源极垫上的嵌入式本体-源极短接结构，其中这个嵌入式本体-源极短接结构位于漏极金属下方；
其中漏极、源极和栅极垫都形成在半导体器件的一个表面上；
其中所述多个单元沿衬底分布，因此每个半导体器件的源极接触点和源极区域之间形成的电连接也沿衬底分布；
其中漏极垫形成在半导体封装的有源区上；
其中源极和栅极垫形成在有源区外面的半导体封装的终止区上。
上述的本体-源极短接结构为一种嵌入式栅极屏蔽。
上述的本体-源极短接结构为一种嵌入式导电插塞。
上述的本体-源极短接结构在半导体器件上分布源极。
上述的半导体芯片级封装还包含一个设置在半导体封装外围的栅极环，用于所述的半导体器件的栅极垫和栅极区之间的互联。
上述的半导体芯片级封装还包含一个设置在半导体封装外围的金属化的衬底环，用于直接连接到源极垫上。
上述的每个单元还包含一个导电插塞，用于将漏极区域电连接到漏极金属上。
上述的金属氧化物场效应管为一个底部源极横向扩散金属氧化物半导体器件，
上述的底部源极横向扩散金属氧化物半导体器件的每个单元的源极接触点和源极区域之间形成的电接触包含一个顶部源极区、衬底，以及一个在外延层中的复合下沉-沟道区，其中复合下沉-沟道区作为一个下沉区，将衬底电连接到顶部源极区，并作为一个形成金属氧化物半导体场效应管沟道的本体区域，其中嵌入式本体-源极短接结构将顶部源极区短接到下沉-沟道区。
上述的底部-源极横向扩散金属氧化物半导体器件还包含一个设置在栅极区域下方的漂移区，与源极区域形成一距离，延伸至漏极区并围绕着漏极区。
上述的复合下沉-沟道区延伸至漂移区下方，其掺杂电导性与漂移区相反，并补偿漂移区，以便降低源-漏电容。
上述的底部-源极横向扩散金属氧化物半导体器件中的嵌入式本体-源极短接结构包含一个嵌入式栅极屏蔽层，此屏蔽层包含一个在栅极区域、源极区域和本体区域上方设置的导电层。
上述的嵌入式栅极屏蔽层包含一层氮化钛或硅化钛金属。
上述的源极垫位于嵌入式栅极屏蔽层上方。
上述的嵌入式栅极屏蔽层将源极分布至整个半导体器件。
上述的半导体芯片级封装还包含一个或更多的导电插塞，以便将源极垫连接到嵌入式栅极屏蔽层上。
上述的金属氧化物半导体场效应管包含一个逆沟槽源极接地垂直沟道金属氧化物半导体场效应管器件。
上述的逆沟槽源极接地垂直沟道金属氧化物半导体场效应管器件的每个单元还包含：
源极区和漏极区之间的一个垂直电流传导沟道，由设置在沟道侧壁上的一个垂直侧壁栅极区控制，通过附着在沟道侧壁上的栅极氧化层提供衬垫；
其中所述的嵌入式本体-源极短接结构为一个嵌入式导电插塞，从沟道的一个底面向下延伸，用于将半导体衬底中的本体区短接到设置在所述沟道底面下的源极区。
上述的每个单元中的嵌入式导电插塞用于在多个单元中分布源极。
上述的每个单元中的导电插塞包含一种钛、钴或钨的硅化物。
上述的逆沟槽源极接地垂直沟道金属氧化物半导体场效应管器件的每个单元还包含：
一个设置在半导体衬底中的掺杂本体区，环绕着源极区域周围的沟道中较低的部分，其中掺杂本体区包含沿沟道侧壁的沟道；
一个设置在衬底顶面附近的漂移区，环绕沟道上部，并包围漏极区域；以及
一个设置在漂移区下方的连接区，向下延伸到掺杂沟道区，以便连接漂移区和掺杂沟道区。
上述的半导体芯片级封装还包含一个设置在终止区和多个栅极流道中的栅极金属，每个栅极流道都为多个单元的栅极区和设置在终止区中的栅极金属之间提供电连接。
一种用于制造半导体芯片级封装的方法，其特征是，包含以下步骤：
形成一个半导体衬底；
在半导体衬底中的有源区形成多个单元，每个单元都包含一个栅极区、一个设置在半导体器件底部的源极、一个设置在半导体器件顶部的漏极区，以及为每个半导体器件中的源极区域分布衬底接触点；
在多个半导体器件上形成一个共漏极金属；
形成一个嵌入式本体-源极短接结构，放置在共漏极金属下面，并连接到源极区和源极垫上；
在共漏极金属上部，形成至少一个漏极垫；以及
在半导体衬底的终止区，形成至少一个源极垫和至少一个栅极垫；
其中漏极、源极和栅极垫都在半导体封装的一个表面上。
上述的嵌入式本体-源极短接结构在多个单元分布源极。
本发明基于底部-源极场效应管的真实芯片级封装功率场效应管与现有技术的半导体芯片级封装相比，其优点在于：本发明的整个有源区内提供分布式的衬底连接，这有利于降低阻抗和器件封装带来的电感；
本发明在器件的背部装配源极，同时也增强了屏蔽，降低了电磁干扰；
本发明在背部装配源极，降低电击的风险；
本发明的结构通过标准处理工艺就能实现，无需深沟道刻蚀或典型的底部源极金属氧化物半导体场效应管器件所需的特殊工艺，制作衬底接触点也无需多余的加工工艺，工艺简单；
本发明的有源区外面所有的表面都能用作衬底接触区，进一步降低衬底阻抗。
附图说明
图1A为一种半导体封装的俯视图，依据本发明的一个实施例，这种封装在器件的一个前表面上包含两个漏极垫、一个源极垫和一个栅极垫。
图1B为一种半导体封装的俯视图，依据本发明的另一个实施例，这种封装在器件的一个前表面上包含一个漏极垫、一个源极垫和一个栅极垫。
图1C为一种半导体封装的俯视图，依据本发明的一个实施例，这种封装在器件的一个前表面上包含两个漏极垫、一个源极垫和一个栅极垫，以及一个在器件外围的金属化的衬底环接触点。
图1D为一种半导体封装的俯视图，依据本发明的一个实施例，这种封装在器件的一个前表面上包含一个漏极垫、两个源极垫和一个栅极垫，以及一个在器件外围的金属化的衬底环接触点。
图2为带有沟道的底部源极的横向双扩散金属氧化物半导体器件的一个单元的横截面视图。
图3为图1A所示的半导体封装沿A-A’线的横截面视图，依据本发明的一个实施例，这种封装包含多个如图2所示的底部源极横向双扩散金属氧化物半导体单元。
图4A为图1A所示的半导体封装沿B-B’线的横截面视图，依据本发明的另一个实施例，这种封装包含多个如图2所示的底部源极横向双扩散金属氧化物半导体单元。
图4B为图1所示的半导体封装沿B-B’线的横截面视图，依据本发明的另一个实施例，这种封装包含多个如图2所示的底部源极横向双扩散金属氧化物半导体器件，以及在源极垫区域中的导电插塞。
图5A为图4A-图4B所示的半导体封装装置的俯视图，表示一个有边的顶部栅极连接。
图5B为图5A所示的栅极互联区域的横截面视图。
图5C为图4A-图4B所示的半导体封装装置的俯视图，表示一个有边的顶部栅极与一个嵌入式栅极屏蔽的接线，用于引导源极连接到晶粒上。
图6为图1所示的半导体封装的俯视图，表示一个连接到源极垫上的栅极防护。
图7表示一个反转沟道的垂直通道金属氧化物半导体场效应管的横截面视图。
图8为图1A所示的半导体封装沿A-A’线的横截面视图，依据本发明的另一个实施例，这种封装包含如图7所示的反转沟道的垂直通道金属氧化物半导体场效应管器件。
图9为图1A所示的半导体封装沿B-B’线的横截面视图，依据本发明的另一个实施例，这种封装包含如图7所示的反转沟道的垂直通道金属氧化物半导体场效应管器件。
具体实施方式
尽管以下所述的详尽说明包含了许多用于解释说明的细节内容，但是本领域的任何一位技术人员都应认识到依据以下内容所做出的变换和改动都应属本发明的范围。因此，以下内容毫无遗漏、如实详尽地阐述了本发明的实施例。
本发明的实施例提出了一种真实的芯片级封装分离的金属氧化物半导体场效应管器件，用底部源极器件，使封装的全部漏极、源极和栅极连接位于晶粒前表面上。
根据本发明的实施例，半导体封装包含一个半导体衬底、数个形成在半导体衬底上的半导体器件、以及一个设置在衬底底部的共同源极区域。每个半导体器件都包含一个在顶端设置的漏极区域、一个用于在栅极上加电压时控制源极和漏极之间电流的栅极、一个邻近栅极的源极接触点；以及一个通过源极接触点和设置在衬底底部的源极区域之间的衬底所形成的电连接。至少有一个漏极垫电耦合到漏极区域上。至少有一个源极垫电连接到源极区域上。至少有一个栅极垫电耦合到每个半导体器件的栅极上。漏极、源极和栅极垫都形成在半导体封装的一个表面上。数个半导体器件分布在衬底上，以使每个半导体器件的源极接触点和和源极区域之间形成的电连接都分布在衬底上。
图1A为根据本发明的一个实施例而来的一种半导体封装100的俯视图。正如图1所示，半导体封装100包含两个漏极垫108、一个源极垫110和一个栅极垫112，位于底部源极半导体器件102的前表面上，比如底部源极横向双扩散金属氧化物半导体器件。漏极、源极和栅极垫108、110和112可以用于接收芯片级封装装置的焊锡球、突起或支柱。漏极垫108可位于漏极金属106上，漏极金属106位于横向双扩散金属氧化物半导体器件的有源区上面并与其保持电接触。也可选用，一种另外的金属垫，用于将漏极垫108连接到漏极金属106上。源极垫110和栅极垫112位于器件102的非有源区或终止区。由于这是一种底部源极半导体晶粒，源极垫110电连接到源极接点(图中没有给出)，源极接点分布在构成晶粒的多个单元之间。栅极垫112通过位于半导体封装100外围的导电栅极环104，电连接到横向双扩散金属氧化物半导体器件的每个单元(图1A中没有给出)中的栅极区域。可以使用多晶硅或金属、或者两者的组合制造栅极环104，这仅作举例说明用，并不局限于此。
由于漏极接线可形成在有源区之上，而非有源区之外，因此半导体封装100的结构具有比源极接线更多的漏极接线，这也就增加了真实的芯片级封装金属氧化物半导体场效应管的有源区。
图1B为根据本发明的另一个实施例而来的一种半导体封装101的俯视图。正如图1B所示，半导体封装101仅包含一个漏极垫108、一个源极垫110和一个栅极垫112，位于底部源极半导体器件101的前表面上。漏极垫108位于漏极金属106上，在底部源极半导体器件102的有源区，例如底部源极横向双扩散金属氧化物半导体器件。源极垫110和栅极垫112位于器件102的非有源区。栅极垫112通过栅极环104连接到个别单元的栅极区域。源极垫、栅极垫和漏极垫为半导体封装可提供到其他电路元件的电连接，例如，通过导电附着物或焊锡球。为了保证晶粒在封装过程中保持“平坦”，所需的垫开口和焊锡球的最小数量是三。如果晶粒的焊锡球数小于三，封装后的晶粒可能会不平坦。
图1C为根据本发明的另一个实施例而来的一种半导体封装103的俯视图。同图1A所示的半导体封装100类似，半导体封装103包含两个漏极垫108、一个源极垫110和一个栅极垫112，位于半导体封装103的前平面上。漏极垫108位于有源区，源极和栅极垫110、112位于底部源极半导体封装102的非有源区或终止区，例如底部源极横向双扩散金属氧化物半导体器件。栅极垫112通过位于半导体封装103外围的导电栅极环104，电连接到横向双扩散金属氧化物半导体器件的单元(图中没有给出)中的栅极区域。半导体封装103还包含一个位于器件102外围的衬底接触环114。衬底环114直接连接到源极接线110上。可以用金属制造衬底接触环114。
图1D为根据本发明的另一个实施例而来的一种半导体封装105的俯视图。正如图1D所示，半导体封装105包含一个漏极垫108、两个源极垫110和一个栅极垫112，位于底部源极半导体器件101的前表面上，比如底部源极横向双扩散金属氧化物半导体器件。漏极垫108位于半导体封装105有源区的漏极接触金属106上。源极垫110和栅极垫112位于器件102的非有源区。栅极垫112通过位于半导体封装105外围的栅极环104，电连接到器件102的栅极区域(图中没有给出)。半导体封装105还包含一个位于器件105外围的衬底接触环114。衬底环114直接连接到源极接线110上。
半导体封装105带有两个源极垫110的结构降低了源极电感，使得源极简并也随之降低。高频率器件应用中(例如无线电频率(RF)应用)需要很低的源极简并。
图2为带有沟道的底部源极的横向扩散金属氧化物半导体(BSLDMOS)器件的单元200的横截面视图，在与上述类型如图1A-1D所示的半导体器件封装的连结中可以使用这种器件。一个沟道底部源极横向扩散金属氧化物半导体器件是由多个这种单元构成的。在图2所示的示例中，沟道底部源极横向双扩散金属氧化物半导体单元200，位于一个P-型重掺杂(P+++)衬底202上，202起底部源极电极的作用。在衬底202的上方，形成一个P-型(P-)轻掺杂外延层206。在器件的有源单元区下方，一个掺杂P+离子的深下沉-沟道区204，形成在外延层中至一深度，并且侧面延伸到漏极漂移区220的底部，以补偿一部分晶体管中堆积的N-掺杂，这样才能将N-漂移区220的掺杂物轮廓调整至最佳，使得当漏极源极间阻抗Pdson维持在一个较低值时，栅极-漏极电容能够达到最小。下沉区204作为连接P+++衬底202的源极部分到P+本体接触区210的下沉沟道，还担任本体区域的作用，在本体区域中，金属氧化物半导体场效应管沟道形成在栅极222下面。被氧化物218环绕着的栅极222设置在栅极氧化层216上，栅极氧化层216位于顶部源极区208的顶面和漏极漂移区220之间。因此，作为一个横向金属氧化物半导体器件，栅极222通过形成在下沉沟道区204中的沟道，控制着顶部源极区208和N-漂移区220之间的电流。漏极区220设置在氧化物216下面。由钨等金属制成的导电插塞214可以用于，通过一个接触阻抗很小的N+掺杂接触区209，将顶部漏极金属224电连接至漏极漂移区220。被氧化物218环绕着的嵌入式栅极屏蔽212可以设置在栅极222上，并与P本体接触区210和顶部源极区208接触。嵌入式屏蔽212可用于将顶部源极区域208短接至P本体接触区210上，和下沉沟道区204上，形成一种嵌入式本体-源极短路结构。顶部源极区208通过嵌入式栅极屏蔽212和下沉区204，电连接至底部源极P+++衬底212上。可以用氮化钛(TiN)制作嵌入式屏蔽212，这仅作举例说明用，并不局限于此。
相同通转让人的公开号为20080023785的美国专利申请中介绍了一种类似结构的沟道底部源极横向双扩散金属氧化物半导体，在此将引用该文，以作参考。
参照图3、图4A、图4B、图5A和图5B，可以了解图1A-1D所示的半导体封装结构的优势所在。
图3为图1所示的半导体封装100沿A-A’线的横截面视图。正如图3所示，半导体封装100包含多个图2所示类型的带有沟道的底部源极横向式扩散金属氧化物半导体单元200。正是由于这些单元的存在，使得器件封装区域成为一个有源区。栅极环104位于半导体封装100的外围。共漏极金属224设置在带有沟道的底部源极横向式扩散金属氧化物半导体器件200上方，并同底部源极横向式扩散金属氧化物半导体器件200的所有导电插塞214电接触。漏极垫301可以形成在共漏极金属224的上方，并通过由聚酰亚胺制成的钝化层304，将不同漏极垫分离开。另一种方案是，漏极垫301包含漏极金属224通过钝化层304的曝光部分。漏极垫108位于漏极垫301的上方。嵌入式屏蔽212用于将源极区域208与P本体接触区210短接。
图4A为图1A所示的半导体封装沿B-B’线的横截面视图。正如图4A所示，源极垫401和栅极垫411分别形成在无源区402和404上。在无源区402中，嵌入式屏蔽212向外延伸，以便为源极金属406提供空间。源极金属406设置在嵌入式屏蔽212上方，并通过P+下沉区204，与器件200的源极区域208形成源接触点。源极垫401形成在源极金属406上方，或者另一种方案是，源极金属406通过钝化层304中的一个开口曝光的部分形成了源极垫401。焊锡球或导电附着物(图中没有给出)位于源极垫401上，以便提供与外部电路器件的电接触。在无源区404中，栅极电极410形成在深P+下沉区204上的一个没有单元200的区域上。栅极电极410通过栅极环1004，与单元200的独立栅极222电连接。栅极电极410通过氧化层412，与深P+下沉区204电绝缘。可以使用多晶硅或金属制造栅极电极410。也可以用覆盖在嵌入式屏蔽212上的氧化物218部分包围栅极电极410。栅极金属408形成在栅极电极410上方。然后在栅极金属408上形成栅极垫411，或者另一种方案是，栅极金属408通过钝化层304中的一个开口曝光的部分形成了栅极垫411。焊锡球或导电附着物(图中没有给出)位于栅极垫411上。源极垫401和栅极垫411之间，通过钝化层304电绝缘。
图4B为图1所示的半导体封装100沿B-B’线的另一种横截面视图。在本实施例中，源极金属406设置在嵌入式屏蔽212上，并通过插塞414，与嵌入式屏蔽212电接触，插塞414由类似金属钨等导电材料制成。
图5A为图4A-4B所示的半导体封装装置的俯视图，表示一种单面顶部栅极连接。如图5A所示，为了清楚地说明，忽略栅极屏蔽212和漏极金属224。导电插塞214被栅极222包围，并通过氧化物218(图中没有给出)，与栅极222电绝缘。栅极连接到栅极浇道223上，栅极浇道223为栅极222和栅极电极410之间提供电接触。P+下沉区204位于邻近栅极222的地方。图5B为图5A所示的栅极互联区域502的横截面视图，其中包含一个设置在P+++衬底202上方的深P+下沉区204和设置在深P+下沉区204上方的栅极222，栅极222通过氧化物216与深P+下沉区204电绝缘。氧化物216在栅极无源(例如栅极浇道223)的区域中较厚，以便降低栅极和基极(源极)之间的寄生电容。独立的底部源极接触点之间的电连接可以通过每个单元中的P+下沉区204提供，位于无源区402上面的源极垫110可以通过衬底202提供。另一种方案是，如图5C所示，嵌入式栅极屏蔽金属212可用作连接器，协助分配源极电流。嵌入式栅极屏蔽212是一种可用于引导半导体器件上的源极接触点的导体。正如图5C所示，嵌入式栅极屏蔽212展示了重叠的栅极电极。事实上，嵌入式栅极屏蔽212覆盖在栅极222和P+深下沉区204上，在此没有详细阐述以免混淆。在图5A和图5C中，尽管通过氧化物218(图中没有给出)使其大部分都绝缘，可借助导电插塞214形成连接，但是漏极金属224(图中没有给出)还是覆盖了器件的整个有源区。同样地，P+++衬底202(图中没有给出)位于整个区域下方。嵌入式栅极屏蔽212在漏极金属224下工作。作为示例，图5A和图5C中的A-A’横截面可用图2表示。
图6为图1A所示的半导体封装100的俯视图，表示栅极屏蔽连接到源极垫上。图6中，源极垫110和栅极垫112上面的金属绘成透明状，是为了便于说明。正如图6所示，漏极金属224覆盖了半导体封装100的整个有源区106，漏极垫108设置在漏极金属224上。独立器件200的栅极222设置在漏极金属224下面。一个栅极环104环绕在有源区周围。栅极222和栅极垫112之间的电接触由栅极浇道223和栅极环104提供，栅极环104设置在器件周围，并与栅极垫电接触。嵌入式屏蔽212可以直接电连接到源极垫上，以便协助分配源极电流。最好是将嵌入式屏蔽212互联到源极垫，并与源极垫直接接触(如图6所示)，以便降低阻抗分布。但这并不是必须的，嵌入式屏蔽212也可以通过源极/本体接触点下沉区204，连接到一起。
图7为带有一个底部源极和一个顶部漏极的N-沟道反转基极-源极沟道型场效应管器件700的一部分的横截面视图。反转基极-源极沟道型场效应管器件700作为底部源极电极，位于P+衬底702上。另一种方案是，在其他衬底材料上形成P-沟道器件，比如N+掺杂型硅衬底、碳化硅、氮化硅等其他半导体衬底。在衬底702上形成一个P-外延层704。衬底具有一个有源单元区701和一个终止区703，它们都设置在衬底周围。场效应管器件700具有多个沟道，从衬底顶面开始，一直到外延层704较低的部分。有源单元区域701中的沟道制作得比较宽，以便在每个单元中形成一个栅极，此栅极带有一个沿着沟道侧壁形成的栅极多晶硅层712，其中沟道侧壁填充有沟道壁氧化层706，中心部分填充有含有硼磷的硅玻璃层708等绝缘材料。较窄的沟道形成在终止区或有源区内，形成栅极浇道710，以便形成栅极浇道710提供电接触，将有源区中的沟道之间的侧壁栅极712连接到终止区和有源区上方的栅极接触点上。形成在外延层中的P-本体区714环绕着绝缘沟道侧壁栅极712。N-掺杂连接区716形成在P-本体区714上方连接N-掺杂漂移区718，在衬底连接漏极区716和掺杂沟道区的顶面附近，N-掺杂漂移区718环绕着N+漏极接触区720。
沟道垂直场效应管器件中的每个单元还包含一个本体-源极短接结构，形成在有源单元区域中沟道的底部。本体-源极短接结构带有一个由钛、钴或钨的硅化物制成的嵌入式导电插塞722，环绕着高掺杂N+源区724和高掺杂P++区726，在嵌入式导电插塞722下方形成一个高电导、低电阻的本体-源极短接结构。漏极金属728覆盖着有源单元区，栅极金属730形成在终止区内。漏极金属和栅极金属分别与漏极720和栅极沟道710电接触，通过周围是绝缘层732(比如含有硼磷的硅玻璃层)和绝缘层(比如氧化层)734的漏极接触点736和栅极接触点738，覆盖着场效应管器件的顶面。漏极和栅极接触点736、738最好使用比如钨插塞等导电插塞。如图所示，每个单元中由嵌入式导电插塞722形成的集成的嵌入式本体-源极短接结构，可用于在构成器件的单元之间平均分配源极电流。器件结构带有一个垂直沟道，包含一个底部源极，也就是连接在衬底底部上的源极。器件700在源极区域的下方，无需配置P+下沉区。取而代之的是，底部源极器件采用一种带有本体-源极短接结构722的嵌入式源极和本体。因此，这种器件结构节省了水平空间，避免P+下沉区的水平扩散。
美国公开号为20080035987的专利提出了一种类似于图7所示的反转式基极-源极带沟道的横向扩散金属氧化物半导体场效应管(LDMOSFET)，在此将作为示例加以引述。
图8为与图1A所示的沿A-A’线类似的一种半导体封装的横截面视图，这种封装包含与图7中同类型的反转式垂直沟道金属氧化物半导体场效应管器件。正如图8所示，半导体封装100包含多个反转式带沟道的垂直沟道金属氧化物半导体场效应管器件700，有源单元701在有源区106内，栅极浇道710设置在封装100的外围。共漏极金属802设置在反转式沟道垂直沟道金属氧化物半导体场效应管有源单元701上方，并且通过一个导电插塞736同单元701电接触，导电插塞可以用钨等金属制作。漏极接触点108形成在共漏极金属802上，并通过钝化层804相互绝缘。每个单元701中集成的嵌入式本体-源极短接结构722用于分配整个封装100上的源极接触点。
图9为图1所示的沿B-B’线的半导体封装的横截面视图，根据本发明的一个实施例，这种封装包含图7所示的反转式沟道垂直沟道金属氧化物半导体场效应管器件。正如图9所示，通过一个带有源极金属904的宽沟道，以及沟道内用于接触嵌入式导电插塞722的导电(比如钨)插塞902，形成了源极连接110。栅极垫112形成在栅极金属906上，通过导电插塞738将栅极金属906电连接到一个栅极浇道的阵列710上。通过适当的布局安排，嵌入式导电插塞722无需通过衬底，就可以分配整个半导体器件上的源极，以便获得更低的阻抗。
如上图2-9所示的半导体封装结构可以在器件的整个有源区内提供分布式的衬底连接，这有利于降低阻抗和器件封装带来的电感。本发明的实施例不仅适用于N-沟道的金属氧化物半导体场效应管，也适用于P-沟道的金属氧化物半导体场效应管。在器件的背部装配源极，同时也增强了屏蔽，降低了电磁干扰(EMI)。对于N-沟道的金属氧化物半导体场效应管，由于其源极电势接地，因此在背部装配源极还能降低电击的风险。这种结构通过标准处理工艺就能实现，无需深沟道刻蚀或典型的底部源极金属氧化物半导体场效应管器件所需的任何特殊工艺。另外，制作衬底接触点也无需多余的加工工艺。有源区外面所有的表面都能用作衬底接触区，以便进一步降低衬底阻抗。
上述为本发明的较佳实施例的完整介绍，也可以使用各种等量的变换和修正。因此本发明的范围不应局限与上述说明，而应由附加的权利要求书及其等效的要求范围所决定。无论是否优先说明，任何特性都可以同其他任何一个特性结合起来。在下述权利要求中，除非特别指明，否则不定冠词“一个”或“一种”都指代下文中一个或更多的项目。除非在一个权利要求中用“指定”明确指出，否则附加的权利要求不能看作包含方式加功能的限制。
尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。

Claims (24)

1.一种半导体芯片级封装，其特征在于，包含：
一个半导体衬底；
一个半导体器件包含一个分立的金属氧化物半导体场效应管，具有多个形成在该半导体衬底一有源区中的单元；
一个设置在全部单元共用的衬底底部的源极区域，其中每个单元都包含：
一个设置在半导体器件顶部的漏极区域；
一个栅极，用于当栅极外加电压时，控制源极区域和漏极区域之间的电流；
一个位于栅极附近的源极接触点；
一个通过衬底在源极接触点和源极区域之间形成的电接触；
至少一个漏极垫电耦合到漏极区域；
至少一个源极垫电连接到源极区域，其中源极垫向衬底施加偏置；
至少一个栅极垫电耦合到栅极上；
一个漏极金属覆盖整个有源区；
一个连接到源极垫上的嵌入式本体-源极短接结构，其中这个嵌入式本体-源极短接结构位于漏极金属下方；
其中漏极、源极和栅极垫都形成在半导体器件的一个表面上；
其中所述多个单元沿衬底分布，因此每个半导体器件的源极接触点和源极区域之间形成的电连接也沿衬底分布；
其中漏极垫形成在半导体封装的有源区上；
其中源极和栅极垫形成在有源区外面的半导体封装的终止区上。
2.如权利要求1所述的半导体芯片级封装，其特征在于，所述的本体-源极短接结构为一种嵌入式栅极屏蔽。
3.如权利要求1所述的半导体芯片级封装，其特征在于，所述的本体-源极短接结构为一种嵌入式导电插塞。
4.如权利要求1所述的半导体芯片级封装，其特征在于，所述的本体-源极短接结构在半导体器件上分布源极。
5.如权利要求1所述的半导体芯片级封装，其特征在于，所述的半导体芯片级封装还包含一个设置在半导体封装外围的栅极环，用于所述的半导体器件的栅极垫和栅极区之间的互联。
6.如权利要求5所述的半导体芯片级封装，其特征在于，所述的半导体芯片级封装还包含一个设置在半导体封装外围的金属化的衬底环，用于直接连接到源极垫上。
7.如权利要求1所述的半导体芯片级封装，其特征在于，所述的每个单元还包含一个导电插塞，用于将漏极区域电连接到漏极金属上。
8.如权利要求7所述的半导体芯片级封装，其特征在于，所述的金属氧化物场效应管为一个底部源极横向扩散金属氧化物半导体器件，
9.如权利要求8所述的半导体芯片级封装，其特征在于，所述的底部源极横向扩散金属氧化物半导体器件的每个单元的源极接触点和源极区域之间形成的电接触包含一个顶部源极区、所述的衬底，以及一个在外延层中的复合下沉-沟道区，其中所述复合下沉-沟道区作为一个下沉区，将衬底电连接到顶部源极区，并作为一个形成金属氧化物半导体场效应管沟道的本体区域，其中嵌入式本体-源极短接结构将顶部源极区短接到下沉-沟道区。
10.如权利要求9所述的半导体芯片级封装，其特征在于，所述的底部-源极横向扩散金属氧化物半导体器件还包含一个设置在栅极区域下方的漂移区，与源极区域形成一距离，延伸至漏极区并围绕着漏极区。
11.如权利要求10所述的半导体芯片级封装，其特征在于，所述的复合下沉-沟道区延伸至漂移区下方，其掺杂电导性与漂移区相反，并补偿漂移区，以便降低源-漏电容。
12.如权利要求11所述的半导体芯片级封装，其特征在于，所述的底部-源极横向扩散金属氧化物半导体器件中的嵌入式本体-源极短接结构包含一个嵌入式栅极屏蔽层，此屏蔽层包含一个在栅极区域、源极区域和本体区域上方设置的导电层。
13.如权利要求12所述的半导体芯片级封装，其特征在于，所述的嵌入式栅极屏蔽层包含一层氮化钛或硅化钛金属。
14.如权利要求12所述的半导体芯片级封装，其特征在于，所述的源极垫位于嵌入式栅极屏蔽层上方。
15.如权利要求14所述的半导体芯片级封装，其特征在于，所述的嵌入式栅极屏蔽层将源极分布至整个半导体器件。
16.如权利要求14所述的半导体芯片级封装，其特征在于，所述的半导体芯片级封装还包含一个或更多的导电插塞，以便将源极垫连接到嵌入式栅极屏蔽层上。
17.如权利要求1所述的半导体芯片级封装，其特征在于，所述的金属氧化物半导体场效应管包含一个逆沟槽源极接地垂直沟道金属氧化物半导体场效应管器件。
18.如权利要求17所述的半导体芯片级封装，其特征在于，所述的逆沟槽源极接地垂直沟道金属氧化物半导体场效应管器件的每个单元还包含：
源极区和漏极区之间的一个垂直电流传导沟道，由设置在沟道侧壁上的一个垂直侧壁栅极区控制，通过附着在沟道侧壁上的栅极氧化层提供衬垫；
其中所述的嵌入式本体-源极短接结构为一个嵌入式导电插塞，从沟道的一个底面向下延伸，用于将半导体衬底中的本体区短接到设置在所述沟道底面下的源极区。
19.如权利要求18所述的半导体芯片级封装，其特征在于，所述的每个单元中的嵌入式导电插塞用于在多个单元中分布源极。
20.如权利要求18所述的半导体芯片级封装，其特征在于，所述的每个单元中的导电插塞包含一种钛、钴或钨的硅化物。
21.如权利要求18所述的半导体芯片级封装，其特征在于，所述的逆沟槽源极接地垂直沟道金属氧化物半导体场效应管器件的每个单元还包含：
一个设置在半导体衬底中的掺杂本体区，环绕着源极区域周围的沟道中较低的部分，其中掺杂本体区包含沿沟道侧壁的沟道；
一个设置在衬底顶面附近的漂移区，环绕沟道上部，并包围漏极区域；以及
一个设置在漂移区下方的连接区，向下延伸到掺杂沟道区，以便连接漂移区和掺杂沟道区。
22.如权利要求18所述的半导体芯片级封装，其特征在于，所述的半导体芯片级封装还包含一个设置在终止区和多个栅极流道中的栅极金属，所述的每个栅极流道都为多个单元的栅极区和设置在终止区中的栅极金属之间提供电连接。
23.一种用于制造半导体芯片级封装的方法，其特征在于，包含以下步骤：
形成一个半导体衬底；
在半导体衬底中的有源区形成多个单元，每个单元都包含一个栅极区、一个设置在半导体器件底部的源极、一个设置在半导体器件顶部的漏极区，以及为每个半导体器件中的源极区域分布衬底接触点；
在多个半导体器件上形成一个共漏极金属；
形成一个嵌入式本体-源极短接结构，放置在共漏极金属下面，并连接到源极区和源极垫上；
在共漏极金属上部，形成至少一个漏极垫；以及
在半导体衬底的终止区，形成至少一个源极垫和至少一个栅极垫；
其中漏极、源极和栅极垫都在半导体封装的一个表面上。
24.如权利要求23所述的半导体芯片级封装方法，其特征在于，所述的嵌入式本体-源极短接结构在多个单元分布源极。
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