CN110313066B - 用于最小化串扰的集成电路连接布置 - Google Patents

用于最小化串扰的集成电路连接布置 Download PDF

Info

Publication number
CN110313066B
CN110313066B CN201880012916.5A CN201880012916A CN110313066B CN 110313066 B CN110313066 B CN 110313066B CN 201880012916 A CN201880012916 A CN 201880012916A CN 110313066 B CN110313066 B CN 110313066B
Authority
CN
China
Prior art keywords
semiconductor die
front side
bottom semiconductor
electrically connected
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201880012916.5A
Other languages
English (en)
Other versions
CN110313066A (zh
Inventor
S.L.涂
M.A.斯图伯
B.塔斯巴斯
S.B.莫林
R.蒋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silanna Asia Pte Ltd
Original Assignee
Silanna Asia Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silanna Asia Pte Ltd filed Critical Silanna Asia Pte Ltd
Publication of CN110313066A publication Critical patent/CN110313066A/zh
Application granted granted Critical
Publication of CN110313066B publication Critical patent/CN110313066B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66696—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4001—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40141—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged on opposite sides of a substrate, e.g. mirror arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48108—Connecting bonding areas at different heights the connector not being orthogonal to a side surface of the semiconductor or solid-state body, e.g. fanned-out connectors, radial layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73213—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/086—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Container Filling Or Packaging Operations (AREA)

Abstract

一种半导体封装，包括：引线框架，其具有周边封装引线和接地电压引线；底部半导体管芯，其倒装芯片安装到所述引线框架；以及顶部半导体管芯。所述底部半导体管芯具有：第一正面有源层，其具有电连接到所述引线框架的第一正面电触点；第一背面部分；以及隐埋氧化物层，其位于所述第一正面有源层与所述第一背面部分之间。所述顶部半导体管芯安装到所述第一背面部分。所述第一正面有源层包括通过背面电连接经由所述隐埋氧化物层电连接到所述第一背面部分的电路。所述底部半导体管芯的所述第一背面部分通过所述第一正面电触点中的第一电触点电连接到所述接地电压引线，以最小化串扰。

Description

用于最小化串扰的集成电路连接布置
相关申请的交叉引用
本申请要求2017年12月22日提交且标题为“用于最小化串扰的集成电路连接布置(INTEGRATED CIRCUIT CONNECTION ARRANGEMENT FOR MINIMIZING CROSSTALK)”的美国非临时专利申请号15/853,357的优先权；该专利申请要求2017年2月20日提交且标题为“背面接触的集成式横向扩散MOS设备和方法(Backside Contact Integrated LaterallyDiffused MOS Apparatus and Methods)”的美国临时申请号62/461,117的权益，所述专利申请都以引用方式并入以用于所有目的。
背景技术
半导体功率装置是通常用作电力电子电路中的开关或整流器的专门装置。半导体功率装置可以使用横向扩散场效应晶体管(LDFET)来实施，诸如横向扩散金属氧化物半导体(LDMOS)晶体管。这些类型的晶体管的特征在于“横向扩散”区(或者低掺杂或轻掺杂漏极(LDD)区)，所述横向扩散区对应于掺杂强度低于核心漏极区的漏极区的延伸并且横向地延伸远离沟道。横向扩散区增加LDFET在关闭状态下通过吸收电场的原本将导致源极-漏极穿通的部分来处理较高电压以及在接通状态下通过防止大电位降在漏极-主体接口处累积来处理较大电流的能力，所述电位降累积原本将经由热载流子喷射到装置的主体中而导致装置的退化。
切换式电压调节器通常包括以同步方式不断地接通和断开以调节电压的两个半导体功率装置。该切换可能会产生负面地影响周围电路系统的电干扰(在一些情况下，表现为串扰)。串扰是由从一个电路到另一电路的不合需要(例如，电感、电容或导电)的耦合引起的现象。在其中封装有用于控制电力电子电路的集成电路以及电力电子电路本身的紧密包装的半导体封装中，电力电子电路与控制器电路之间的串扰可以导致不合需要的系统性能或行为。
发明内容
在一些实施例中，一种集成电路(IC)封装包括：引线框架，其具有周边封装引线和接地电压引线；底部半导体管芯；以及顶部半导体管芯。所述底部半导体管芯被倒装芯片安装到所述引线框架。所述底部半导体管芯包括：i)具有电连接到所述引线框架的第一正面电触点的第一正面有源层；ii)第一背面部分；以及iii)隐埋氧化物层。所述隐埋氧化物层位于所述第一正面有源层与所述第一背面部分之间。所述顶部半导体管芯包括：i)第二正面以及ii)第二背面。所述顶部半导体管芯的所述第二背面安装到所述底部半导体管芯的所述第一背面部分。所述底部半导体管芯的所述第一正面有源层包括通过背面电连接经由所述隐埋氧化物层电连接到所述第一背面部分的电路。所述第一正面电触点中的第一电触点电连接到所述背面电连接，并且所述底部半导体管芯的所述第一背面部分通过所述第一电触点电连接到所述引线框架的所述接地电压引线，以最小化串扰。
在一些实施例中，一种用于封装IC封装中的半导体装置的方法涉及提供引线框架，所述引线框架具有周边封装引线和接地电压引线。形成底部半导体管芯，所述底部半导体管芯包括：i)具有第一正面电触点的第一正面有源层；ii)第一背面部分；以及iii)隐埋氧化物层。所述隐埋氧化物层位于所述第一正面有源层与所述第一背面部分之间。所述底部半导体管芯被倒装芯片安装到所述引线框架。所述倒装芯片安装包括将所述底部半导体管芯的所述第一正面电触点电连接并物理地安装到所述引线框架，所述第一正面电触点中的第一电触点电连接并物理地安装到所述引线框架的所述接地电压引线。提供顶部半导体管芯。所述顶部半导体管芯包括：i)具有第二正面电触点的第二正面，以及ii)第二背面。所述顶部半导体管芯安装到所述底部半导体管芯，所述顶部半导体管芯的所述第二背面附接到所述底部半导体管芯的所述第一背面部分。所述底部半导体管芯的所述第一正面有源层包括通过相应的第一正面电连接电连接到所述第一正面电触点并通过第一正面连接经由所述隐埋氧化物层电连接到所述第一背面部分的电路。所述底部半导体管芯的所述第一背面部分通过所述第一背面连接和所述第一正面电触点中的所述第一电触点电连接到所述引线框架的所述接地电压引线，以最小化串扰。
附图说明
图1是结合一些实施例的高功率半导体开关的示例的电路图。
图2A是根据一些实施例的集成电路封装的简化图解性顶视正视图。
图2B是根据一些实施例的集成电路封装的简化图解性截面。
图2C是根据一些实施例的集成电路封装的简化图解性截面。
图3是根据一些实施例的集成电路封装的简化图解性截面。
具体实施方式
在以下描述中，相似的附图标记用来标识相似的元件。此外，附图意图以图解方式示出示例性实施例的主要特征。附图不意图描绘实际实施例的每个特征也不描绘所示元件的相对尺寸，并且未按比例绘制。
本文中描述的一些实施例提供一种半导体装置，所述半导体装置包括安装在底部半导体管芯的顶部上的顶部半导体管芯。底部半导体管芯是安装到半导体装置封装的引线框架上的倒装芯片，使得底部半导体管芯的背面部分向上取向，并且底部半导体管芯的正面部分向下取向。
底部半导体管芯的背面部分包括半导体衬底，诸如处理晶片。底部半导体的背面部分通过底部半导体管芯的正面部分的电触点电连接到引线框架的接地引线的底部半导体。在一些实施例中，该电连接包括穿过底部半导体的隐埋绝缘体层的导电路径。因而接地的底部半导体的背面部分有利地产生位于顶部半导体管芯下方且在底部半导体管芯的正面有源层上方的接地平面。该接地平面的存在有利地最小化顶部半导体管芯与底部半导体管芯之间的串扰。
在一些实施例中，顶部半导体管芯是向底部半导体管芯中形成的电路节点(例如，晶体管的栅极节点)提供控制信号的控制器管芯。在一些实施例中，底部半导体管芯包括集成式横向扩散场效应晶体管(LDFET)电路。此类LDFET电路包括到底部半导体管芯的背面部分的至少一个衬底触点，以减少所需的正面电连接的数量。通过这种方式，增大了底部半导体管芯的可用于容纳相对大的高性能电连接(例如，引线框架的电连接器，诸如能够传导高电流的金属带)的正面空间。这进而增加集成式LDFET功率装置电路的电路设计灵活性、性能和可制造性。在一些实施例中，具有衬底触点的LDFET与相同电路中的其他LDFET电隔离，以通过防止在连接到衬底的LDFET与没有连接到衬底的那些LDFET之间形成公共节点来进一步改进电路的性能。
仅出于说明目的，本公开在与图1所示的示例性高功率半导体开关电路10类似的实施例的背景下描述了单半导体管芯集成式LDFET电路的具体示例。相同或类似的教导可以用来制造适合于电力应用和非电力应用的其他单半导体管芯集成式LDFET电路。
高功率半导体开关电路10包括高侧场效应晶体管(FET)12和低侧FET 14。高侧FET12的高侧源极在相位节点16(V相位)处耦合到低侧FET 14的低侧漏极。高侧栅极节点18和低侧栅极节点20控制高侧FET 12和低侧FET 14的占空比，以将高侧FET 12的高侧漏极处的电压输入节点23处的输入电压(V输入)转换成相位节点16处的输出电压(V相位)。一般来说，FET12、14可以使用广泛多种半导体材料系统和技术中的任一种来制造，包括硅、锗和化合物半导体技术。
图2A示出了根据一些实施例的集成电路(IC)封装200的一部分的简化示例的顶视正视图，所述集成电路封装通常包括引线框架220、顶部半导体管芯222和底部半导体管芯230。IC封装200通常还包括接合线292a至292d。
一般来说，引线框架220包括电连接器275a至257c以及周边封装引线291a至291h。图2A或本文中的任一附图中示出的电连接器和/或周边封装引线的数量被示为简化示例。在一些实施例中，可以使用更多或更少的电连接器和/或周边封装引线。之后参考图2B至图2C讨论截面切割线233a至233b。
在所示的示例中，底部半导体管芯230体现集成负载点(POL)电压转换器，从而体现图1所示的高功率半导体开关电路10的示例性实现方式。然而，底部半导体管芯230的半导体装置可以是如本领域中已知的另一半导体装置。在所示的示例中，底部半导体管芯230通常包括背面部分231a(例如，处理晶片)和与背面部分相对的正面(图2B中示出的231b)。
顶部半导体管芯222通常包括正面223a上的顶部电触点224以及与正面223a相反的背面部分(例如，衬底，诸如处理晶片)(图2B中示出的223b)。在一些实施例中，顶部半导体管芯222是以下各项中的一者：(i)控制器管芯、(ii)块体半导体管芯、(iii)微处理器、(iv)微控制器，(v)数字信号处理器或(vi)如本领域中已知的另一半导体。在本文中描述的示例性实施例中，顶部半导体管芯222是用于功率开关电路的控制器管芯。在这种情况下，顶部半导体管芯222被配置成使底部半导体管芯230的POL电压转换器的晶体管的相应接通/断开状态同步。
如图所示，顶部半导体管芯222的与正面223a相对的背面物理地安装到底部半导体管芯230的背面部分231a。底部半导体管芯230的与背面部分231a相对的正面的相应电触点(图2B和图2C中示出)电耦合并电安装到引线框架的电连接器275a至275c。底部半导体管芯230的背面部分231a有利地产生接地平面，顶部半导体管芯222安装在所述接地平面上，由此减少顶部半导体管芯222与底部半导体管芯230之间的串扰。
顶部半导体管芯222的顶部电触点224中的一者或多者电耦合到周边封装引线291a至291h中的一者或多者、电耦合到引线框架220和/或电耦合到底部半导体管芯230，以接收或发送用于控制底部半导体管芯230中的高功率半导体开关电路的电子部件(例如，晶体管)的信号、命令和/或反馈。例如，顶部半导体管芯222的顶部电触点224的触点通过接合线292a至292b电连接到周边封装引线291a至291b并且通过接合线292c至292d电连接到电连接器275b至275c。
图2B示出了根据一些实施例的图2A中介绍的用于半导体装置的包括引线框架220的简化示例性集成电路(IC)封装200的一部分的图解性截面图。IC封装200的截面图是由图2A的切割线233a指示的穿过图2A的IC封装200的一部分截取的截面。
图2B的IC封装200包括图2A中介绍的元件，以及安装介质215、顶部半导体管芯222的背面223b和底部半导体管芯230的正面231b。
如图所示，接合线292a将周边封装引线291a电耦合到顶部半导体管芯222的顶部电触点224中的正面点触点。顶部半导体管芯222的背面223b通过安装介质215物理地安装到底部半导体管芯230的背面部分231a。在一些实施例中，安装介质215包括管芯附接粘合剂、烧结银、焊锡膏、热传导粘合剂，或适合于形成物理连接、热连接和/或电连接的任何物质。在一些实施例中，安装介质215是电绝缘材料。在一些实施例中，一个或多个其他中介层(例如，金属层或绝缘层)位于顶部半导体管芯222与底部半导体管芯230之间。
在一些实施例中，底部半导体管芯230的正面电触点包括铜柱或焊接凸点。底部半导体管芯230的第一正面电触点280电连接并物理地安装到电连接器275a，底部半导体管芯230的第二正面电触点282电连接并物理地安装到电连接器275b，并且底部半导体管芯230的第三正面电触点284电连接并物理地安装到电连接器275c(例如，各自通过管芯附接粘合剂或其他合适的安装技术)。
在一些实施例中，底部半导体管芯230的第一正面电触点280、第二正面电触点282和第三正面电触点284通常表示底部半导体管芯230的多个金属层中的顶部金属层。底部半导体管芯230被倒转或呈倒装芯片配置，使得底部半导体管芯230的“顶部”/“正面”和“底部”/“背面”在图中分别在底部和顶部上示出。为简单起见，省略了一些金属层、连接、接合线或其他特征。可以存在中介金属层、导电粘合剂、铜柱、焊接凸点或其他金属接合结构。
在一些实施例中，在底部半导体管芯230、引线框架220和/或顶部半导体管芯222之间进行至少五个电连接。参考图1，这五个电连接包括到电压输入节点23(V输入)的电连接、到相位节点16(V相位)的电连接、低侧FET 14的低侧源极到接地节点的电连接、到高侧栅极节点18的电连接，以及到低侧栅极节点20的电连接。
在一些实施例中，顶部半导体管芯222的背面223b上的背面电触点(未示出)电耦合到底部半导体管芯230的背面部分231a。在其中安装介质215导电的一些实施例中，安装介质215用于该电耦合。在其中安装介质215电绝缘的其他实施例中，顶部半导体管芯222的背面223b通过安装介质215与底部半导体管芯230的背面部分231a基本上电隔离。在任一实施例中，底部半导体管芯230的背面部分231a有利地提供用于最小化顶部半导体管芯222与底部半导体管芯230之间的串扰的接地平面。
图2C示出了根据一些实施例的用于半导体装置的包括引线框架220的简化示例性集成电路(IC)封装200的一部分的图解性截面图。图2C所示的IC封装200的截面图是由图2A的切割线233b指示的穿过图2A的IC封装200的一部分截取的截面。
图2C的IC封装200包括图2A至图2B中介绍的元件，以及底部半导体管芯230的第四正面电触点286。在一些实施例中，第四正面电触点286电耦合到底部半导体管芯230的晶体管的栅极触点。如图所示，第四正面电触点286电耦合并物理地安装到在底部半导体管芯230的下方延伸的周边封装引线291b。尽管第四正面电触点286被示为物理地安装到周边封装引线291b，但在其他实施例中，第四正面电触点286电耦合到周边封装引线291b(例如，通过接合线)，而不是物理地安装到周边封装引线291b。
在所示实施例中，接合线292b将周边封装引线291b电耦合到顶部半导体管芯222的顶部电触点224中的正面电触点，并且由此将第四正面电触点286电耦合到顶部半导体管芯222的正面电触点。
在一些实施例中，第四正面电触点286通常表示底部半导体管芯230的多个金属层中的顶部金属层。为简单起见，省略了一些金属层、连接、接合线或其他特征。可以存在中介金属层、导电粘合剂、铜柱、焊接凸点或其他金属接合结构。
图3示出了根据一些实施例的集成电路(IC)封装300的一部分的简化图解性截面侧视图，所述IC封装包括图2A至图2C中介绍的元件，包括引线框架220。为简单起见，省略了先前图中示出的引线框架220的部分。例如，从图3中省略了图2A的周边封装引线291a至291h，但它们是引线框架220的一部分。
在所示的简化示例性实施例中，半导体230是功率半导体管芯，从而体现图1的高功率半导体开关电路10。在该示例中，LDFET 32实施开关电路10的高侧FET 12，并且LDFET34实施开关电路10的低侧FET 14。在一个示例性配置中，高侧LDFET 32的第一正面电触点280对应于开关电路10的电压输入节点23，第二正面电触点282对应于开关电路10的相位节点16，并且电连接到第三正面电触点284的衬底45(例如，处理晶片)对应于开关电路10的接地节点。
LDFET 32的漏极区52电耦合到与第一正面电触点280连接的漏极触点56。LDFET32的源极区46电耦合到与第二正面电触点282电连接的源极触点54。LDFET 34的漏极区52’电耦合到与第二正面电触点282电连接的漏极触点56’。LDFET 34的源极区46’电耦合到与第三正面电触点284电连接的源极触点54’。因此，底部半导体管芯230的衬底45通过源极触点54’电耦合到第三正面电触点284。
第三正面电触点284进而电连接到电连接器275c，所述电连接器是引线框架220的接地电压引线。通过将衬底45耦合到接地，在顶部半导体管芯222与底部半导体管芯230之间形成接地平面，因为衬底45插入顶部半导体管芯222的大部分(如果不是全部的话)与底部半导体管芯230的其余层之间，由此最小化顶部半导体管芯222与底部半导体管芯230之间的串扰。
在一些实施例中，顶部半导体管芯222的正面电触点(例如，图2A所示的顶部电触点224)经由线接合和/或通过引线框架220电耦合到LDFET 32和/或LDFET 34的栅极节点。该配置使得顶部半导体管芯222能够控制高侧LDFET 32和低侧LDFET 34的接通/断开状态。在一些实施例中，高侧LDFET 32是p型晶体管，并且低侧LDFET34是n型晶体管。在其他实施例中，LDFET32、34两者是n型晶体管。在一些实施例中，LDFET 32、34两者同时地切换、利用两个栅极触点单独地切换，或者使用单个栅极触点一起切换(例如，其中高侧LDFET 32的栅极和低侧LDFET 34的栅极电耦合到单个栅极触点)。
在图3所示的高功率半导体开关电路10的示例性实现方式中，高侧LDFET 32的漏极触点56连接到电压输入节点23(参考图1)，高侧LDFET 32的源极触点54和低侧LDFET 34的漏极触点56’两者连接到相位节点16(参考图1)，并且低侧LDFET 34的源极触点54’连接到接地节点(参考图1)。如上文提及，其他节点连接布置是可能的。例如，这些其他连接布置包括第一LDFET与第二LDFET之间的任何连接布置，其包括(i)电连接到第一LDFET的源极和第二LDFET的漏极的公共节点，(ii)第一LDFET的漏极、第二LDFET的源极和公共节点中的至少一者电连接到半导体衬底，以及(iii)连接到第一LDFET的漏极、第二LDFET的源极和公共节点中的至少两者的至少两个正面电触点，它们没有电连接到半导体衬底。
高侧LDFET 32和低侧LDFET 34在底部半导体管芯230的正面有源层42中实施。衬底45在底部半导体管芯230的背面部分231a中。正面有源层42可以是半导体晶片的块体的掺杂部分、在半导体晶片的较大掺杂部分中形成的局部化井、绝缘体上半导体(SOI)晶片的有源层，以及在SOI晶片中形成的局部化井。在所示示例中，正面有源层42是在衬底45(例如，SOI衬底)上的隐埋氧化物层44上方形成的薄膜。在所示示例中，介电隔离屏障47在高侧LDFET 32与低侧LDFET 34之间从正面有源层42的顶部延伸到隐埋氧化物层44。在一些示例中，使用浅沟槽隔离(STI)过程形成介电隔离屏障47。
高侧LDFET 32包括在掺杂区48中形成的源极区46、具有在掺杂区51中形成的较重掺杂延伸区49的轻掺杂漏极(LDD)区50，以及漏极区52。源极区46、掺杂区48、LDD区50、延伸区49和漏极区52可以包括通过例如将杂质植入到正面有源层42中而形成的掺杂半导体材料。每个区46和48至52的掺杂半导体材料具有类似的导电类型(例如，n型或p型)。因此，每个区46和48至52可以由相同的掺杂剂种类形成，诸如通过植入一种掺杂剂原子。LDD区50具有比漏极区52低的掺杂剂浓度，并且也可以具有比源极区46低的掺杂剂浓度。LDD区50就其抵挡大电压的能力而言向LDFET提供作为功率装置的优越性能，并且在吸收大电流时不退化。LDD区50的存在向LDFET提供具有不对称的源极区和漏极区的特性。在一些方法中，LDD区50通常横向地从漏极区52延伸至少是掺杂区48从源极区46延伸的两倍远。
高侧LDFET 32还包括主体区60和深井区62，所述主体区和深井区具有与区46和48至52的导电类型相反的导电类型。深井区62在源极区46和主体区60的形成沟道的部分的下方横向地延伸。深井区62增强高侧LDFET 32承受大电压的能力，并且用来从主体区60移除多余的电荷载流子，以防止寄生的双极面结型晶体管在高侧LDFET 32的接通状态期间激活。
在正面有源层42的上方，高侧LDFET 32包括栅极结构，所述栅极结构包括栅极屏蔽66和栅极电极68。栅极电极68分别通过介电材料70、72与正面有源层42和栅极屏蔽66电绝缘。
漏极区52可以是高掺杂漏极区，并且可以在漏极触点56与LDD区50之间形成导电路径。电绝缘材料74(例如，层间电介质)电隔离并防止正面有源层42上方的电部件无意间耦合。一般来说，电绝缘材料74和介电材料70、72可以是相同或类似的材料。另外，在某些方法中，不论它们何时和如何形成，绝缘材料74和介电材料70、72的组合都可以概念化为成品装置中的单个绝缘层。
响应于向栅极电极68施加电压(例如，通过顶部半导体管芯222)，在源极触点54与漏极触点56之间形成导电路径。源极触点54与漏极触点56之间的导电路径包括在施加到栅极电极68的前述电压的影响下选择性地在主体区60中形成的沟道。在形成沟道时，晶体管被称为接通。在未形成沟道并且源极触点54与漏极触点56之间不存在导电路径时，晶体管被称为断开。在这种情形下不存在导电路径，因为源极区46和漏极区50、52具有与主体区60相反的导电类型，使得在它们的接口处形成二极管结。
栅极屏蔽66与源极触点54处于欧姆接触。栅极屏蔽66是使高侧FET 32更适合高功率应用的另一特征。通过将电压屏蔽66偏压到给定的电压，屏蔽漏极触点56上的高功率信号以免对栅极区产生明显影响。尽管栅极屏蔽66被示为欧姆耦合到源极触点54，但栅极屏蔽66也可以独立地偏压。在一些示例中，栅极屏蔽66和源极触点54可以在两个不同的步骤中形成，并且可以包括两个不同种类的材料。然而，在这种情况下，此类特征在多数情形下对装置的操作无关紧要，因为栅极屏蔽66和源极触点54是具有从介电材料74上方一直到正面有源层42的表面的不间断欧姆接触的高导电材料的一个连续区。因此，栅极屏蔽66和源极触点54的组合可以概念化为单个源极触点。
一般来说，源极触点54和漏极触点56使得能够从可以或可以不与相同集成电路上的LDFET集成的其他电路系统电连接到高侧LDFET32。源极区46可以经由在源极区46的表面上形成的硅化物层电耦合到源极触点54。更一般地，源极区46可以使用在结构的两个区之间形成欧姆或非整流接触的任何过程耦合到源极触点54。漏极触点56与漏极区52之间的连接可以包括上文参考源极触点54和源极区46描述的变型中的任一者。源极触点54和漏极触点56可以包括金属、金属合金、金属硅化物，或导电半导体材料，诸如掺杂多晶硅。示例性金属、金属合金和金属硅化物可以各自包括铜、钨、钼和铝。
在图3所示的示例中，正面有源层42的低侧LDFET34的元件中的一些与正面有源层42的高侧LDFET32的对应元件以类似的方式起作用。就这点而言，低侧LDFET34的功能类似的元件用高侧LDFET32的对应元件的附图标记后面加撇号来标记。例如，与高侧LDFET 32的功能类似漏极区52对应的低侧LDFET 34的漏极区用附图标记52’标记。因此，低侧LDFET 34包括以下元件：源极区46’、掺杂区48’、具有在掺杂区51’中形成的较重掺杂延伸区49’的LDD区50’、漏极区52’、源极触点54’、漏极触点56’、主体区60’、深井区62’、栅极屏蔽66’、栅极电极68’和介电材料70’、72’。
在该示例中，低侧LDFET 34的源极触点54’不仅从正面有源层42穿过源极区46’和掺杂区48’延伸到深井区62’，而且穿过深井区62’和隐埋氧化物层44并延伸到衬底45中。通过这种方式，低侧LDFET 34的源极触点54’提供到衬底45的源极向下电连接，并且由此到对应于高功率半导体开关电路10的接地节点的衬底45。
第二正面电触点282(相位节点)将高侧LDFET 32的源极触点54与低侧LDFET 34的源极触点56’电互连，并且由此形成用于高侧LDFET 32的源极区46和低侧LDFET 34的漏极区52’的公共节点。应注意，隐埋氧化物层44和介电隔离屏蔽47将高侧LDFET 32与衬底45电隔离，以防止在功率开关电路10的操作期间与低侧LDFET 34的源极触点54’形成公共节点。
半导体管芯230安装在IC封装300的引线框架220上并且在其部分内。如图所示，底部半导体管芯230的第一正面电触点280电耦合并物理地安装到电连接器275a(引线框架220的输入电压节点引线)，第二正面电触点282电耦合并物理地安装到电连接器275b(引线框架220的相位节点引线)，并且第三正面电触点284电耦合并物理地安装到电连接器275c(引线框架220的接地电压引线)。
在顶部半导体管芯222与底部半导体管芯230之间进行类似于图2A至图2C所示的那些的附加电连接，但为了简单起见，在图3中省略所述附加电连接。
顶部半导体管芯222的背面223b物理地安装到底部半导体管芯230的背面部分231a。包括衬底45的背面部分231a耦合到引线框架220的电连接器275c(接地电压引线)。这有利地在顶部半导体管芯222与底部半导体管芯230之间产生接地平面，以最小化这些管芯之间的串扰。
图3所示的金属层(例如，第一正面电触点280)通常表示根据需要对连接进行布线的多个金属层，包括用于半导体管芯垫的顶部金属层以及在半导体管芯垫与正面有源层42的绝缘材料(例如，74)之间的附加金属层。为简单起见，省略了一些金属层、连接、接合线或其他特征。可以存在中介金属层、导电粘合剂、铜柱、焊接凸点或其他金属接合结构。
为简单起见，简化的图解性截面侧视图仅示出了单个晶体管“指状件”。在一些实施例中，多个晶体管指状件并联地连接以增加所体现的电路的功率处理能力，并且减小所体现的电路的应用所需要的总电阻。
已经详细参考所公开的本发明的实施例，本发明的一个或多个示例已经在附图中示出。每个示例已经通过解释本技术而不是限制本技术的方式提供。事实上，尽管已经关于本发明的具体实施例详细地描述了本说明书，但将了解，本领域技术人员在获得对前述内容的理解后可以容易地设想出这些实施例的替代、变型和等效物。例如，作为一个实施例的一部分示出或描述的特征可以与另一实施例一起使用以产生又一实施例。因此，本主题意图涵盖在所附权利要求及其等效物的范围内的所有此类修改和变化。在不脱离所附权利要求中具体地阐述的本发明的范围的情况下，对本发明的这些和其他修改和变型可以由本领域的一般技术人员实践。此外，本领域的一般技术人员将理解，前述描述仅仅是示例，并且不意图限制本发明。

Claims (20)

1.一种集成电路封装，其包括：
引线框架，其具有周边封装引线和接地电压引线；
底部半导体管芯，所述底部半导体管芯是安装到所述引线框架的倒装芯片，所述底部半导体管芯包括：i)第一正面有源层，其具有电连接到所述引线框架的第一正面电触点；ii)第一背面部分；以及iii)隐埋氧化物层，所述隐埋氧化物层位于所述第一正面有源层与所述第一背面部分之间；以及
顶部半导体管芯，所述顶部半导体管芯包括：i)第二正面；以及ii)第二背面，所述顶部半导体管芯的所述第二背面安装到所述底部半导体管芯的所述第一背面部分；
其中：
所述底部半导体管芯的所述第一正面有源层包括通过背面电连接经由所述隐埋氧化物层电连接到所述第一背面部分的电路；
所述第一正面电触点中的第一电触点电连接到所述背面电连接；并且
所述底部半导体管芯的所述第一背面部分通过所述第一电触点电连接到所述引线框架的所述接地电压引线，以最小化串扰。
2.根据权利要求1所述的集成电路封装，其中：
所述底部半导体管芯是功率半导体管芯。
3.根据权利要求1所述的集成电路封装，其中：
所述顶部半导体管芯的所述第二正面的电触点电耦合到所述周边封装引线的第一组。
4.根据权利要求3所述的集成电路封装，其中：
所述顶部半导体管芯是控制器管芯。
5.根据权利要求1所述的集成电路封装，其中：
所述底部半导体管芯的所述电路包括两个或更多个晶体管；
所述两个或更多个晶体管中的至少一者电连接到所述底部半导体管芯的所述第一正面电触点；并且
所述两个或更多个晶体管中的至少一者电连接到所述底部半导体管芯的所述第一背面部分。
6.根据权利要求5所述的集成电路封装，其中：
所述两个或更多个晶体管包括高侧晶体管和低侧晶体管；
所述高侧晶体管包括高侧源极、高侧漏极和高侧栅极；
所述低侧晶体管包括低侧源极、低侧漏极和低侧栅极；并且
所述底部半导体管芯的所述第一背面部分通过所述隐埋氧化物层电连接到所述低侧源极。
7.根据权利要求6所述的集成电路封装，其中：
所述顶部半导体管芯的所述第二正面的电触点电连接到所述高侧栅极或所述低侧栅极中的一者或两者。
8.根据权利要求7所述的集成电路封装，其中：
所述顶部半导体管芯的所述第二正面的所述电触点通过所述引线框架的周边封装引线电连接到所述高侧栅极或所述低侧栅极中的所述一者或两者。
9.根据权利要求6所述的集成电路封装，其中：
所述底部半导体管芯的所述第一正面电触点中的所述第一电触点电连接到所述低侧源极。
10.根据权利要求9所述的集成电路封装，其中：
所述底部半导体管芯的所述第一正面电触点中的第二电触点将所述低侧漏极电耦合到所述高侧源极；并且
所述第二电触点电耦合并物理地安装到所述引线框架的相位节点引线。
11.根据权利要求10所述的集成电路封装，其中：
所述底部半导体管芯的所述第一正面电触点中的第三电触点电耦合到所述高侧漏极；并且
所述第三电触点电耦合并物理地安装到所述引线框架的输入电压节点引线。
12.一种用于封装集成电路封装中的半导体装置的方法，其包括：
提供引线框架，所述引线框架具有周边封装引线和接地电压引线；
形成底部半导体管芯，所述底部半导体管芯包括：i)具有第一正面电触点的第一正面有源层；ii)第一背面部分；以及iii)隐埋氧化物层，所述隐埋氧化物层位于所述第一正面有源层与所述第一背面部分之间；
将所述底部半导体管芯倒装芯片安装到所述引线框架，所述倒装芯片安装包括将所述底部半导体管芯的所述第一正面电触点电连接并物理地安装到所述引线框架，所述第一正面电触点中的第一电触点电连接并物理地安装到所述引线框架的所述接地电压引线；
提供顶部半导体管芯，所述顶部半导体管芯包括：i)具有第二正面电触点的第二正面；以及ii)第二背面；以及
将所述顶部半导体管芯安装到所述底部半导体管芯，所述顶部半导体管芯的所述第二背面附接到所述底部半导体管芯的所述第一背面部分；
其中：
所述底部半导体管芯的所述第一正面有源层包括通过相应的第一正面电连接来电连接到所述第一正面电触点并通过第一背面电连接经由所述隐埋氧化物层电连接到所述第一背面部分的电路；并且
所述底部半导体管芯的所述第一背面部分通过所述第一背面电连接和所述第一正面电触点中的所述第一电触点电连接到所述引线框架的所述接地电压引线，以最小化串扰。
13.根据权利要求12所述的方法，其中：
所述顶部半导体管芯的所述第二正面电触点中的电触点电耦合到所述周边封装引线的第一组。
14.根据权利要求12所述的方法，其中：
所述底部半导体管芯包括两个或更多个晶体管；
所述两个或更多个晶体管中的至少一者电连接到所述底部半导体管芯的所述第一正面电触点；并且
所述两个或更多个晶体管中的至少一者电连接到所述底部半导体管芯的所述第一背面部分。
15.根据权利要求14所述的方法，其中：
所述两个或更多个晶体管包括高侧晶体管和低侧晶体管；
所述高侧晶体管包括高侧源极、高侧漏极和高侧栅极；
所述低侧晶体管包括低侧源极、低侧漏极和低侧栅极；并且
所述底部半导体管芯的所述第一背面部分通过所述隐埋氧化物层电连接到所述低侧源极。
16.根据权利要求15所述的方法，其中：
所述顶部半导体管芯的所述第二正面电触点中的顶部电触点电连接到所述高侧栅极或所述低侧栅极中的一者或两者。
17.根据权利要求16所述的方法，其中：
所述顶部电触点通过所述引线框架的周边封装引线电连接到所述高侧栅极或所述低侧栅极中的所述一者或两者。
18.根据权利要求15所述的方法，其中：
所述底部半导体管芯的所述第一正面电触点中的所述第一电触点电连接到所述低侧源极。
19.根据权利要求18所述的方法，其中：
所述底部半导体管芯的所述第一正面电触点中的第二电触点将所述低侧漏极电耦合到所述高侧源极；并且
所述第二电触点电耦合并物理地安装到所述引线框架的相位节点引线。
20.根据权利要求19所述的方法，其中：
所述底部半导体管芯的所述第一正面电触点中的第三电触点电耦合到所述高侧漏极；并且
所述第三电触点电耦合并物理地安装到所述引线框架的输入电压节点引线。
CN201880012916.5A 2017-02-20 2018-02-14 用于最小化串扰的集成电路连接布置 Active CN110313066B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762461117P 2017-02-20 2017-02-20
US62/461,117 2017-02-20
US15/853,357 US10192989B2 (en) 2017-02-20 2017-12-22 Integrated circuit connection arrangement for minimizing crosstalk
US15/853,357 2017-12-22
PCT/IB2018/050905 WO2018150337A1 (en) 2017-02-20 2018-02-14 Integrated circuit connection arrangement for minimizing crosstalk

Publications (2)

Publication Number Publication Date
CN110313066A CN110313066A (zh) 2019-10-08
CN110313066B true CN110313066B (zh) 2024-02-13

Family

ID=61598720

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201880012873.0A Active CN110337719B (zh) 2017-02-20 2018-02-14 引线框架和集成电路连接布置
CN201880012916.5A Active CN110313066B (zh) 2017-02-20 2018-02-14 用于最小化串扰的集成电路连接布置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201880012873.0A Active CN110337719B (zh) 2017-02-20 2018-02-14 引线框架和集成电路连接布置

Country Status (4)

Country Link
US (5) US9923059B1 (zh)
CN (2) CN110337719B (zh)
TW (2) TWI773732B (zh)
WO (2) WO2018150337A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10804186B2 (en) * 2017-05-12 2020-10-13 Mitsubishi Electric Corporation Semiconductor module and power converter
CN109671773B (zh) * 2017-10-16 2020-05-05 苏州能讯高能半导体有限公司 半导体器件及其制造方法
CN108172621A (zh) * 2018-01-19 2018-06-15 矽力杰半导体技术(杭州)有限公司 Ldmos晶体管及其制造方法
US11088046B2 (en) * 2018-06-25 2021-08-10 Semiconductor Components Industries, Llc Semiconductor device package with clip interconnect and dual side cooling
TWI682540B (zh) * 2018-07-24 2020-01-11 新唐科技股份有限公司 半導體裝置及其形成方法
US20200194459A1 (en) * 2018-12-18 2020-06-18 Vanguard International Semiconductor Corporation Semiconductor devices and methods for fabricating the same
US10950546B1 (en) * 2019-09-17 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including back side power supply circuit
US11282955B2 (en) * 2020-05-20 2022-03-22 Silanna Asia Pte Ltd LDMOS architecture and method for forming
CN116169171B (zh) * 2021-11-25 2024-05-14 苏州华太电子技术股份有限公司 Soi-ldmos器件及其制作方法
US20240153876A1 (en) * 2022-11-03 2024-05-09 Globalfoundries Singapore Pte. Ltd. Transistors having backside contact structures

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101378053A (zh) * 2007-08-31 2009-03-04 万国半导体股份有限公司 高、低压侧n沟道金属氧化物半导体场效应晶体管组合封装
CN203882995U (zh) * 2013-03-13 2014-10-15 半导体元件工业有限责任公司 半导体组件

Family Cites Families (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4738936A (en) 1983-07-01 1988-04-19 Acrian, Inc. Method of fabrication lateral FET structure having a substrate to source contact
US5559044A (en) 1992-09-21 1996-09-24 Siliconix Incorporated BiCDMOS process technology
US5548150A (en) 1993-03-10 1996-08-20 Kabushiki Kaisha Toshiba Field effect transistor
DE69326543T2 (de) 1993-04-28 2000-01-05 Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania Monolithisch integrierte Struktur einer elektronischen Vorrichtung mit einer bestimmten unidirektionalen Konduktionsschwellenspannung
US5365102A (en) 1993-07-06 1994-11-15 North Carolina State University Schottky barrier rectifier with MOS trench
US5378912A (en) 1993-11-10 1995-01-03 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a lateral drift region
US5382818A (en) 1993-12-08 1995-01-17 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode
US6124179A (en) 1996-09-05 2000-09-26 Adamic, Jr.; Fred W. Inverted dielectric isolation process
US6078090A (en) 1997-04-02 2000-06-20 Siliconix Incorporated Trench-gated Schottky diode with integral clamping diode
US6049108A (en) 1995-06-02 2000-04-11 Siliconix Incorporated Trench-gated MOSFET with bidirectional voltage clamping
DE19647324B4 (de) 1995-11-15 2013-06-27 Denso Corporation Halbleiterbauelement
US6831331B2 (en) 1995-11-15 2004-12-14 Denso Corporation Power MOS transistor for absorbing surge current
KR100187635B1 (ko) 1996-03-20 1999-07-01 김충환 단락 애노우드 수평형 절연 게이트 바이폴라 트랜지스터
US5818084A (en) 1996-05-15 1998-10-06 Siliconix Incorporated Pseudo-Schottky diode
KR100225411B1 (ko) 1997-03-24 1999-10-15 김덕중 LDMOS(a lateral double-diffused MOS) 트랜지스터 소자 및 그의 제조 방법
US5889310A (en) 1997-04-21 1999-03-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with high breakdown voltage island region
US5869875A (en) 1997-06-10 1999-02-09 Spectrian Lateral diffused MOS transistor with trench source contact
US6294838B1 (en) 1997-09-24 2001-09-25 Utron Technology Inc. Multi-chip stacked package
US6355501B1 (en) * 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
US6692998B2 (en) 2000-11-30 2004-02-17 International Business Machines Corporation Integrated high quality diode
US6794719B2 (en) 2001-06-28 2004-09-21 Koninklijke Philips Electronics N.V. HV-SOI LDMOS device with integrated diode to improve reliability and avalanche ruggedness
WO2003036699A2 (en) 2001-10-23 2003-05-01 Cambridge Semiconductor Limited Lateral semiconductor-on-insulator structure and corresponding manufacturing methods
US6492244B1 (en) 2001-11-21 2002-12-10 International Business Machines Corporation Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices
KR100867574B1 (ko) 2002-05-09 2008-11-10 페어차일드코리아반도체 주식회사 고전압 디바이스 및 그 제조방법
US6855985B2 (en) 2002-09-29 2005-02-15 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
US7719054B2 (en) 2006-05-31 2010-05-18 Advanced Analogic Technologies, Inc. High-voltage lateral DMOS device
US7576388B1 (en) 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
KR100948139B1 (ko) 2003-04-09 2010-03-18 페어차일드코리아반도체 주식회사 높은 브레이크다운 전압 및 낮은 온 저항을 위한 다중전류 이동 경로를 갖는 수평형 이중-확산 모스 트랜지스터
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US6900538B2 (en) 2003-06-03 2005-05-31 Micrel, Inc. Integrating chip scale packaging metallization into integrated circuit die structures
US7273771B2 (en) 2004-02-09 2007-09-25 International Rectifier Corporation Common MOSFET process for plural devices
JP2006019518A (ja) 2004-07-01 2006-01-19 Seiko Instruments Inc 横型トレンチｍｏｓｆｅｔ
TWI234261B (en) 2004-09-10 2005-06-11 Touch Micro System Tech Method of forming wafer backside interconnects
US7466006B2 (en) 2005-05-19 2008-12-16 Freescale Semiconductor, Inc. Structure and method for RESURF diodes with a current diverter
EP1742270A1 (en) 2005-07-06 2007-01-10 STMicroelectronics S.r.l. MOS transistor having a trench-gate and method of manufacturing the same
US7282765B2 (en) 2005-07-13 2007-10-16 Ciclon Semiconductor Device Corp. Power LDMOS transistor
US8692324B2 (en) 2005-07-13 2014-04-08 Ciclon Semiconductor Device Corp. Semiconductor devices having charge balanced structure
US7589378B2 (en) 2005-07-13 2009-09-15 Texas Instruments Lehigh Valley Incorporated Power LDMOS transistor
US7235845B2 (en) 2005-08-12 2007-06-26 Ciclon Semiconductor Device Corp. Power LDMOS transistor
US7420247B2 (en) 2005-08-12 2008-09-02 Cicion Semiconductor Device Corp. Power LDMOS transistor
TWI273718B (en) 2005-10-12 2007-02-11 Advanced Semiconductor Eng Lead frame base package structure with high-density of foot prints arrangement
US7560808B2 (en) 2005-10-19 2009-07-14 Texas Instruments Incorporated Chip scale power LDMOS device
DE102006053145B4 (de) 2005-11-14 2014-07-10 Denso Corporation Halbleitervorrichtung mit Trennungsbereich
US7285849B2 (en) * 2005-11-18 2007-10-23 Fairchild Semiconductor Corporation Semiconductor die package using leadframe and clip and method of manufacturing
US7375371B2 (en) 2006-02-01 2008-05-20 International Business Machines Corporation Structure and method for thermally stressing or testing a semiconductor device
US7446375B2 (en) 2006-03-14 2008-11-04 Ciclon Semiconductor Device Corp. Quasi-vertical LDMOS device having closed cell layout
WO2008003041A2 (en) 2006-06-28 2008-01-03 Great Wall Semiconductor Corporation Circuit and method of reducing body diode reverse recovery time of lateral power semiconduction devices
US7605446B2 (en) 2006-07-14 2009-10-20 Cambridge Semiconductor Limited Bipolar high voltage/power semiconductor device having first and second insulated gated and method of operation
US7554154B2 (en) 2006-07-28 2009-06-30 Alpha Omega Semiconductor, Ltd. Bottom source LDMOSFET structure and method
US7550318B2 (en) 2006-08-11 2009-06-23 Freescale Semiconductor, Inc. Interconnect for improved die to substrate electrical coupling
US7622793B2 (en) 2006-12-21 2009-11-24 Anderson Richard A Flip chip shielded RF I/O land grid array package
US7952145B2 (en) 2007-02-20 2011-05-31 Texas Instruments Lehigh Valley Incorporated MOS transistor device in common source configuration
JP2008251067A (ja) 2007-03-29 2008-10-16 Hitachi Ltd ディスクアレイ装置
US7598128B2 (en) 2007-05-22 2009-10-06 Sharp Laboratories Of America, Inc. Thin silicon-on-insulator double-diffused metal oxide semiconductor transistor
US7713821B2 (en) 2007-06-25 2010-05-11 Sharp Laboratories Of America, Inc. Thin silicon-on-insulator high voltage auxiliary gated transistor
US7768123B2 (en) 2007-09-26 2010-08-03 Fairchild Semiconductor Corporation Stacked dual-die packages, methods of making, and systems incorporating said packages
US7745846B2 (en) 2008-01-15 2010-06-29 Ciclon Semiconductor Device Corp. LDMOS integrated Schottky diode
US8174071B2 (en) 2008-05-02 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. High voltage LDMOS transistor
US7745920B2 (en) 2008-06-10 2010-06-29 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
WO2010014281A1 (en) 2008-07-30 2010-02-04 Maxpower Semiconductor Inc. Semiconductor on insulator devices containing permanent charge
US7994609B2 (en) 2008-11-21 2011-08-09 Xilinx, Inc. Shielding for integrated capacitors
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US20100171543A1 (en) 2009-01-08 2010-07-08 Ciclon Semiconductor Device Corp. Packaged power switching device
US8193559B2 (en) 2009-01-27 2012-06-05 Infineon Technologies Austria Ag Monolithic semiconductor switches and method for manufacturing
US7829947B2 (en) 2009-03-17 2010-11-09 Alpha & Omega Semiconductor Incorporated Bottom-drain LDMOS power MOSFET structure having a top drain strap
US8101993B2 (en) 2009-03-18 2012-01-24 Force Mos Technology Co., Ltd. MSD integrated circuits with shallow trench
US8395191B2 (en) 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US8138049B2 (en) 2009-05-29 2012-03-20 Silergy Technology Fabrication of lateral double-diffused metal oxide semiconductor (LDMOS) devices
US8288820B2 (en) * 2009-06-15 2012-10-16 Texas Instruments Incorporated High voltage power integrated circuit
JP5534298B2 (ja) 2009-06-16 2014-06-25 ルネサスエレクトロニクス株式会社 半導体装置
US9257375B2 (en) * 2009-07-31 2016-02-09 Alpha and Omega Semiconductor Inc. Multi-die semiconductor package
US8120105B2 (en) 2009-07-31 2012-02-21 Micrel, Inc. Lateral DMOS field effect transistor with reduced threshold voltage and self-aligned drift region
US20120326287A1 (en) * 2011-06-27 2012-12-27 National Semiconductor Corporation Dc/dc convertor power module package incorporating a stacked controller and construction methodology
US8174070B2 (en) 2009-12-02 2012-05-08 Alpha And Omega Semiconductor Incorporated Dual channel trench LDMOS transistors and BCD process with deep trench isolation
US8547162B2 (en) 2009-12-23 2013-10-01 Texas Instruments Incorporated Integration of MOSFETs in a source-down configuration
US20110148376A1 (en) 2009-12-23 2011-06-23 Texas Instruments Incorporated Mosfet with gate pull-down
US8582317B2 (en) 2010-05-26 2013-11-12 Semiconductor Components Industries, Llc Method for manufacturing a semiconductor component and structure therefor
US8294210B2 (en) 2010-06-15 2012-10-23 Texas Instruments Incorporated High voltage channel diode
JP5043990B2 (ja) 2010-06-18 2012-10-10 シャープ株式会社 半導体装置およびその製造方法
US8722503B2 (en) 2010-07-16 2014-05-13 Texas Instruments Incorporated Capacitors and methods of forming
US8217452B2 (en) 2010-08-05 2012-07-10 Atmel Rousset S.A.S. Enhanced HVPMOS
KR101888369B1 (ko) 2010-10-12 2018-08-14 퀄컴 인코포레이티드 박형 기판을 갖는 수직 반도체 디바이스
US9159825B2 (en) 2010-10-12 2015-10-13 Silanna Semiconductor U.S.A., Inc. Double-sided vertical semiconductor device with thinned substrate
US8426952B2 (en) 2011-01-14 2013-04-23 International Rectifier Corporation Stacked half-bridge package with a common conductive leadframe
US8674497B2 (en) 2011-01-14 2014-03-18 International Business Machines Corporation Stacked half-bridge package with a current carrying layer
US20120228696A1 (en) * 2011-03-07 2012-09-13 Texas Instruments Incorporated Stacked die power converter
US9842797B2 (en) 2011-03-07 2017-12-12 Texas Instruments Incorporated Stacked die power converter
WO2012141355A1 (ko) * 2011-04-15 2012-10-18 주식회사 블리스팩 재 밀봉이 가능한 블리스터 포장용기
TWI469311B (zh) * 2011-04-29 2015-01-11 萬國半導體股份有限公司 聯合封裝的功率半導體元件
US8436429B2 (en) 2011-05-29 2013-05-07 Alpha & Omega Semiconductor, Inc. Stacked power semiconductor device using dual lead frame and manufacturing method
US8614480B2 (en) 2011-07-05 2013-12-24 Texas Instruments Incorporated Power MOSFET with integrated gate resistor and diode-connected MOSFET
US9524957B2 (en) 2011-08-17 2016-12-20 Intersil Americas LLC Back-to-back stacked dies
US9269653B2 (en) 2012-06-27 2016-02-23 Mediatek Inc. SGS or GSGSG pattern for signal transmitting channel, and PCB assembly, chip package using such SGS or GSGSG pattern
US8965790B2 (en) * 2012-06-27 2015-02-24 Bank Of America Corporation Readable indicia for fuel purchase
US9412881B2 (en) 2012-07-31 2016-08-09 Silanna Asia Pte Ltd Power device integration on a common substrate
US8674440B2 (en) 2012-07-31 2014-03-18 Io Semiconductor Inc. Power device integration on a common substrate
US8847310B1 (en) 2012-07-31 2014-09-30 Azure Silicon LLC Power device integration on a common substrate
US8994105B2 (en) 2012-07-31 2015-03-31 Azure Silicon LLC Power device integration on a common substrate
US8928116B2 (en) 2012-07-31 2015-01-06 Silanna Semiconductor U.S.A., Inc. Power device integration on a common substrate
US9064705B2 (en) 2012-12-13 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of packaging with interposers
US9324838B2 (en) 2013-01-11 2016-04-26 Stmicroelectronics S.R.L. LDMOS power semiconductor device and manufacturing method of the same
US9847284B2 (en) 2013-01-29 2017-12-19 Apple Inc. Stacked wafer DDR package
US9589929B2 (en) 2013-03-14 2017-03-07 Vishay-Siliconix Method for fabricating stack die package
US9466536B2 (en) 2013-03-27 2016-10-11 Qualcomm Incorporated Semiconductor-on-insulator integrated circuit with back side gate
US8748245B1 (en) 2013-03-27 2014-06-10 Io Semiconductor, Inc. Semiconductor-on-insulator integrated circuit with interconnect below the insulator
US9214415B2 (en) 2013-04-11 2015-12-15 Texas Instruments Incorporated Integrating multi-output power converters having vertically stacked semiconductor chips
KR101977994B1 (ko) * 2013-06-28 2019-08-29 매그나칩 반도체 유한회사 반도체 패키지
US9412911B2 (en) 2013-07-09 2016-08-09 The Silanna Group Pty Ltd Optical tuning of light emitting semiconductor junctions
US9269699B2 (en) * 2014-05-09 2016-02-23 Alpha And Omega Semiconductor Incorporated Embedded package and method thereof
US20160005675A1 (en) * 2014-07-07 2016-01-07 Infineon Technologies Ag Double sided cooling chip package and method of manufacturing the same
US20160365334A1 (en) * 2015-06-09 2016-12-15 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same
DE102016101676B3 (de) * 2016-01-29 2017-07-13 Infineon Technologies Ag Elektrische schaltung, die eine halbleitervorrichtung mit einem ersten transistor und einem zweiten transistor und eine steuerschaltung enthält
US10083897B2 (en) 2017-02-20 2018-09-25 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101378053A (zh) * 2007-08-31 2009-03-04 万国半导体股份有限公司 高、低压侧n沟道金属氧化物半导体场效应晶体管组合封装
CN203882995U (zh) * 2013-03-13 2014-10-15 半导体元件工业有限责任公司 半导体组件

Also Published As

Publication number Publication date
CN110337719A (zh) 2019-10-15
US20180240904A1 (en) 2018-08-23
CN110313066A (zh) 2019-10-08
WO2018150337A1 (en) 2018-08-23
US10446687B2 (en) 2019-10-15
US20180240740A1 (en) 2018-08-23
WO2018150339A1 (en) 2018-08-23
CN110337719B (zh) 2024-02-13
US20190157446A1 (en) 2019-05-23
TWI755485B (zh) 2022-02-21
TW201842638A (zh) 2018-12-01
US10424666B2 (en) 2019-09-24
US10192989B2 (en) 2019-01-29
TW201842639A (zh) 2018-12-01
US9923059B1 (en) 2018-03-20
TWI773732B (zh) 2022-08-11
US10249759B2 (en) 2019-04-02
US20180240876A1 (en) 2018-08-23

Similar Documents

Publication Publication Date Title
CN110313066B (zh) 用于最小化串扰的集成电路连接布置
US10431598B2 (en) Vertical semiconductor device with thinned substrate
US10079230B2 (en) Double-sided vertical semiconductor device with thinned substrate
US11335627B2 (en) Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
US9431394B2 (en) Power semiconductor package with gate and field electrode leads

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant