TWI773732B - 電子設備及用於封裝半導體裝置之方法 - Google Patents

電子設備及用於封裝半導體裝置之方法 Download PDF

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TWI773732B
TWI773732B TW107105557A TW107105557A TWI773732B TW I773732 B TWI773732 B TW I773732B TW 107105557 A TW107105557 A TW 107105557A TW 107105557 A TW107105557 A TW 107105557A TW I773732 B TWI773732 B TW I773732B
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electrical contact
low
electrically coupled
semiconductor die
electrical
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TW107105557A
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TW201842638A (zh
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尚暉 杜
麥可 A. 斯圖柏
比夫魯茲 塔斯巴斯
斯圖爾特 B. 摩林
蔣鑫
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新加坡商西拉娜亞洲私人有限公司
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Abstract

一種半導體封裝包括：一引線框，該引線框具有周邊封裝引線及電連接器；一單個半導體晶粒，該單個半導體晶粒具有一背面電接點及多個正面電接點；一導電夾子(「夾子」)；及一頂部半導體晶粒，該頂部半導體晶粒具有一正面及一背面。該單個半導體晶粒包括兩個或更多個電晶體。該半導體晶粒之正面電接點中的兩者或更多者電耦接至且實體安裝至該引線框之各別電接點。該夾子之一電接觸表面電耦接至且實體安裝至該引線框之一電連接器。該夾子之另一電接觸表面實體安裝至且電耦接至該半導體晶粒之該背面電接點。該頂部半導體晶粒之該背面實體安裝至該導電夾子之又一表面。

Description

電子設備及用於封裝半導體裝置之方法 相關申請案之交叉引用
本申請案主張2017年8月17日申請且發明名稱為「Leadframe and Integrated Circuit Connection Arrangement」之美國非臨時專利申請案第15/680,034號之優先權；該申請案主張2017年2月20日申請且發明名稱為「Backside Contact Integrated Laterally Diffused MOS Apparatus and Methods」之美國臨時申請案第62/461,117號的權益，以上各案皆出於所有目的以引用方式併入。
本發明係一種引線框及積體電路連接配置。
發明背景
半導體功率裝置為通常用作功率電子電路中之開關或整流器的專用裝置。半導體功率裝置藉由其耐受高電壓及大電流以及與高功率操作相關聯之高溫的能力來表徵。舉例而言，開關式調壓器通常包括以同步方式不斷地接通及關斷以調整電壓之兩個功率裝置。該等功率裝置在此情形中需要在接通狀態下吸取系統級電流，在關斷狀態下耐受電源供應器之全電位，且耗散大量之熱。理想之功率裝置能夠在高功率條件下操作，且在接通與關斷狀態之間快速地切換，且展現出低熱阻及接通狀態電阻。
典型半導體功率裝置封裝包括一組離散功率電晶體，其中每一電晶體製作於其自己之各別半導體晶粒上。該等單獨之晶粒與引線框一起囊封於絕緣塑封料中，該引線框為形成於半導體晶粒中之單獨裝置或積體電路提供外部電連接。
高功率半導體應用(諸如功率切換及功率處置)需要半導體晶粒襯墊與封裝引線之間的電連接，該等電連接藉由高載流能力、低電阻及/或低電感表徵。出於此等原因，已作出努力來將由銅、銅合金或鋁組成之導電帶或預形成夾子替代焊線用於半導體封裝內之高功率電連接。然而，導電夾子實體上較大且難以在機械上極精確地定位於晶片上。
在典型半導體功率裝置封裝中，每一離散功率電晶體半導體晶粒藉由單個正面高電流封裝引線、用於閘控之單個正面低電流封裝引線及至封裝底盤之背面連接來電連接至封裝。在每半導體晶粒僅具有單個高電流正面連接之情況下，在此等類型之封裝配置中，導電夾子可容易地用於正面連接，而不會有損可製造性或效能。
可使用側向擴散場效應電晶體(LDFET)，諸如側向擴散金屬氧化物半導體(LDMOS)電晶體，來實施功率裝置。此等類型之電晶體藉由與汲極區之延伸部對應的「側向擴散」區(或低摻雜或輕摻雜汲極(LDD)區)表徵，該延伸部之摻雜程度遠小於核心汲極區且側向地延伸遠離通道。側向擴散區藉由吸收電場的原本會引起源極-汲極擊穿之部分來提高LDFET在關斷狀態下處置較高電壓的能力及藉由防止在汲極-主體界面處建立大電位降來提高LDFET在接通狀態下處置較大電流的能力，該較大電位降原 本會經由熱載流子至裝置主體中之注入而導致裝置降級。
側向功率裝置，諸如LDFET，通常具有正面源極接點及汲極接點，其中每一接點通常具有其自己的高電流、低電阻及/或低電感之正面電連接。對外部(例如封裝)與晶片上電連接之需要隨著整合於同一半導體晶粒上之側向功率裝置的數目而增加。然而，半導體晶粒之正面可用於容納尺寸相對較大之高效能電連接的空間有限。此限制嚴重地限制了積體側向功率裝置電路之電路設計靈活性、效能及可製造性。
發明概要
在一些實施例中，一種積體電路(IC)封裝包括一引線框，該引線框具有周邊封裝引線、一第一電連接器、一第二電連接器及一第三電連接器。該IC封裝另外包括一單個半導體功率晶粒，該單個半導體功率晶粒具有一正面及一背面。該半導體功率晶粒之背面具有一背面電接點，該正面具有一第一正面電接點及一第二正面電接點。該第一正面電接點電耦接至且實體安裝至該第一電連接器，且該第二正面電接點電耦接至且實體安裝至該第二電連接器。該IC封裝亦包括一導電夾子，該導電夾子具有一第一電接觸表面、一第二電接觸表面及一第三電接觸表面。該第二電接觸表面與該第三電接觸表面係在該導電夾子之一部分的相對側上。該第一電接觸表面電耦接至且實體安裝至該第三電連接器，且該第二電接觸表面電耦接至且實體安裝至該單個半導體功率晶粒之該背面電接點。該IC封裝亦包括一控制器晶粒，該控制器晶粒具有一控制器正面、一控制器背面及一控制器背面電接點。 該控制器背面實體安裝至該導電夾子之該第三電接觸表面。
在一些實施例中，一種用於將一半導體裝置封裝於一IC封裝中之方法涉及提供一引線框，該引線框具有周邊封裝引線、一第一電連接器、一第二電連接器及一第三電連接器。形成一單個半導體功率晶粒，該單個半導體功率晶粒具有一正面及一背面。該半導體功率晶粒背面具有一背面電接點，且該正面具有一第一正面電接點及一第二正面電接點。該方法包括將該第一正面電接點電耦接且實體安裝至該第一電連接器及將該第二正面電接點電耦接且實體安裝至該第二電連接器。提供一導電夾子，該導電夾子具有一第一電接觸表面、一第二電接觸表面及一第三電接觸表面。該第二電接觸表面與該第三電接觸表面係在該導電夾子之一部分的相對側上。該方法包括將該第一電接觸表面電耦接且實體安裝至該引線框之該第三電連接器及將該導電夾子之該第二電接觸表面電耦接且實體安裝至該單個半導體功率晶粒之該背面電接點。提供一控制器晶粒，該控制器晶粒具有一控制器正面、一控制器背面及一控制器背面電接點。該控制器晶粒之該控制器背面實體安裝至該導電夾子之該第三電接觸表面。
10、794:開關電路
12:高側FET
14:低側FET
16、716:相位節點
18、20:驅動器輸入端子
22、222、422、522、622:控制器晶粒
23、723:輸入節點
30、230、430、530、630、730:半導體晶粒
32、432、780:高側LDFET
34、434:低側LDFET
35、235、435、735:導電夾子/夾子
40、440、540:基板接點
42:主動層
44、444:介電層
45:SOI基板
46、46'、446、446'、546、546'、646、646'、746、746'、746":源極區
47:介電隔離障壁
48、48'、51'、51、448、448'、451'、448、451:摻雜區
49、49'、449、449':延伸區
50、50'、450、450':LDD區
52、52'、452、452'、552、552'、652、652'、752、752'、752":汲極區
54、54'、454、454'、554、554'、654、654'、756、756'、756":源極接點
56、56'、456、456'、556、556'、656、656'、754、754'、754":汲極接點
60、60'、460、460':主體區
62、62'、462、462':深井區
66、66'、466、466':閘極屏蔽
68、68'、468、468'、568、568'、668、668'、768、768'、768":閘極電極
70、72、70'、72'、470、472、470'、472':介電材料
74:電絕緣材料/絕緣材料
75a-75c、275a-c、475a-d、575a-c、675a-c、775a-d:電連接器
40、81、440、540、640、681、740、781:背面電接點/背面接點
82、282、480、580、680、786:第一正面接點/第一正面電接點
84、284、482、584、684、788:第二正面接點/第二正面電接點
215a-c:安裝媒介
220、320、420、520、620、720:引線框
223a:控制器正面
223b:控制器背面
224:控制器正面電接點
231a:背面
231b:正面
233a、233b:截面切割線
240a-c:電接觸表面
286、484、790:第三正面電接點
291a-h:周邊封裝引線
292a-d:焊線
445:晶圓基板
474:絕緣材料
483、582:電絕緣與導熱材料/電絕緣材料
489:平面外部分
200、300、400、500、600、700:積體電路(IC)封裝
535、635:半夾子
782:第一低側FET
784:第二低側FET
800:方法
805、810、815、820、825、830、835、840、845:步驟
圖1為合併一些實施例的高功率半導體開關之實例的電路圖。
圖2A為根據一些實施例的積體電路封裝之一部分的簡化實例之示意性頂部正投影視圖。
圖2B為根據一些實施例的積體電路封裝之一部分的簡化實例之示意性截面圖。
圖2C為根據一些實施例的積體電路封裝之一部分的簡化實例之示意性截面圖。
圖3為根據一些實施例的積體電路封裝之一部分的簡化實例之示意性截面圖。
圖4為根據一些實施例的積體電路封裝之一部分的簡化實例之示意性截面圖。
圖5為根據一些實施例的積體電路封裝之一部分的簡化實例之示意性截面圖。
圖6為根據一些實施例的積體電路封裝之一部分的簡化實例之示意性截面圖。
圖7A為合併一些實施例的高功率半導體開關之實例的電路圖。
圖7B為根據一些實施例的積體電路封裝之一部分的簡化實例之示意性截面圖。
圖8示出根據一些實施例的用於將半導體裝置封裝於具有引線框之積體電路封裝中的方法之簡化實例。
較佳實施例之詳細說明
在以下描述中，相同之元件符號用於指明相同元件。此外，圖式意欲以圖解方式說明示例性實施例之主要特徵。圖式不意欲繪示實際實施例之每個特徵或所繪示元件之相對尺寸，且未按比例繪製。
本文中描述之一些實例提供一種用於倒裝晶片取向之半導體裝置的有利導電夾子配置以促進積體電路封裝之導 電性及排熱。該積體電路封裝包括一控制器晶粒以及在單個半導體晶粒內之兩個或更多個功率電晶體。本文中包括的積體電路封裝之一些實例包括某些實施例，在該等實施例中，控制器晶粒直接安裝至導電夾子(「夾子」)，使得控制器晶粒之電接點電耦接至夾子(例如，夾子耦接至積體電路封裝之接地節點且控制器晶粒之接地節點電耦接至夾子)。在其他實例中，控制器晶粒直接安裝至夾子，但控制器晶粒與夾子實質上電隔離。
本文中提供的半導體晶粒之實例包括在半導體晶粒上形成之積體側向擴散場效應電晶體(LDFET)電路，該等電路包括與背面電連接接觸之至少一個基板接點，如此減少所需正面電連接之數目。以此方式，此等實例增加可用於容納尺寸相對較大之高效能電連接(例如，引線框之電連接器，諸如能夠傳導高電流之金屬條帶)_的正面空間，藉此增加積體LDFET功率裝置電路之電路設計靈活性、效能及可製造性。在一些實例中，具有基板接點之LDFET與同一電路中之其他LDFET電隔離以藉由防止在連接至基板之LDFET與未連接至基板之LDFET之間形成共同節點來進一步提高電路之效能。
僅為了進行說明，本揭示案在與圖1中所示之示例性高功率半導體開關電路10類似之實施例的情形中描述單半導體晶粒積體LDFET電路的具體實例。可使用相同或類似之教示來製作適合於電力及非電力應用之其他單半導體晶粒積體LDFET電路。
高功率半導體開關電路10包括高側場效應電晶體(FET)12及低側FET 14。高側FET 12之源極在相位節點(phase node)16(V相位)處耦接至低側FET 14之汲極。驅動器輸入端子18、20控制高側FET 12及低側FET 14之占空比以將輸入節點23處之輸入電壓(V輸入)轉換成相位節點16處之特定輸出電壓(V相位)。一般而言，可使用各種半導體材料系統及技術中之任一者(包括矽、鍺及複合半導體技術)來製作FET 12、14。
圖2A示出根據一些實施例的積體電路(IC)封裝200之一部分的簡化實例之頂部正投影視圖，該積體電路封裝包括引線框220、半導體晶粒230、導電夾子235及頂部半導體晶粒(例如，控制器晶粒222)。在一些實施例中，頂部半導體晶粒為以下一者：(i)控制器晶粒、(ii)體半導體晶粒、(iii)微處理器、(iv)微控制器、(v)數位信號處理器或(vi)如此項技術中所知之另一半導體。在本文中描述之示例性實施例中，頂部半導體晶粒為控制器晶粒(控制器晶粒222)。IC封裝200亦包括焊線292a-d。在所示實例中，半導體晶粒230具體實現了整合式負載點(POL)電壓轉換器，且控制器晶粒222經組態以同步POL電壓轉換器之電晶體的各別接通/關斷狀態。在所示之簡化實例中，半導體晶粒230具體實現了圖1中所示之高功率半導體開關電路10的示例性實施方案。然而，該半導體裝置可為如此項技術中所知之另一半導體裝置。
如所示，控制器晶粒222具有控制器正面223a(如圖2B中所示，以及其他側)及控制器正面電接點224。如圖2B中所示，半導體晶粒230具有背面231a以及其他側。類似地，如圖2B中所示，導電夾子(「夾子」)235具有電接觸表面240a以及其他電接觸表面。亦示出截面切割線233a-b，稍後參看圖2B-C來討論該等切割線。
一般而言，引線框220包括電連接器275a-c及周邊封裝引線291a-h。圖2A或本文中之任一圖中所示之電連接器及/或周邊封裝引線的數目係作為簡化實例示出。在一些實施例中，可使用更多或更少電連接器及/或周邊封裝引線。如所示，夾子235的與電接觸表面240a相對之電接觸表面實體安裝至半導體晶粒230之背面231a。控制器晶粒222的與控制器正面223a相對之控制器背面實體安裝至夾子235之電接觸表面240a。半導體晶粒230之正面(與半導體晶粒230之背面231a相對)的各別電接點(示出於圖2B及圖2C中)電耦接至且實體安裝至引線框之電連接器275b-c。
控制器晶粒222之正面電接點中的一或多者電耦接至周邊封裝引線291a-h中之一或多者、引線框220及/或半導體晶粒230以接收或發送信號、命令及/或回饋以用於控制下文描述之半導體晶粒230中的高功率半導體開關電路之電子組件，例如電晶體。舉例而言，控制器正面電接點224中之一接點藉由焊線292a耦接至周邊封裝引線291a。控制器正面電接點224中之另一接點藉由焊線292b耦接至周邊封裝引線291b，另一接點藉由焊線292c耦接至電連接器275c，且又一接點藉由焊線292d耦接至電連接器275b。
導電夾子235之至少一個尺寸大於焊線292a-d。因此，相較於焊線，導電夾子235相對地傳導較大量之熱且具有較大之導電性。藉由有利地將導電夾子235放置於半導體晶粒230與控制器晶粒222(或其他頂部半導體晶粒)之間，自此等晶粒中之任一者或兩者形成之熱可藉由導電夾子235傳導出IC封裝200或傳導至IC封裝200之外周。
傳導性夾子，諸如導電夾子235，通常使用銅(Cu)來預形成(例如，而非沈積)，與半導體晶粒及/或與焊線相比在機械上為大的，與焊線相比具有較大之結構強度，具有比焊線大之導電能力，且具有比焊線大之導熱能力。舉例而言，導電夾子通常具有為約100μm之最小特徵尺寸及一實質截面積。如先前所提及，傳導性夾子235有利地放置於半導體晶粒230與控制器晶粒222之間且耦接至半導體晶粒230及控制器晶粒222以促進熱自彼等部件輸送離開。
圖2B示出根據一些實施例的包括用於半導體裝置之引線框220的簡化示例性積體電路(IC)封裝200之一部分的示意性截面圖。IC封裝200之截面圖為穿過藉由圖2A之切割線233a指示的、圖2A之IC封裝200之一部分截取的截面圖。
圖2B之IC封裝200包括圖2A中介紹之元件以及安裝媒介215a-c、控制器背面223b、半導體晶粒230之正面231b及夾子235之電接觸表面240b-c。
夾子235之電接觸表面240b藉由安裝媒介215b電耦接至且實體安裝至電連接器275a。夾子235之電接觸表面240c藉由安裝媒介215a電耦接至且實體安裝至半導體晶粒230之背面231a。在一些實施例中，安裝媒介215a-c包括晶粒附接黏合劑、燒結銀、焊錫膏、導熱黏合劑或適合於形成實體連接、熱連接及電連接之任何物質。如將描述，在一些實施例中，安裝媒介215c為電絕緣材料。在一些實施例中，半導體晶粒230之正面電接點包括銅柱或焊料凸塊。半導體晶粒230之第一正面電接點282電耦接至且實體安裝至電連接器275b，且第二正面電連接器284電耦 接至且實體安裝至電連接器275c(例如，藉由晶粒附接黏合劑或其他合適之安裝技術)。焊線292a將(例如，圖2A之周邊封裝引線291a-h中之)周邊封裝引線291a電耦接至控制器晶粒222之控制器正面電接點。
在一些實施例中，半導體晶粒230之第一正面電接點282及第二正面電接點284大體上表示半導體晶粒230之多個金屬層中的頂部金屬層。半導體晶粒230為倒置的或按倒裝晶片組態，因此在圖式中，半導體晶粒230之「頂部」/「正面」及「底部」/「背面」分別被示出於底部及頂部。為簡單起見，已省去一些金屬層、連接、焊線或其他特徵。可存在介於中間之金屬層、導電黏合劑、銅柱、焊料凸塊或其他金屬結合結構。在一些實施例中，在半導體晶粒230、引線框220及/或控制器晶粒222之間製作至少五個電連接。參看圖1，此五個電連接包括至輸入節點23(V輸入)之電連接、至相位節點16(V相位)之電連接、至接地節點之電連接、至驅動器輸入端子18(例如，高側FET 12之閘極節點)之電連接及至驅動器輸入端子20(例如，低側FET 14之閘極節點)之電連接。
在一些實施例中，控制器晶粒222之控制器背面223b上之背面電接點藉由安裝媒介215c電耦接至夾子235之電接觸表面240a，該安裝媒介為晶粒附接黏合劑、燒結銀、焊錫膏、導熱黏合劑或適合於形成實體連接、熱連接及電連接之任何物質。在其他實施例中，控制器晶粒222之控制器背面223b上之背面電接點藉由安裝媒介215c實質上與夾子235之電接觸表面240a電隔離，該安裝媒介為晶粒附接黏合劑或適合於形成實體連接及 熱連接之任何物質。在任一實施例中，將藉由半導體晶粒230及控制器晶粒222產生之熱有利地(經由安裝媒介215a,c、夾子235及安裝媒介215b)傳導至IC封裝200之面向外部分(例如，傳導至電連接器275a)。
圖2C示出根據一些實施例的包括用於半導體裝置之引線框220的簡化示例性積體電路(IC)封裝200之一部分的示意性截面圖。圖2C中所示之IC封裝200的截面圖為穿過藉由圖2A之切割線233b指示的、圖2A之IC封裝200之一部分截取的截面圖。
圖2C之IC封裝200包括圖2A-B中介紹之元件以及半導體晶粒230之第三正面電接點286。在一些實施例中，第三正面電接點286電耦接至半導體晶粒230之電晶體的閘極接點。如所示，第三正面電接點286電耦接至且實體安裝至周邊封裝引線291b，該周邊封裝引線在半導體晶粒230下面延伸。儘管第三正面接點286被示出為實體安裝至周邊封裝引線291b，但在一些實施例中，第三正面電接點286電耦接至周邊封裝引線291b(例如，藉由焊線)但並未實體安裝至周邊封裝引線291b。
在所示實施例中，焊線292b將周邊封裝引線291b電耦接至控制器晶粒222之控制器正面電接點且藉此將第三正面接點286電耦接至控制器晶粒222之接點。
在一些實施例中，第三正面電接點286大體上表示半導體晶粒230之多個金屬層中的頂部金屬層。為簡單起見，已省去一些金屬層、連接、焊線或其他特徵。可存在介於中間之金屬層、導電黏合劑、銅柱、焊料凸塊或其他金屬結合結構。
圖3示出根據一些實施例的包括引線框320之積體 電路(IC)封裝300的一部分之簡化示意性截面側視圖。所示之引線框320之部分大體上包括電連接75a-c。為簡單起見，已省去引線框320之其他部分。舉例而言，與圖2A之周邊封裝引線291a-h類似的周邊封裝引線可為引線框320之部分。IC封裝300包括半導體晶粒30，該半導體晶粒具有第一正面電接點82及第二正面電接點84。IC封裝300亦包括導電夾子(「夾子」)35及具有背面電接點81之控制器晶粒22。IC封裝300之多個部分類似於參看圖2A-C討論的IC封裝200之多個部分。舉例而言：夾子35類似於夾子235，且電連接器75a-c類似於電連接器275a-c。
在所示之簡化示例性實施例中，此等半導體晶粒30具體實現圖1之高功率半導體開關電路10。在此實例中，LDFET 32實現開關電路10之高側FET 12，且LDFET 34實現開關電路10之低側FET 14。在一個示例性組態中，高側LDFET 32之第一正面接點82對應於開關電路10之輸入節點23，第二正面接點84對應於開關電路10之相位節點16，且基板接點40對應於開關電路10之接地節點。在一些實施例中，控制器晶粒22之正面電接點(例如，類似於圖2A中所示之控制器正面接點224)經由打線結合及/或經由引線框320電耦接至LDFET 32及/或LDFET 34之閘極節點。此組態使控制器晶粒22能夠控制高側LDFET 32及低側LDFET 34之接通/關斷狀態。在一些實施例中，半導體晶粒30包括p型高側電晶體及n型低側電晶體。在一些實施例中，同時地切換高側電晶體與低側電晶體，用兩個閘極接點分別切換或使用單個閘極接點一起切換(例如，其中高側電晶體之閘極及低側電晶體之閘極電耦接至單個閘極接點)。
在上文描述及圖3中示出之高功率半導體開關電路10的示例性實施方案中，高側LDFET 32之汲極接點56連接至輸入節點23，高側LDFET 32之源極接點54與低側LDFET 34之汲極接點56'均連接至相位節點16，且低側LDFET 34之源極接點54'連接至接地節點。如上文所提及，其他節點連接配置為可能的。舉例而言，此等其他連接配置包括第一LDFET與第二LDFET之間的任何連接配置，該等連接配置包括：(i)電連接至第一LDFET之源極及第二LDFET之汲極的共同節點，(ii)第一LDFET之汲極、第二LDFET之源極及該共同節點中之至少一者電連接至半導體基板，及(iii)連接至第一LDFET之汲極、第二LDFET之源極及該共同節點中未電連接至半導體基板的至少兩者的至少兩個正面接點。
在主動層42中實現高側LDFET 32及低側LDFET 34。主動層42可為半導體晶圓之體的摻雜部分、在半導體晶圓之較大摻雜部分中形成之區域化井、絕緣體上半導體(SOI)晶圓之主動層及在SOI晶圓中形成之區域化井中的任一者。在所示實例中，主動層42為在SOI基板45上之內埋介電層44上面形成之薄膜。在所示實例中，介電隔離障壁47在高側LDFET 32與低側LDFET 34之間自主動層42之頂部至內埋介電層44延伸。在一些實例中，使用淺溝槽隔離(STI)製程來形成介電隔離障壁47。
主動層42之高側LDFET 32包括形成於摻雜區48中之源極區46、形成於摻雜區51中的輕摻雜汲極(LDD)區50與較重摻雜延伸區49、及汲極區52。源極區46、摻雜區48、LDD區50、延伸區49及汲極區52可包括藉由(例如)將雜質植入於主動層42中 而形成之摻雜半導體材料。每一區46-52之摻雜半導體材料具有類似之傳導性類型(例如，n型或p型)。因此，每一區46-52可由相同摻雜劑種類形成，諸如經由植入一種摻雜劑原子。LDD區50具有比汲極區52低之摻雜劑濃度且亦可具有比源極區46低之摻雜劑濃度。LDD區50向LDFET提供其作為功率裝置就其耐受大電壓且在吸收大電流時不會降級之能力而言的優良效能。LDD區50之存在向LDFET提供其具有不對稱源極區及汲極區之特性。在一些方法中，LDD區50自汲極區52側向地延伸之長度大體上為摻雜區48自源極區46延伸之長度的至少兩倍。
主動層42之高側LDFET部分亦包括主體區60及深井區62，該兩個區具有與源極區、摻雜區、LDD區、延伸區及汲極區46-52之傳導性類型相反的傳導性類型。深井區62在源極區46及主體區60中形成通道之部分下面側向地延伸。深井區62增強高側LDFET 32耐受大電壓之能力且用於自主體區60移除不想要之電荷載流子以防止在高側LDFET 32之接通狀態期間寄生雙極型接面電晶體啟動。
在主動層42上方，高側LDFET 32包括一閘極結構，該閘極結構包括一閘極屏蔽66及一閘極電極68。閘極電極68分別藉由介電材料70、72與主動層42及閘極屏蔽66電絕緣。源極區46電耦接至源極接點54，該源極接點連接至第二正面電接點(相位)84。汲極區52電耦接至汲極接點56，該汲極接點連接至第一正面電接點(輸入)82。汲極區52可為高摻雜汲極區且可在汲極接點56與LDD區50之間形成導電路徑。電絕緣材料74(例如，層間介電材料)將主動層42上方之電組件電隔離。一般而言，電絕緣材 料74與介電材料70、72可為相同或類似之材料。另外，在某些方法中，絕緣材料74與介電材料70、72之組合可被概念化為成品裝置中之單個絕緣層，不管該等材料何時及如何形成。
回應於對閘極電極68施加電壓(例如，藉由控制器晶粒22)而在源極接點54與汲極接點56之間形成傳導路徑。源極接點54與汲極接點56之間的傳導路徑包括在對閘極電極68施加之前述電壓的影響下在主體區60中選擇性地形成之通道。在形成通道時，據稱該電晶體為接通的。在不形成通道時且源極接點54與汲極接點56之間不存在傳導路徑時，據稱該電晶體為關斷的。在此情況中不存在傳導路徑，因為源極區46及汲極區50、52具有與主體區60相反之傳導性類型使得在其界面處形成二極體接面。
閘極屏蔽66與源極接點54歐姆接觸。閘極屏蔽66為使高側FET 32更適合於高功率應用之另一特徵。藉由將閘極屏蔽66偏置向給定電壓，屏蔽汲極接點56上之高功率信號使之不會對閘極區具有可感知到之影響。雖然閘極屏蔽66被示出為歐姆耦接至源極接點54，但亦可對閘極屏蔽66獨立地偏置。在一些實例中，閘極屏蔽66及源極接點54可在兩個不同步驟中形成且可包括兩種不同材料。然而，在這種情況中，在大多數情形中此類特徵對裝置之操作為不重要的，因為閘極屏蔽66及源極接點54為由高傳導性材料製成之一個連續區，該區具有自上方之電絕緣材料74一直至主動層42之表面的無中斷歐姆接點。因而，閘極屏蔽66與源極接點54之組合可被概念化為單個源極接點。
一般而言，源極接點54及汲極接點56實現了自其他電路至高側LDFET 32之電連接，該等其他電路可能會或可能不會 與該LDFET整合於同一積體電路上。源極區46可經由在源極區46之表面上形成的矽化物層電耦接至源極接點54。更一般而言，可使用在基板之該兩個區之間形成歐姆或非整流接觸之任何方法來將源極區46耦接至源極接點54。汲極接點56與汲極區52之間的連接可包括上文參考源極接點54及源極區46描述之任何變型。源極接點54及汲極接點56可包括金屬、金屬合金、金屬矽化物或導電半導體材料(諸如摻雜多晶矽)。示例性金屬、金屬合金及金屬矽化物可各自包括銅、鎢、鉬及鋁。
在圖3中所示之實例中，主動層42之低側LDFET部分34的一些元件以與主動層42之高側LDFET部分32的對應元件類似之方式起作用。就此而言，低側LDFET 34的功能類似之元件將被標有後面加上撇號的、高側LDFET之對應元件的元件符號。舉例而言，與高側LDFET 32的功能類似之汲極區52對應的低側LDFET 34之汲極區被標有元件符號52'。因此，低側LDFET 34包括以下元件：源極區46'、摻雜區48'、在摻雜區51'中形成之LDD區50'與較重摻雜延伸區49'、汲極區52'、源極接點54'、汲極接點56'、主體區60'、深井區62'、閘極屏蔽66'、閘極電極68'及介電材料70'、72'。
在此實例中，低側LDFET 34之源極接點54'不僅自主動層42上方、穿過源極區46'及摻雜區48'延伸至深井區62'，且該源極接點亦延伸穿過深井區62'及內埋介電層44且延伸至基板45中。以此方式，低側LDFET 34之源極接點54'提供至基板45且藉此至基板接點40之源極向下電連接，該基板接點對應於用於高功率半導體開關電路10之接地節點。
第二正面電接點84(相位節點)將高側LDFET之源極接點54與低側LDFET之汲極接點56'電互連且藉此形成用於高側LDFET 32之源極區46及低側LDFET 34之汲極區52'的共同節點。請注意，內埋介電層44及介電隔離障壁47將高側LDFET 32與基板45電隔離以防止在功率開關電路10之操作期間與低側LDFET 34之源極接點54'形成共同節點。
半導體晶粒30安裝於IC封裝300之引線框320的多個部分之上及之內。如所示，半導體晶粒30之第一正面電接點82電耦接至且實體安裝至電連接器75b，第二正面電接點84電耦接至且實體安裝至電連接器75c，夾子35電耦接至且實體安裝至半導體晶粒30之背面電接點40，且夾子35電耦接至且實體安裝至電連接器75a。製作與圖2A-C中所示之連接類似的、控制器晶粒22與半導體晶粒之間的額外電連接，但為了簡單起見在圖3中將該等額外電連接省去。
控制器晶粒22之控制器背面電接點81電耦接至且實體安裝至夾子35。如上文所提及，夾子35有利地放置於半導體晶粒30與控制器晶粒22之間且耦接至半導體晶粒30及控制器晶粒22以促進熱自彼等部件輸送離開。圖3中所示之金屬層(例如，第一正面電接點82及第二正面電接點84)大體上表示在需要時為連接進行選路之多個金屬層，包括用於半導體晶粒襯墊之頂部金屬層及在半導體晶粒襯墊與絕緣材料(例如，74)或主動層(例如，42)之間的額外金屬層。為簡單起見，已省去一些金屬層、連接、焊線或其他特徵。可存在介於中間之金屬層、導電黏合劑、銅柱、焊料凸塊或其他金屬結合結構。為簡單起見，該簡化示意性截面 側視圖僅示出單個電晶體「指狀物」。在一些實施例中，多個電晶體指狀物並聯連接以在所具體實現之電路的應用要求時增加所具體實現之電路的功率處置能力及減少總電阻。半導體晶粒30為倒置的或按倒裝晶片組態，因此在圖式中，半導體晶粒30之「頂部」/「正面」及「底部」/「背面」分別被示出於底部及頂部。
圖4示出根據一些實施例的包括引線框420之積體電路(IC)封裝400的一部分之簡化示意性截面圖。所示之引線框420之部分大體上包括電連接器475a-d。為簡單起見，已省去引線框420之其他部分。舉例而言，與周邊封裝引線291a-h類似之周邊封裝引線可為引線框420之部分。
IC封裝400包括半導體晶粒430(類似於圖3之半導體晶粒30)，該半導體晶粒具有第一正面電接點480、第二正面電接點482及第三正面電接點484。IC封裝400亦包括導電夾子(「夾子」)435、控制器晶粒422(類似於圖3之半導體晶粒22)及電絕緣與導熱材料483。IC封裝400之多個部分類似於參看圖2A-C討論的IC封裝200之多個部分。舉例而言：夾子435類似於夾子235，且電連接器475a-d類似於電連接器275a-c。
在所示之示例性實施例中，半導體晶粒430具體實現圖1之高功率半導體開關電路10。在一個示例性組態中，高側LDFET 432之第一正面電接點480對應於開關電路10之輸入節點23(見圖1)，基板接點440對應於開關電路10之相位節點16，且第三正面電接點484對應於開關電路10之接地節點。
圖3中所示的半導體晶粒30之高側LDFET 32及引線框320的一些元件以與圖4中所示之高側LDFET 432及引線框 420的對應元件類似之方式起作用。就此而言，高側LDFET 432的功能類似之元件被標有前面加上了數字「4」的、圖3之高側LDFET的對應元件之元件符號。舉例而言，與圖3之高側LDFET 32的功能類似之汲極區52對應的圖4之高側LDFET 432的汲極區被標有元件符號「452」。另外，圖4之電連接器475a類似於圖3之電連接器75a。
高側LDFET 432包括以下元件：源極區446、摻雜區448、在摻雜區451中形成之LDD區450與較重摻雜延伸區449、汲極區452、源極接點454、汲極接點456、主體區460、深井區462、閘極屏蔽466、閘極電極468、介電材料470、472及絕緣材料474。另外，低側LDFET 434的功能類似之元件被標有後面加上撇號的、高側LDFET 432之對應元件的元件符號。因此，低側LDFET 434包括以下元件：源極區446'、摻雜區448'、在摻雜區451'中形成之LDD區450'與較重摻雜延伸區449'、汲極區452'、源極接點454'、汲極接點456'、主體區460'、深井區462'、閘極屏蔽466'、閘極電極468'及介電材料470'、472'。
在所示之示例性實施例中，低側LDFET 434之汲極接點456'與高側LDFET 432之源極接點454藉由第二正面電接點482(例如，導電體)電連接，該第二正面電接點包括平面外部分489。另外，高側LDFET 432之源極接點454不僅自主動層上方、穿過源極區446及摻雜區448延伸至深井區462，且該源極接點亦延伸穿過深井區462及內埋介電層444且延伸至晶圓基板445中。以此方式，高側LDFET 432之源極接點454提供至基板445且藉此至用於高功率半導體開關電路10之相位節點16的基板接點440之 源極向下電連接。請注意，內埋介電層444及介電隔離障壁447將低側LDFET 434與基板445電隔離以防止在功率開關電路之操作期間與高側LDFET 432之源極接點454形成共同節點。
半導體晶粒430安裝於引線框420之一部分上。如所示，第一正面電接點480電耦接至且實體安裝至引線框420之電連接器475d，第二正面電接點482電耦接至且實體安裝至電連接器475c，且第三正面電接點484電耦接至且實體安裝至電連接器475b。夾子435電耦接至且實體安裝至半導體晶粒430之背面電接點440且電耦接至且實體安裝至電連接器475a。另外，控制器晶粒422實體安裝至夾子435，但藉由電絕緣材料483與夾子435實質上電隔離。亦即，在所示實施例中，控制器晶粒422之背面電接點未電耦接至夾子435。製作與圖2A-C中所示之連接類似的、控制器晶粒422與半導體晶粒之間的額外電連接，但為了簡單起見在圖4中將該等額外電連接省去。替代地，在其中基板接點440對應於開關電路之相位節點16且電耦接至夾子435的一些實施例中，電連接器475c為可選的，或不包括電連接器475c。
如上文所提及，夾子435有利地放置於半導體晶粒430與控制器晶粒422之間且耦接至半導體晶粒430及控制器晶粒422以促進熱自彼等部件輸送離開。圖4中所示之金屬層(例如，正面電接點480、482及484)大體上表示在需要時為連接進行選路之多個金屬層，包括用於半導體晶粒襯墊之頂部金屬層及在半導體晶粒襯墊與絕緣材料(例如，474)或主動層之間的額外金屬層。為簡單起見，已省去一些金屬層、連接、焊線或其他特徵。可存在介於中間之金屬層、導電黏合劑、銅柱、焊料凸塊或其他金屬結 合結構。半導體晶粒430為倒置的或按倒裝晶片組態，因此在圖式中，半導體晶粒430之「頂部」/「正面」及「底部」/「背面」分別被示出於底部及頂部。
圖5示出根據一些實施例的包括引線框520之積體電路(IC)封裝500的一部分之簡化示意性截面側視圖。所示之引線框520之部分大體上包括電連接器575a-c。為簡單起見，已省去引線框520之其他部分。舉例而言，與圖2A之周邊封裝引線291a-h類似的周邊封裝引線可為引線框520之部分。IC封裝500亦包括半導體晶粒530，該半導體晶粒具有第一正面電接點580及第二正面電接點584、導電夾子(「夾子」)535、控制器晶粒522及電絕緣與導熱材料582。IC封裝500之多個部分類似於參看圖2A-C討論的IC封裝200之多個部分。舉例而言：夾子535類似於夾子235，且電連接器575a-c類似於電連接器275a-c。
在所示之示例性實施例中，半導體晶粒530具體實現圖1之高功率半導體開關電路10。在一個實例中，高側LDFET之第一正面接點580連接至開關電路10之輸入節點(V輸入)(見圖1)，基板接點540連接至開關電路10之相位節點16(V相位)，且第二正面接點584連接至開關電路10之接地節點(GND)。基板接點540對應於開關電路10之相位節點。
在此實例中，圖3中所示的半導體晶粒30之高側LDFET 32的一些元件以與圖5中所示之高側LDFET的對應元件類似之方式起作用。就此而言，圖5之高側LDFET的功能類似之元件被標有前面加上了數字「5」的、圖3之高側LDFET的對應元件之元件符號。舉例而言，與圖3之高側LDFET 32的功能類似之汲 極區52對應的圖5之高側LDFET的汲極區被標有元件符號「552」。類似地，圖5之引線框520的功能類似之元件被標有前面加上了數字「5」的、圖3之引線框320的對應元件之元件符號。因此，高側LDFET包括以下元件：源極區546、汲極區552、源極接點554、汲極接點556及閘極電極568。另外，低側LDFET的功能類似之元件被標有後面加上撇號的、高側LDFET之對應元件的元件符號。因此，圖5中所示之低側LDFET包括以下元件：源極區546'、汲極區552'、源極接點554'、汲極接點556'及閘極電極568'。
在此實例中，使用支持源極與汲極基板接點之形成的製程，將高側源極接點554與低側汲極接點556'製作為穿過內埋介電層544延伸至基板545的基板接點。因此，替代如在圖4中所示之實例中使用正面接點將高側源極區546連接至低側汲極區552'，高功率半導體開關電路10之此實施方案使用兩個基板接點554及556'將高側源極區546及低側汲極區552'分別連接至相位節點(V相位)。以此方式，將正面連接之數目自三個減少至兩個。
如所示，第一正面電接點580電耦接至且實體安裝至引線框520之電連接器575c，第二正面電接點584電耦接至且實體安裝至電接點575b，夾子535電耦接至且實體安裝至半導體晶粒530之背面電接點540，且夾子535電耦接至且實體安裝至電連接器575a。另外，控制器晶粒522實體安裝至夾子535，但藉由電絕緣材料582與夾子535實質上電隔離。然而，可存在控制器晶粒522與半導體晶粒530之間(例如，至閘極電極568/568')之其他電連接，在圖5中為簡單起見省去該等電連接。半導體晶粒530為倒置的或按倒裝晶片組態，因此在圖式中，半導體晶粒530之「頂部」 /「正面」及「底部/背面」分別被示出於底部及頂部。
如上文所提及，夾子535有利地放置於半導體晶粒530與控制器晶粒522之間且耦接至半導體晶粒530及控制器晶粒522以促進熱自彼等部件輸送離開。圖5中所示之金屬層(例如，第一正面接點580及第二正面電接點584)大體上表示在需要時為連接進行選路之多個金屬層，如上文在其他實施例中針對金屬層所提及的，包括用於半導體晶粒襯墊之頂部金屬層及在半導體晶粒襯墊與絕緣材料或主動層之間的額外金屬層。為簡單起見，已省去一些金屬層、連接、焊線或其他特徵。可存在介於中間之金屬層、導電黏合劑、銅柱或其他金屬結合結構。
圖6示出根據一些實施例的包括引線框620之積體電路(IC)封裝600的一部分之簡化示意性截面圖。所示之引線框620之部分大體上包括電連接器675a-c。為簡單起見，已省去引線框620之其他部分。舉例而言，與圖2A之周邊封裝引線291a-h類似的周邊封裝引線可為引線框620之部分。IC封裝600亦包括半導體晶粒630，該半導體晶粒具有第一正面電接點680及第二正面電接點684。IC封裝600亦包括導電夾子(「夾子」)635及控制器晶粒622，該控制器晶粒具有背面電接點681。IC封裝600之多個部分類似於參看圖2A-C討論的IC封裝200之多個部分。舉例而言：夾子635類似於夾子235，且電連接器675a-d類似於電連接器275a-c。
在所示之示例性實施例中，半導體晶粒630具體實現圖1之高功率半導體開關電路10。在一個示例性組態中，高側LDFET之第一正面接點680連接至開關電路10之輸入節點(V輸入)(見圖1)，第二正面接點684連接至開關電路10之相位節點(V相位)， 且接觸基板645之源極接點654'藉由夾子635經由背面接點640連接至開關電路10之接地節點(GND)。
圖3中所示的半導體晶粒30之高側LDFET 32的一些元件以與圖6中所示之高側LDFET的對應元件類似之方式起作用。就此而言，圖6之高側LDFET的功能類似之元件被標有前面加上了數字「6」的、圖3之高側LDFET的對應元件之元件符號。舉例而言，與圖3之高側LDFET 32的功能類似之汲極區52對應的圖6之高側LDFET的汲極區被標有元件符號「652」。因此，高側LDFET包括以下元件：源極區646、汲極區652、源極接點654、汲極接點656及閘極電極668。另外，低側LDFET的功能類似之元件被標有後面加上撇號的、高側LDFET之對應元件的元件符號。因此，圖6中所示之低側LDFET包括以下元件：源極區646'、汲極區652'、源極接點654'、汲極接點656'及閘極電極668'。
如所示，第一正面電接點680電耦接至且實體安裝至電連接器675b，第二正面電接點684電耦接至且實體安裝至電接點675c，夾子635電耦接至且實體安裝至半導體晶粒630之背面電接點640，且夾子635電耦接至且實體安裝至電連接器675a。另外，控制器晶粒622實體安裝至夾子635且藉由控制器背面電接點681電耦接至夾子635。
如上文所提及，夾子635有利地放置於半導體晶粒630與控制器晶粒622之間且耦接至半導體晶粒630及控制器晶粒622以促進熱自彼等部件輸送離開。圖6中所示之金屬層(例如，接點680及684)大體上表示在需要時為連接進行選路之多個金屬層，如上文在其他實施例中針對金屬層所提及的，包括用於半導 體晶粒襯墊之頂部金屬層及在半導體晶粒襯墊與絕緣材料或主動層之間的額外金屬層。為簡單起見，已省去一些金屬層、連接、焊線或其他特徵。可存在介於中間之金屬層、導電黏合劑、銅柱、焊料凸塊或其他金屬結合結構。半導體晶粒630為倒置的或按倒裝晶片組態，因此在圖式中，半導體晶粒630之「頂部」/「正面」及「底部」/「背面」分別被示出於底部及頂部。
圖7A示出高功率半導體開關電路794之實例，該高功率半導體開關電路包括高側場效應電晶體(FET)780、第一低側FET 782及第二低側FET 784。高側FET 780之源極在相位節點716處耦接至第一低側FET 782之汲極且耦接至第二低側FET 784之汲極。
圖7B示出根據一些實施例的包括引線框720之積體電路(IC)封裝700的一部分之簡化示意性截面側視圖，該引線框具體實現了圖7A之高功率開關電路794。所示之引線框720之部分大體上包括電連接器775a-d。為簡單起見，已省去引線框720之其他部分。舉例而言，與周邊封裝引線291a-h類似之周邊封裝引線可為引線框720之部分。IC封裝700亦包括半導體晶粒730，該半導體晶粒具有第一正面電接點786、第二正面電接點788及第三正面電接點790。IC封裝700亦包括導電夾子(「夾子」)735及控制器晶粒722，該控制器晶粒具有背面電接點781。IC封裝700之多個部分類似於參看圖2A-C討論的IC封裝200之多個部分。舉例而言：夾子735類似於夾子235，且電連接器775a-d類似於電連接器275a-c。
在所示之示例性實施例中，半導體晶粒730具體實 現高功率半導體開關電路794，該高功率半導體開關電路包括一個高側LDFET 780及兩個低側LDFET 782及784。在一個示例性組態中，第一正面接點786將高側LDFET 780之源極接點756及低側LDFET 784之汲極接點754"連接至開關電路794之相位節點716(V相位)(見圖7A)，第二正面接點788將高側LDFET 780之汲極接點754連接至開關電路794之輸入節點723(V輸入)，且第三正面接點790將低側LDFET 782之汲極接點754'連接至相位節點(V相位)。在一些實施例中，第一正面接點786及第三正面接點790在圖7B中所示之截面圖之平面外電耦接至彼此。
圖3中所示的半導體晶粒30之高側LDFET 32的一些元件以與圖7B中所示之高側LDFET 780的對應元件類似之方式起作用。就此而言，圖7B之高側LDFET 780的功能類似之元件被標有前面加上了數字「7」的、圖3之高側LDFET的對應元件之元件符號。舉例而言，與圖3之高側LDFET 32的功能類似之汲極區52對應的圖7B之高側LDFET 780的汲極區被標有元件符號「752」。因此，高側LDFET 780包括以下元件：源極區746、汲極區752、汲極接點754、源極接點756及閘極電極768。另外，低側LDFET 782的功能類似之元件被標有後面加上撇號的、高側LDFET之對應元件的元件符號。因此，圖7B中所示之低側LDFET 782包括以下元件：源極區746'、汲極區752'、汲極接點754'、源極接點756'及閘極電極768'。類似地，低側LDFET 784的功能類似之元件被標有後面加上雙撇號的、高側LDFET之對應元件的元件符號。因此，圖7B中所示之低側LDFET 784包括以下元件：源極區746"、汲極區752"、汲極接點754"、源極接點756"及閘極電極 768"。
在所示之示例性實施例中，高側源極區746與相鄰之低側汲極區752"藉由第一正面接點786及高側源極接點756及低側汲極接點754"互連。藉由將基板接點756'及756"用於分別將源極區746'及746"連接至接地節點(GND)，較大金屬區域可用於低側汲極區752'之正面相位節點接點790以使得能夠減小平面外電阻。
如所示，第一正面電接點786電耦接至且實體安裝至電連接器775d，第二正面電接點788電耦接至且實體安裝至電連接器775c，第三正面電接點790電耦接至且實體安裝至電連接器775d，夾子735電耦接至且實體安裝至半導體晶粒730之背面電接點740，且夾子735電耦接至且實體安裝至電連接器775a。替代地，在其中第一正面接點786及第三正面接點790在圖7B中所示之截面圖的平面外電耦接至彼此的一些實施例中，電連接器775b或775d中之一者為可選的或不包括電連接器775b或775d中之一者。另外，控制器晶粒722實體安裝至夾子735且藉由控制器背面電接點781電耦接至夾子735。
如上文所提及，夾子735有利地放置於半導體晶粒730與控制器晶粒722之間且耦接至半導體晶粒730及控制器晶粒722以促進熱自彼等部件輸送離開。圖7B中所示之金屬層(例如，接點786、788、790)大體上表示在需要時為連接進行選路之多個金屬層，如上文在其他實施例中針對金屬層所提及的，包括用於半導體晶粒襯墊之頂部金屬層及在半導體晶粒襯墊與絕緣材料或主動層之間的額外金屬層。為簡單起見，已省去一些金屬層、連接、焊線或其他特徵。可存在介於中間之金屬層、導電黏合劑、 銅柱或其他金屬結合結構。半導體晶粒730為倒置的或按倒裝晶片組態，因此在圖式中，半導體晶粒730之「頂部」/「正面」及「底部」/「背面」分別被示出於底部及頂部。
儘管示出了有兩個及三個LDFET整合至單個功率半導體晶粒中的實例，但可用於實現整合式LDFET裝置的構成LDFET之結構及配置的眾多變型為可能的。另外，此等單獨LDFET結構中之兩者或更多者可彼此組合以產生額外整合式LDFET電路實施例。任何數目之電晶體及/或電晶體指狀物可整體地整合於半導體晶粒730中。舉例而言，多個功率區塊(各自具有其自己之獨立高側及低側電晶體)可共存於半導體晶粒730內，每一電晶體共用共同背面電位(接地或V輸入)。
圖8示出根據一些實施例的用於將倒裝晶片取向之半導體裝置封裝於具有引線框之積體電路(IC)封裝中的方法800之簡化實例。在步驟805中，提供IC封裝之引線框。在一些實施例中，類似於圖2A-C中所示之IC封裝200的引線框220之示例性部分，該引線框具有多個電連接器及周邊封裝引線。一般而言，該等電連接器為各別金屬條帶(例如，如圖2A中所示之275a-c)且至少一個尺寸大於周邊封裝引線。在一些實施例中，該電連接器為具有一厚度、一寬度及一長度之金屬條帶，其中該電連接器之長度實質上長於該電連接器之寬度。
在步驟810中，形成或提供單個半導體晶粒。一般而言，該半導體晶粒具有正面及背面，該正面具有一或多個正面電接點，且該背面具有一背面電接點。在一些實施例中，該單個半導體晶粒為根據本文中尤其係關於圖3至圖7B討論之晶粒的晶 粒。在一些實施例中，該單個半導體晶粒為一功率裝置且包括兩個或更多個LDFET電晶體。在其他實施例中，該單個半導體晶粒包括並非LDFET電晶體之兩個或更多個電晶體。
在步驟815中，將該單個半導體晶粒倒置且按倒裝晶片組態實體安裝至IC封裝之引線框。該單個半導體晶粒之一或多個正面電接點電耦接至且實體安裝至該引線框之各別電連接器。在一些實施例中，該單個半導體晶粒之正面電接點中的一或多者電耦接至且實體安裝至該引線框之各別周邊封裝引線。舉例而言，在一些實施例中，該單個半導體晶粒包括兩個或更多個LDFET，其各自具有耦接至該單個半導體晶粒之各別正面電接點的各別閘極節點。耦接至該等各別閘極節點之正面電接點可電耦接至各別周邊封裝引線且在一些實施例中可實體安裝至各別封裝引線。
在步驟820中，提供導電且導熱之夾子。在一些實施例中，該導電夾子由亦促進熱輸送之導電材料(諸如銅)製成。在一些實施例中，該導電夾子之最小特徵尺寸為約100微米。
在步驟825中，將導電夾子之表面電耦接至且實體安裝至該引線框之電接點(例如，電連接器)。在一些實施例中，該電接點為引線框底盤。在其他實施例中，該電接點為一金屬條帶，該條帶具有一厚度、一寬度及一長度，其中該長度實質上長於該寬度。在一些實施例中，該電接點亦為散熱片。在步驟830中，將該導電夾子之另一表面電耦接至且實體安裝至該單個半導體晶粒之背面電接點(例如，使用晶粒附接黏合劑、焊錫膏、燒結銀、導熱黏合劑或另一種適當技術)。
在步驟835中，形成或提供一控制器晶粒，該控制器晶粒具有一正面及一背面。在一些實施例中，該控制器晶粒具有背面電接點(例如，接地接點)。在其他實施例中，該控制器晶粒不具有背面電接點。根據一些實施例，該控制器晶粒電耦接至該半導體晶粒且包括經組態以控制該半導體晶粒內之電晶體的狀態(例如，接通/關斷、導通/非導通)且使該等電晶體之狀態同步的電路。
在步驟840中，將控制器晶粒實體安裝至導電夾子之一表面(例如，使用晶粒附接黏合劑、焊錫膏、燒結銀、導熱黏合劑或另一種適當技術)。該控制器晶粒之背面可安裝至該導電夾子之一表面，該表面與該導電夾子的安裝至該單個半導體晶粒之背面電接點的表面相對。然而，其他安裝組態為可能的。舉例而言，該控制器晶粒之正面可安裝至該導電夾子之一表面。在一些實施例中，該控制器晶粒安裝至該導電夾子之一表面，使得控制器晶粒與導電夾子實質上電隔離。在其他實施例中，該控制器晶粒安裝至該導電夾子之一表面，使得控制器晶粒電耦接至導電夾子。
在步驟845中，製作IC封裝內之其他電連接(例如，使用焊線)。此等電連接包括控制器晶粒與單個半導體晶粒之間的電連接、控制器晶粒與周邊封裝引線之間的電連接、控制器晶粒與該引線框之電連接器之間的電連接、單個半導體晶粒與該等周邊封裝引線中之一或多者之間的電連接及控制器晶粒及/或單個半導體晶粒與該引線框之間的其他電連接。方法800中之其他步驟可完成IC封裝。
已詳細地參考所揭示之發明的實施例，該等實施例之一或多個實例已示出於附圖中。每一實例被提供作為對當前技術之闡釋而非作為對當前技術之限制。實際上，雖然已關於本發明之具體實施例來詳細地描述了本說明書，但將瞭解，熟習此項技術者在理解了前文之後可容易地設想出此等實施例之更改、變型及等效物。舉例而言，被說明或描述為一個實施例之部分的特徵可用於另一個實施例以得到又一個實施例。因此，希望本主題涵蓋屬於所附申請專利範圍及其等效物之範疇內的所有此類修改及變型。在不脫離本發明之範疇的情況下，可藉由一般熟習此項技術者實行對本發明之此等及其他修改及變型，在所附申請專利範圍中更具體地陳述了本發明之範疇。此外，一般熟習此項技術者將瞭解，以上描述僅為舉例，且不希望限制本發明。
200:積體電路(IC)封裝
220:引線框
222:控制器晶粒
223a:控制器正面
224:控制器正面電接點
230:半導體晶粒
231a:背面
233a、233b:截面切割線
235:導電夾子/夾子
240a:電接觸表面
275a-c:電連接器
291a-h:周邊封裝引線
292a-d:焊線

Claims (23)

  1. 一種電子設備，該電子設備包括：一引線框，該引線框具有周邊封裝引線、一第一電連接器、一第二電連接器及一第三電連接器；一單個半導體晶粒，該單個半導體晶粒具有一正面及一背面，該背面具有一背面電接點，該正面具有一第一正面電接點及一第二正面電接點，該第一正面電接點電耦接至且實體安裝至該第一電連接器，且該第二正面電接點電耦接至且實體安裝至該第二電連接器；一導電夾子，該導電夾子具有一第一電接觸表面、一第二電接觸表面及一第三電接觸表面，該第二電接觸表面與該第三電接觸表面係在該導電夾子之一部分的相對側上，該第一電接觸表面電耦接至且實體安裝至該第三電連接器，且該第二電接觸表面電耦接至且實體安裝至該單個半導體晶粒之該背面電接點；及一頂部半導體晶粒，該頂部半導體晶粒具有一頂部半導體正面、一頂部半導體背面及一頂部半導體背面電接點，該頂部半導體背面實體安裝至該導電夾子之該第三電接觸表面；其中：該單個半導體晶粒包括兩個或更多個電晶體及一第三正面電接點，該第一正面電接點電耦接至該等兩個或更多個電晶體中之至少一者，該第二正面電接點電耦接至該等兩個或更多個電晶體中之至少一者，該第三正面電接點電耦接至該等兩個或更多個電晶體中之至少一者，且該背面電接點電耦接至該等兩個或更多個電晶體中之至少一者。
  2. 如申請專利範圍第1項之電子設備，其中：該頂部半導體晶粒為一控制器晶粒。
  3. 如申請專利範圍第1項之電子設備，其中：該單個半導體晶粒為一功率半導體晶粒。
  4. 如申請專利範圍第1項之電子設備，其中：該導電夾子之一最小特徵尺寸為約100微米。
  5. 如申請專利範圍第1項之電子設備，該電子設備進一步包括：該頂部半導體晶粒之一第一頂部半導體正面電接點及該頂部半導體晶粒之一第二頂部半導體正面電接點，該第一頂部半導體正面電接點電耦接至該等周邊封裝引線中之一第一組，且該第二頂部半導體正面電接點電耦接至該單個半導體晶粒之該第三正面電接點。
  6. 如申請專利範圍第5項之電子設備，其中：該等兩個或更多個電晶體包括一高側電晶體及一低側電晶體；該高側電晶體包括一高側源極、一高側汲極及一高側閘極；該低側電晶體包括一低側源極、一低側汲極及一低側閘極；且該第三正面電接點電耦接至該高側閘極或該低側閘極中之一者或兩者。
  7. 如申請專利範圍第6項之電子設備，其中：該高側電晶體為一p型電晶體；該低側電晶體為一n型電晶體； 該高側閘極電耦接至該第三正面電接點；該低側閘極電耦接至該第三正面電接點；且使用該第三正面電接點來同時地切換該高側電晶體及該低側電晶體。
  8. 如申請專利範圍第1項之電子設備，其中：該等兩個或更多個電晶體包括一高側電晶體及一低側電晶體；該高側電晶體包括一高側源極、一高側汲極及一高側閘極；該低側電晶體包括一低側源極、一低側汲極及一低側閘極；該第一正面電接點電耦接至該高側汲極；該第二正面電接點將該高側源極與該低側汲極電耦接在一起；且該背面電接點電耦接至該低側源極。
  9. 如申請專利範圍第8項之電子設備，其中該頂部半導體背面電接點電耦接至該導電夾子。
  10. 如申請專利範圍第1項之電子設備，其中：該引線框包括一第四電連接器；該單個半導體晶粒包括電耦接至且實體安裝至該第四電連接器之一第四正面電接點；該等兩個或更多個電晶體包括一高側電晶體及一低側電晶體；該高側電晶體包括一高側源極、一高側汲極及一高側閘極；該低側電晶體包括一低側源極、一低側汲極及一低側閘極；該第一正面電接點電耦接至該高側汲極； 該第二正面電接點將該高側源極與該低側汲極電耦接在一起；該背面電接點電耦接至該高側源極；且該第四正面電接點電耦接至該低側源極。
  11. 如申請專利範圍第10項之電子設備，其中該頂部半導體背面電接點與該導電夾子實質上電隔離。
  12. 如申請專利範圍第1項之電子設備，其中：該等兩個或更多個電晶體包括一高側電晶體及一低側電晶體；該高側電晶體包括一高側源極、一高側汲極及一高側閘極；該低側電晶體包括一低側源極、一低側汲極及一低側閘極；該第一正面電接點電耦接至該高側汲極；該背面電接點將該高側源極與該低側汲極電耦接在一起；且該第二正面電接點電耦接至該低側源極。
  13. 如申請專利範圍第12項之電子設備，其中該頂部半導體背面電接點與該導電夾子實質上電隔離。
  14. 如申請專利範圍第1項之電子設備，其中：該等兩個或更多個電晶體包括一高側電晶體及一低側電晶體；該高側電晶體包括一高側源極、一高側汲極及一高側閘極；該低側電晶體包括一低側源極、一低側汲極及一低側閘極；該第一正面電接點電耦接至該高側汲極；該第二正面電接點將該高側源極與該低側汲極電耦接在一起；且 該低側源極電耦接至該背面電接點。
  15. 如申請專利範圍第14項之電子設備，其中該頂部半導體背面電接點電耦接至該導電夾子。
  16. 如申請專利範圍第1項之電子設備，其中：該引線框包括一第四電連接器；該單個半導體晶粒包括電耦接至且實體安裝至該第四電連接器之一第四正面電接點；該等兩個或更多個電晶體包括一高側電晶體、一低側電晶體及一第二低側電晶體；該高側電晶體包括一高側源極、一高側汲極及一高側閘極；該低側電晶體包括一低側源極、一低側汲極及一低側閘極；且該第二低側電晶體包括一第二低側源極、一第二低側汲極及一第二低側閘極；其中：該第一正面電接點將該高側源極與該第二低側汲極電耦接在一起；該第二正面電接點電耦接至該高側汲極；該第四正面電接點電耦接至該低側汲極；且該背面電接點將該低側源極與該第二低側源極電耦接在一起。
  17. 如申請專利範圍第16項之電子設備，其中該頂部半導體背面電接點電耦接至該導電夾子。
  18. 如申請專利範圍第1項之電子設備，其中該頂部 半導體背面電接點電耦接至該導電夾子。
  19. 如申請專利範圍第1項之電子設備，其中該頂部半導體背面電接點與該導電夾子實質上電隔離。
  20. 一種用於封裝半導體裝置之方法，該方法包括：提供一引線框，該引線框具有周邊封裝引線、一第一電連接器、一第二電連接器及一第三電連接器；形成一單個半導體晶粒，該單個半導體晶粒具有一正面及一背面，該背面具有一背面電接點，該正面具有一第一正面電接點及一第二正面電接點；將該第一正面電接點電耦接且實體安裝至該第一電連接器；將該第二正面電接點電耦接且實體安裝至該第二電連接器；提供一導電夾子，該導電夾子具有一第一電接觸表面、一第二電接觸表面及一第三電接觸表面，該第二電接觸表面與該第三電接觸表面係在該導電夾子之一部分的相對側上；將該導電夾子之該第一電接觸表面電耦接且實體安裝至該第三電連接器；將該導電夾子之該第二電接觸表面電耦接且實體安裝至該單個半導體晶粒之該背面電接點；提供一頂部半導體晶粒，該頂部半導體晶粒具有一頂部半導體正面、一頂部半導體背面及一頂部半導體背面電接點；及將該頂部半導體背面實體安裝至該導電夾子之該第三電接觸表面；其中：該單個半導體晶粒包括兩個或更多個電晶體及一第三正面 電接點，該第一正面電接點電耦接至該等兩個或更多個電晶體中之至少一者，該第二正面電接點電耦接至該等兩個或更多個電晶體中之至少一者，該第三正面電接點電耦接至該等兩個或更多個電晶體中之至少一者，且該背面電接點電耦接至該等兩個或更多個電晶體中之至少一者。
  21. 如申請專利範圍第20項之方法，其中：該頂部半導體晶粒為一控制器晶粒。
  22. 如申請專利範圍第20項之方法，其中：該單個半導體晶粒為一功率半導體晶粒。
  23. 如申請專利範圍第20項之方法，其中該導電夾子與該頂部半導體背面電接點實質上電隔離。
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