TW202333344A - 半導體裝置和電路設備 - Google Patents

半導體裝置和電路設備 Download PDF

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Publication number
TW202333344A
TW202333344A TW112103210A TW112103210A TW202333344A TW 202333344 A TW202333344 A TW 202333344A TW 112103210 A TW112103210 A TW 112103210A TW 112103210 A TW112103210 A TW 112103210A TW 202333344 A TW202333344 A TW 202333344A
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Taiwan
Prior art keywords
semiconductor
semiconductor substrate
mosfet
region
type
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TW112103210A
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English (en)
Inventor
森和久
波多俊幸
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日商瑞薩電子股份有限公司
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Publication of TW202333344A publication Critical patent/TW202333344A/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0063—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with circuits adapted for supplying loads from the battery
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H03—ELECTRONIC CIRCUITRY
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    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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Abstract

提高了半導體裝置的性能。減少了使用半導體裝置作為開關的電路設備的損耗。一種半導體裝置（100）包括：具有p型第一MOSFET（1Q）和第一寄生二極體（D1）的第一半導體晶片（CHP1）；以及具有n型第二MOSFET（2Q）和第二寄生二極體（D2）的第二半導體晶片（CHP2）。在第一半導體晶片（CHP1）和第二半導體晶片（CHP2）的前表面上，分別形成有第一源極電極（SE1）和第一柵極佈線（GW1）以及第二源極電極（SE2）和第二柵極佈線（GW2）。在第一半導體晶片和第二半導體晶片的後表面上，分別形成有第一汲極電極（DE1）和第二汲極電極（DE2）。第二後表面（BS2）和第一前表面（TS1）彼此面對，使得第二汲極電極（DE2）和第一源極電極（SE1）經由導電膏彼此接觸。

Description

半導體裝置和電路設備
本發明涉及半導體裝置和電路設備，並且具體地涉及包括n型金屬氧化物半導體場效應晶體管（MOSFET）的半導體裝置、以及使用該半導體裝置的電路設備。 [相關申請的交叉引用] 於2022年2月3日提交的日本專利申請No.2022-015406的公開內容（包括說明書、附圖和摘要）通過引用整體併入本文。
在汽車上，安裝有大量需要電力的電器，例如前照燈和電動車窗。迄今為止，繼電器已經被用作開關，以用於向這些電器供應從電池輸出的電力，或用於切斷來自電池的電力。近年來，已經使用包括n型功率MOSFET的半導體裝置來代替這種繼電器。
在維護電池時，有時會斷開連接到電池的電纜，並且當電池完成維護之後，電纜會重新連接到電池。因此，在某些情況下，會發生故障：電纜反接到電池的正極和負極。在使用繼電器的開關中，如果開關處於OFF狀態，即使電纜反接，電流也不會流動。
然而，在使用半導體裝置的開關中，即使功率MOSFET變為OFF狀態，電流也流過功率MOSFET中形成的寄生二極體。為了防止這種電流回流，p型功率MOSFET被串聯連接在n型功率MOSFET的汲極與電池的正極之間。
在這種情況下，針對半導體裝置（半導體模塊）的形式，可以設想一種方法，該方法是將包括n型功率MOSFET的半導體晶片和包括p型功率MOSFET的半導體晶片作為單獨的封裝（第一情況示例）來進行製備。備選地，可以設想一種方法，該方法是將包括n型功率MOSFET的半導體晶片和包括p型功率MOSFET的半導體晶片平放，並且將它們製備為一個封裝（第二情況示例）。然而，第一情況示例具有半導體模塊的實現面積增大的問題，而第二情況示例具有封裝的面積增大的問題。
下面列出了公開的技術。
[專利文獻1]日本未審查專利申請公開No.2016-207716
[專利文獻2]日本未審查專利申請公開No.2012-243930
在專利文獻1中，為了防止電流的回流，使用串聯連接的n型功率MOSFET（同時其源極/汲極的取向反轉）來代替p型功率MOSFET。專利文獻1公開了一種半導體裝置（第三情況示例），其中兩個n型功率MOSFET形成在同一半導體襯底上並且被製備為一個封裝。n型功率MOSFET中的一個n型功率MOSFET的源極連接到電池的正極，n型功率MOSFET中的一個n型功率MOSFET的汲極連接到另一n型功率MOSFET的汲極，另一n型功率MOSFET的源極連接到電池的負極。
此外，專利文獻2公開了一種半導體裝置，其中溝槽柵型的n型功率MOSFET和平面型的n型MOSFET形成在同一半導體襯底上。
在專利文獻1的半導體裝置（第三情況示例）中，與第一情況示例和第二情況示例相比，可以減小實現面積和封裝的面積。
然而，彼此連接的兩個n型功率MOSFET的汲極經由半導體襯底中的n型漂移區、形成在半導體襯底的後表面側的汲極電極和形成在汲極電極下方的引線框架彼此電連接。即，由於兩個n型功率MOSFET之間在橫向方向上的電阻分量增加，因此存在難以提高半導體裝置的性能的問題。因此，在使用半導體裝置作為開關的情況下，存在難以減少開關損耗的問題。
本申請的主要目的是與第一情況示例和第二情況示例相比減小安裝面積和封裝的面積，並且與第三情況示例相比減少電阻分量並且提高半導體裝置的性能。因此，減少了使用半導體裝置作為開關的電路設備的損耗。
根據說明書和附圖中的描述，其他目的和新穎特徵將很清楚。
下面將簡要描述本申請中公開的實施例中的代表的概要。
作為實施例的一種半導體裝置包括：具有p型第一MOSFET和形成在第一MOSFET中的第一寄生二極體的第一半導體晶片；以及具有n型第二MOSFET和形成在第二MOSFET中的第二寄生二極體的第二半導體晶片。在此，第一源極電極和第一柵極佈線形成在第一半導體晶片的前表面上，第一汲極電極形成在第一半導體晶片的後表面上，第一寄生二極體的第一陽極耦接到第一汲極電極，並且第一寄生二極體的第一陰極耦接到第一源極電極，第二源極電極和第二柵極佈線形成在第二半導體晶片的前表面上，第二汲極電極形成在第二半導體晶片的後表面上，第二寄生二極體的第二陽極耦接到第二源極電極，並且第二寄生二極體的第一陰極耦接到第二汲極電極，並且第二半導體晶片的後表面和第一半導體晶片的前表面彼此面對，使得第二汲極電極和第一源極電極經由導電構件彼此接觸。
根據該實施例，可以提高半導體裝置的性能。此外，可以減少使用半導體裝置作為開關的電路設備的損耗。
在下文中，將參考附圖詳細描述實施例。應注意，在用於描述實施例的所有附圖中，相同的附圖標記被分配給具有相同功能的構件，並且將省略其重複描述。此外，在以下實施例中，除非特別必要，否則原則上不重複相同或類似部分的描述。
第一實施例
＜使用半導體裝置的電路設備＞
圖1示出了第一實施例中的使用半導體裝置100作為開關的電路設備。半導體裝置100是半導體模塊，並且包括：半導體晶片CHP1，其包括p型MOSFET 1Q和寄生二極體D1；以及半導體晶片CHP2，其包括n型MOSFET 2Q和寄生二極體D2。此外，在一些情況下，半導體裝置100包括具有控制電路CTRL的半導體晶片CHP3。
圖1中的電路設備包括要用作開關的半導體裝置100、電池BA和負載LAD。負載LAD是安裝在汽車上的電器，例如前照燈和電動車窗。
MOSFET 1Q的汲極電極DE1電連接到電池BA的正極。MOSFET 1Q的源極電極SE1電連接到MOSFET 2Q的汲極電極DE2。MOSFET 2Q的源極電極SE2經由負載LAD電連接到電池BA的負極。MOSFET 1Q的柵極電極GE1電固定到地電位（GND）。MOSFET 2Q的柵極電極GE2電連接到控制電路CTRL。
注意，控制電路CTRL具有向柵極電極GE2提供柵極電位以便使MOSFET 2Q在ON狀態與OFF狀態之間切換的功能。此外，作為具有另一功能的電路，控制電路CTRL有時包括升壓電路、熱關斷控制電路、過電流限制電路、感測電流、電壓等的監測電路等。
寄生二極體D1形成在MOSFET 1Q中。如圖1所示，該寄生二極體D1的陽極耦接到汲極電極DE1。此外，如圖1所示，該寄生二極體D1的陰極耦接到源極電極SE1。
寄生二極體D2形成在MOSFET 2Q中。如圖1所示，該寄生二極體D2的陽極耦接到源極電極SE2。此外，如圖1所示，該寄生二極體D2的陰極耦接到汲極電極DE2。
MOSFET 2Q是用於在電池BA適當地耦接到半導體裝置100時根據需要執行開關操作（ON操作和OFF操作）以向負載LAD供應電力的裝置。MOSFET 1Q是用於在電池BA反接到半導體裝置100時防止電流回流的裝置。
將給出當電池BA適當地耦接到半導體裝置100時的電路操作的描述。首先，對從電池BA向負載LAD提供電力的情況進行說明。MOSFET 1Q的柵極電極GE1固定到地電位，並且相對於源極電極SE1處於低電位狀態，並且因此，MOSFET 1Q處於ON狀態。從控制電路CTRL向柵極電極GE2提供有等於或大於MOSFET 2Q的閾值電壓的柵極電位，由此MOSFET 2Q變為ON狀態。因此，電流從電池BA流向負載LAD。
將描述切斷提供給負載LAD的電力的情況。MOSFET 1Q的柵極電極GE1固定到地電位，並且相對於源極電極SE1處於這樣的低電位狀態，並且因此，MOSFET 1Q處於ON狀態。例如，從控制電路CTRL向柵極電極GE2提供有地電位（GND），由此MOSFET 2Q變為OFF狀態。因此，電流不會從電池BA流向負載LAD。
接下來，將描述當電池BA反接到半導體裝置100時的電路操作。當電池BA反接到半導體裝置100時，固定到地電位（GND）的MOSFET 1Q的柵極電極GE1固定到電池BA的正極電位（其是電路中的最高電位），並且相對於源極電極SE1變為高電位狀態，並且因此，MOSFET 1Q變為OFF狀態。此外，也沒有電流流向寄生二極體D1。因此，可以防止電流從電池BA流向負載LAD。
＜MOSFET和寄生二極體的結構＞
半導體晶片CHP1具有前表面TS1和後表面BS1，並且半導體晶片CHP2具有前表面TS2和後表面BS2。圖2是從前表面TS1側觀察半導體晶片CHP1的平面圖。圖3是從前表面TS2側觀察半導體晶片CHP2的平面圖。注意，半導體晶片CHP1的平面面積大於半導體晶片CHP2的平面面積。
如圖2所示，源極電極SE1和柵極佈線GW1形成在半導體晶片CHP1的前表面TS1上。半導體晶片CHP1的大部分被源極電極SE1覆蓋，並且MOSFET 1Q主要形成在源極電極SE1下方。此外，MOSFET 1Q的柵極電極GE1電連接到柵極佈線GW2。
如圖3所示，源極電極SE2和柵極佈線GW2形成在半導體晶片CHP2的前表面TS2上。半導體晶片CHP1的大部分被源極電極SE2覆蓋，並且MOSFET 2Q主要形成在源極電極SE2下方。此外，MOSFET 2Q的柵極電極GE2電連接到柵極佈線GW1。
參考圖4，下面將描述MOSFET 1Q、寄生二極體D1、MOSFET 2Q和寄生二極體D2的結構。注意，多個MOSFET實際上形成在半導體晶片CHP1和CHP2中的每個上，並且它們彼此並聯連接。因此，就等效電路而言，上述多個MOSFET可以被視為一個MOSFET。本申請中描述的MOSFET 1Q和2Q中的每個通過將上述彼此並聯耦接的多個MOSFET聚合而製成一個MOSFET。
首先，將描述MOSFET 1Q和寄生二極體D1的結構。
半導體襯底SUB1具有前表面和後表面，並且具有低濃度的p型漂移區PV。這裡，半導體襯底SUB1是p型矽襯底，並且半導體襯底SUB1本身構成漂移區PV。注意，漂移區PV可以是在通過外延生長將硼（B）引入矽襯底上的同時生長的p型矽襯底和半導體層的疊層。本申請將在這樣的疊層也是半導體襯底SUB1的前提下描述。
在半導體襯底SUB1的前表面側，在半導體襯底SUB1中形成有n型本體區NB。在本體區NB中形成有p型源極區PS。源極區PS具有高於漂移區PV的雜質濃度。
在半導體襯底SUB1的前表面側，在半導體襯底SUB1中形成有溝槽TR。溝槽TR的底部到達比本體區NB更深的位置。柵極絕緣膜GI形成在溝槽TR內。柵極電極GE1形成在柵極絕緣膜GI上以填充溝槽TR的內部。即，MOSFET 1Q形成溝槽柵型結構。柵極絕緣膜GI例如是氧化矽膜，並且柵極電極GE1例如是p型多晶矽膜。
在半導體襯底SUB1的前表面上，以能夠覆蓋柵極電極GE1的方式形成有層間絕緣膜IL。層間絕緣膜IL是例如氧化矽膜。在層間絕緣膜IL中形成有孔CH。孔CH穿透層間絕緣膜IL和源極區PS，使得其底部位於本體區NB中。此外，在孔CH的底部上，在本體區NB中形成有n型的高濃度區NR。高濃度區NR具有高於本體區NB的雜質濃度。
在層間絕緣膜IL上，以能夠填充孔CH的內部的方式形成有源極電極SE1。源極電極SE1電連接到源極區PS、本體區NB和高濃度區NR，並且向其提供源極電位。注意，儘管這裡未示出，但是柵極佈線GW1也形成在層間絕緣膜IL上。多個柵極電極GE1共同連接到半導體晶片CHP1的外周部分上的柵極提取部分。孔CH也形成在柵極提取部分上，並且柵極佈線GW1嵌入到孔CH的內部。因此，柵極佈線GW1電連接到柵極電極GE1，並且將柵極電位提供給柵極電極GE1。
源極電極SE1和柵極佈線GW1中的每個例如由阻擋金屬膜和形成在上述阻擋金屬膜上的導電膜構成。上述阻擋金屬膜例如是氮化鈦膜，並且上述導電膜例如是鋁膜。
注意，源極電極SE1和柵極佈線GW1中的每個可以由填充孔CH的內部的插塞層和形成在層間絕緣膜IL上的佈線部分組成。在這種情況下，上述佈線部分是上述氮化鈦膜和鋁膜的層疊膜，並且上述插塞層是諸如氮化鈦膜等阻擋金屬膜和諸如鎢膜等導電膜的層疊膜。
在半導體襯底SUB1的後表面側，在半導體襯底SUB1中形成有p型汲極區PD。汲極區PD具有高於漂移區PV的雜質濃度。在半導體襯底SUB1的後表面上，形成有汲極電極DE1。汲極電極DE1電連接到汲極區PD和漂移區PV，並且向汲極區PD提供汲極電位。汲極電極DE1例如由諸如鋁膜、鈦膜、鎳膜、金膜和銀膜等單個金屬膜構成，或者由通過適當地將這些金屬膜彼此層疊而形成的層疊膜構成。
寄生二極體D1由本體區NB、以及位於本體區NB下方的半導體襯底SUB1（漂移區PV）和汲極區PD構成。即，寄生二極體D1是PN二極體，其中在半導體晶片CHP1中，陽極是半導體襯底SUB1和汲極區PD，並且陰極是本體區NB。
接下來，將描述MOSFET 2Q和寄生二極體D2的結構。
半導體襯底SUB2具有前表面和後表面，並且具有低濃度的n型漂移區NV。這裡，半導體襯底SUB2是n型矽襯底，並且半導體襯底SUB本身構成漂移區NV。注意，漂移區NV可以是在通過外延生長將磷（P）引入矽襯底上的同時生長的n型矽襯底和半導體層的疊層。本申請將在這樣的疊層也是半導體襯底SUB2的前提下描述。
在半導體襯底SUB2的前表面側，在半導體襯底SUB2中形成有p型本體區PB。在本體區PB中形成有n型源極區NS。源極區NS具有高於漂移區NV的雜質濃度。
在半導體襯底SUB2的前表面側，在半導體襯底SUB2中形成有溝槽TR。溝槽TR的底部到達比本體區PB更深的位置。柵極絕緣膜GI形成在溝槽TR內。柵極電極GE2形成在柵極絕緣膜GI上以填充溝槽TR的內部。即，MOSFET 2Q形成溝槽柵型結構。柵極絕緣膜GI例如是氧化矽膜，並且柵極電極GE2例如是n型多晶矽膜。
在半導體襯底SUB2的前表面上，以能夠覆蓋柵極電極GE2的方式形成有層間絕緣膜IL。層間絕緣膜IL是例如氧化矽膜。在層間絕緣膜IL中形成有孔CH。孔CH穿透層間絕緣膜IL和源極區NS，使得其底部位於本體區PB中。此外，在孔CH的底部上，在本體區PB中形成有p型的高濃度區PR。高濃度區PR具有高於本體區PB的雜質濃度。
在層間絕緣膜IL上，以能夠填充孔CH的內部的方式形成有源極電極SE2。源極電極SE2電連接到源極區NS、本體區PB和高濃度區PR，並且向其提供源極電位。注意，儘管這裡未示出，但是柵極佈線GW2也形成在層間絕緣膜IL上。多個柵極電極GE2共同連接到半導體晶片CHP2的外周部分上的柵極提取部分。孔CH也形成在柵極提取部分上，並且柵極佈線GW2嵌入到孔CH的內部。因此，柵極佈線GW2電連接到柵極電極GE2，並且將柵極電位提供給柵極電極GE2。
在半導體襯底SUB2的後表面側，在半導體襯底SUB2中形成有n型汲極區ND。汲極區ND具有高於漂移區NV的雜質濃度。在半導體襯底SUB2的後表面上，形成有汲極電極DE2。汲極電極DE2電連接到汲極區ND和漂移區NV，並且向汲極區ND提供汲極電位。
構成源極電極SE2、柵極佈線GW2和汲極電極DE2的材料分別與構成源極電極SE1、柵極佈線GW1和汲極電極DE1的材料相同。
寄生二極體D2由本體區PB、以及位於本體區PB下方的半導體襯底SUB2（漂移區NV）和汲極區ND構成。即，寄生二極體D2是PN二極體，其中在半導體晶片CHP2中，陽極是本體區PB，並且陰極是半導體襯底SUB2和汲極區ND。
注意，在MOSFET 2Q中，在位於體區PB下方的半導體襯底SUB2中形成有p型的柱區PC。柱區PC具有高於本體區PB的雜質濃度。在n型MOSFET 2Q的情況下，形成這樣的p型柱區PC，由此可以耗盡柱區PC的外圍，並且可以提高其耐受電壓。
這裡，由於柱區PC與本體區PB接觸，所以源極電位也被提供給p型柱區PC。然而，柱區PC可以與本體區PB物理分離，並且可以採用浮置結構。
出於與柱區PC相同的目的，在MOSFET 1Q中也可以形成有n型柱區；然而，當形成柱區時，導通電阻增加。MOSFET 2Q是用作圖1的電路設備中的開關的主要裝置。因此，優選的是，在MOSFET 2Q中形成有柱區PC，以確保當電池BA連接到開關時開關的可靠性。優選的是，為了快速地向負載LAD供電，不應當在MOSFET 1Q中設置柱區，以減小導通電阻。
＜半導體裝置的結構＞
參考圖2至圖10，下面將描述半導體裝置100的結構。圖5是示出半導體裝置100的平面圖。圖7是沿著圖5中的線A-A截取的截面圖。圖8是沿著圖6中的線B-B截取的截面圖。
注意，圖6示出了在包括控制電路CTRL的半導體晶片CHP3安裝在半導體晶片CHP1上的情況下的狀態。半導體晶片CHP3設置在源極電極SE2上，其間插入有絕緣樹脂。在這種情況下，儘管未示出，但是在半導體晶片CHP3的前表面上設置有焊盤電極作為控制電路CTRL的一部分，並且該焊盤電極和柵極佈線GW1通過諸如接合線等外部連接構件11彼此電連接。在圖7和圖8中，為了簡化說明，沒有示出半導體晶片CHP3。
如圖7和圖8所示，在半導體裝置100中，半導體晶片CHP1和半導體晶片CHP2彼此層疊。即，半導體晶片CHP2的後表面BS2和半導體晶片CHP1的前表面TS1彼此面對，使得汲極電極DE2和源極電極SE1可以彼此接觸，其間插入有導電構件。導電構件是諸如銀膏和焊料等導電膏30。注意，就實現容易性而言，在具有大平面面積的半導體晶片CHP1上層疊具有小平面面積的晶片CHP2是有利的。
如圖5至圖8所示，在半導體晶片CHP1的前表面TS1側，柵極佈線GW1連接到外部連接構件11，其間插入有導電膏10。在半導體晶片CHP1的後表面BS1側，汲極電極DE1連接到引線框架12，其間插入有導電膏10。在半導體晶片CHP2的前表面TS2側，源極電極SE2和柵極佈線GW2連接到外部連接構件21，其間插入有導電膏20。
導電膏10和20例如是銀膏。外部連接構件11和21例如是由銅或鋁製成的夾子（銅板）或接合線。這裡，示出了外部連接構件11和21是夾子的情況，並且夾子被加工成朝向半導體晶片CHP1的後表面BS1彎曲。
如圖9和圖10所示，半導體晶片CHP1、半導體晶片CHP2、導電膏30、外部連接構件11和21以及引線框架12用密封樹脂MR密封。外部連接構件11和21以及引線框架12部分地從密封樹脂MR暴露。因此，MOSFET 1Q和2Q可以經由外部連接構件11和21以及引線框架12的這種暴露部分電連接到其他半導體晶片、佈線板或電子儀器。即，由MOSFET 1Q和2Q構成的開關可以電連接到這樣的電池BA和負載LAD，如圖1所示。
注意，當半導體晶片CHP3如圖6所示安裝時，半導體晶片CHP2用密封樹脂MR與半導體晶片CHP1和CHP2一起密封，由此半導體晶片CHP1至CHP3可以設置為一個封裝。此外，半導體晶片CHP3以及半導體晶片CHP1和CHP2可以彼此分開封裝。
＜與研究示例的比較＞
圖11和圖12示出了本申請的發明人已經研究了在專利文獻1中公開的封裝兩個n型MOSFET的情況（第三情況示例）的研究示例中的半導體裝置500。
如圖11和圖12所示，研究示例中的半導體晶片CHP5包括形成在同一半導體襯底上的n型MOSFET 5Q和n型MOSFET 2Q。在半導體晶片CHP5的前表面TS5上，形成有源極電極SE5和柵極佈線GW5，並且在半導體晶片CHP5的後表面BS5上，形成有汲極電極DE5。
參考圖1中的等效電路，n型MOSFET 2Q對應於用作電路設備中的開關的主要裝置。然後，n型MOSFET 5Q對應於代替圖1中的p型MOSFET 1Q而應用並且用於防止電流回流的裝置。n型MOSFET 5Q的汲極耦接到n型MOSFET 2Q的汲極，由此提供了與圖1中的電路設備等效的這樣的電路設備。
源極電極SE5和柵極佈線GW5直接連接到外部連接構件51，汲極電極DE5連接到引線框架53，其間插入有導電膏52。包括控制電路CTRL的半導體晶片CHP3設置在源極電極SE5上，其間插入有絕緣樹脂54。
在研究示例中，兩個MOSFET 2Q和5Q的汲極彼此電連接，其間插入有半導體襯底中的n型漂移區、汲極電極DE5和引線框架53。因此，存在這樣的問題，即，由於兩個MOSFET 2Q與5Q之間在橫向方向上的電阻分量增加，所以難以減少開關的損耗。因此，存在難以提高半導體裝置的性能的問題。
此外，由於MOSFET 2Q和5Q形成在同一半導體襯底上，所以它們的相應形成面積減小。特別地，當優先考慮作為主要裝置的MOSFET 2Q時，MOSFET 5Q的形成面積易於減小。因此，存在難以降低MOSFET 2Q和5Q中的每個的導通電阻的問題。此外，由於外部連接構件51的占地面積不能增加，因此存在與這些相關的電阻值容易增加的問題。
圖13是將根據第一實施例的半導體裝置100和根據研究示例的半導體裝置500關於相應電阻值彼此進行比較的表。注意，圖13中的數值被示出為相對值。此外，在此，上述數值是在假定根據第一實施例的MOSFET 2Q的形成面積與根據研究示例的MOSFET 2Q的形成面積大致相同的情況下計算的。
通常，在p型MOSFET中，其載流子遷移率比具有相同尺寸的n型MOSFET低大約三倍。因此，根據第一實施例的p型MOSFET 1Q的導通電阻比具有相同尺寸的n型MOSFET的導通電阻增加得更多。然而，由於包括p型MOSFET 1Q的半導體晶片CHP1與半導體晶片CHP2分開設置，因此根據研究示例，MOSFET 1Q的形成面積可以比MOSFET 5Q的形成面積增加得更多。因此，可以使MOSFET 1Q的導通電阻基本上等於MOSFET 5Q的導通電阻。
此外，在第一實施例中，外部連接構件11和21可以分別設置在半導體晶片CHP1的前表面TS1和半導體晶片CHP2的前表面TS2上，並且引線框架12可以設置在半導體晶片CHP1的後表面BS1上。因此，外部連接構件和引線框架的占地面積增加，並且容易降低與這些相關的電阻值。廣義地說，在第一實施例中，可以佈置外部連接構件和引線框架，它們大約是研究示例中的四到五倍。
此外，儘管橫向方向上的電阻分量較大，例如，在研究示例中的引線框架53中，在第一實施例中，汲極電極DE2和源極電極SE1在縱向方向上彼此接觸，導電膏30插在其間。因此，汲極電極DE2與源極電極SE1之間的距離較短，並且因此，兩個MOSFET 1Q與2Q之間的電阻分量可以減小。
此外，如背景技術中所述，第一情況示例和第二情況示例作為實現包括n型MOSFET的半導體晶片和包括p型MOSFET半導體晶片的方法而存在。第一情況示例是將兩個半導體晶片製備為兩個單獨封裝的方法，而第二情況示例則是在橫向方向上將兩個半導體晶片平放並且將其製備為一個封裝的方法。
在第一實施例中，半導體晶片CHP1和半導體晶片CHP2在縱向方向上彼此層疊，並且被實現為一個封裝。因此，在第一實施例中，與第一情況示例和第二情況示例相比，可以減小封裝的面積，並且還可以減小半導體模塊的實現面積。
此外，在第一實施例中，p型MOSFET 1Q的柵極電極GE1電固定到地電位。因此，控制電路CTRL不需要用於在ON狀態與OFF狀態之間切換MOSFET 1Q的功能。因此，可以簡化控制電路CTRL，並且可以使包括控制電路CTRL的半導體晶片CHP3小型化。
如上所述，根據第一實施例，可以實現與研究示例（第三情況示例）的實現面積和封裝面積基本相等的實現面積和封裝面積，並且可以比研究示例中更多地減小電阻分量，並且因此，可以增強半導體裝置100的性能。此外，可以減少使用半導體裝置100作為開關的電路設備的損耗。
第二實施例
下面將參考圖14和圖15描述第二實施例中的半導體裝置100。注意，在以下描述中，將主要描述與第一實施例的不同之處，並且將省略與第一實施例的相同之處的描述。
在第一實施例中，控制電路CTRL被包括在半導體晶片CHP3中。如圖14所示，在第二實施例中，控制電路CTRL被包括在半導體晶片CHP2中。構成控制電路CTRL的晶體管形成在半導體襯底SUB2的與其中形成有MOSFET 2Q的區域不同的區域中。
構成控制電路CTRL的晶體管是例如如圖15所示的n型MOSFET 3Q和p型MOSFET 4Q。MOSFET 3Q和4Q中的每個形成平面型結構。在其中形成有MOSFET 3Q和4Q的區域中，在半導體襯底SUB2中形成有p型阱區DPW，並且MOSFET 2Q以及MOSFET 3Q和4Q通過阱區DPW彼此電隔離。
將描述MOSFET 3Q的結構。在阱區DPW上，形成有柵極電極GE3，柵極絕緣膜GI3插入在其間。在阱區DPW中，形成有n型擴散區N3。擴散區N3構成MOSFET 3Q的源極區或汲極區。
將描述MOSFET 4Q的結構。在其中形成有MOSFET 4Q的阱區DPW中，形成有n型阱區NW。在阱區NW上，形成有柵極電極GE4，柵極絕緣膜GI4插入在其間。在阱區NW中，形成有p型擴散區P4。擴散區P4構成MOSFET 4Q的源極區或汲極區。
MOSFET 3Q和4Q被層間絕緣膜IL覆蓋，並且在層間絕緣薄膜IL上，形成有多個焊盤電極PAD。多個焊盤電極PAD電連接到柵極電極GE3和GE4以及擴散區N3和P4。注意，多個焊盤電極PAD是在與源極電極SE2和柵極佈線GW2相同的製造工藝中形成的，並且由與源極電極SE2和柵極佈線GW2相同材料製成。
形成多個MOSFET 3Q和4Q中的每個，並且MOSFET 3Q和4Q與多個焊盤電極PAD一起構成諸如CMOS反相器等各種電路。此外，儘管這裡未示出，但是MOSFET 3Q和4Q電連接到其他半導體晶片、佈線板、電子儀器等，外部連接構件（接合線）插入在其間，外部連接構件連接到多個焊盤電極PAD。因此，MOSFET 3Q和4Q可以電連接到MOSFET 1Q和2Q。
如上所述，控制電路CTRL內置在半導體晶片CHP2中，因此不需要製備半導體晶片CHP3。因此，可以簡化半導體裝置100的製造。注意，控制電路CTRL可以代替半導體晶片CHP2而內置在半導體晶片CHP1中。
雖然以上已經基於上述實施例具體描述了本發明，但是本發明不限於上述實施例，並且在不脫離其精神的情況下，可以在範圍內以各種方式修改。
例如，在上述實施例中，已經給出了電路設備的負載LAD是用於汽車的電器的情況的描述；然而，電路設備不限於用於汽車，並且負載LAD可以是用於汽車以外的其他電器。
此外，在半導體襯底SUB1和SUB2是矽襯底的假定下描述了上述實施例。然而，半導體襯底SUB1和SUB2的材料不限於矽，並且半導體襯底SUB2和SUB1可以是碳化矽襯底（SiC襯底）。
此外，在上述實施例中，MOSFET 1Q和2Q採用溝槽柵型結構。然而，如果MOSFET 1Q和2Q具有其中源極電極SE1和SE2以及柵極佈線GW1和GW2設置在表面TS1和TS2側並且汲極電極DE1和DE2設置在後表面BS1和BS2側的結構，則MOSFET 1Q和2Q可以是平面型的。也就是說，不必形成溝槽TR，並且電極GE1和GE2可以形成在半導體襯底SUB1和SUB2上，柵極絕緣膜GI插入在其間。
BA:電池 BS1、BS2、BS5:背面 CH:孔 CHP1～CHP3、CHP5:半導體晶片 CTRL:控制電路 D1、D2:寄生二極體 DE1、DE2、DE5:汲極電極 DPW:阱區 GE1～GE4:柵極電極 GI、GI3、GI4:柵極絕緣膜 GW1、GW2、GW5:柵極佈線 IL:層間絕緣膜 LAD:負載 MR:密封 N3:擴散區 NB:本體區 ND:汲極區 NR:高濃度區 NS:源極區 NV:漂移區 NW:阱區 P4:擴散區 PAD:焊盤電極 PB:本體區 PC:柱區 PD:汲極區 PR:高濃度區 PS:源極區 PV:漂移區 1Q～5Q:MOSFET SUB1、SUB2:半導體襯底 SE1、SE2、SE5:源極電極 TR:溝槽 TS1、TS2、TS5:前表面 10、20、30、52:導電膏 11、21、51:外部連接構件 12、53:引線框架 54:絕緣樹脂 100、500:半導體裝置
圖1是示出第一實施例中的使用半導體裝置的電路設備的等效電路圖；
圖2是示出第一實施例中的兩個半導體晶片中的一個的平面圖；
圖3是示出第一實施例中的另一半導體晶片的平面圖；
圖4是示出第一實施例中的形成在兩個半導體晶片中的兩個MOSFET以及形成在其中的兩個寄生二極體的截面圖；
圖5是示出第一實施例中的半導體裝置的平面圖；
圖6是示出第一實施例中的半導體裝置的平面圖；
圖7是示出第一實施例中的半導體裝置的截面圖；
圖8是示出第一實施例中的半導體裝置的截面圖；
圖9是示出第一實施例中的半導體裝置的截面圖；
圖10是示出第一實施例中的半導體裝置的截面圖；
圖11是示出研究示例中的半導體裝置的平面圖；
圖12是示出研究示例中的半導體裝置的截面圖；
圖13是將第一實施例的電阻值與研究示例的電阻值進行比較的表；
圖14是示出第二實施例中的另一半導體晶片的平面圖；以及
圖15是示出第二實施例中的構成控制電路的MOSFET的截面圖。
11、21:外部連接構件
100:半導體裝置
CHP1~CHP2:半導體晶片
GW1、GW2:柵極佈線
SE1、SE2:源極電極
TS1、TS2:前表面

Claims (7)

  1. 一種半導體裝置，包括： 第一半導體晶片，包括p型第一MOSFET和形成在該第一MOSFET中的第一寄生二極體；以及 第二半導體晶片，包括n型第二MOSFET和形成在該第二MOSFET中的第二寄生二極體， 其中第一源極電極和第一柵極佈線形成在該第一半導體晶片的前表面上， 其中第一汲極電極形成在該第一半導體晶片的後表面上， 其中該第一寄生二極體的第一陽極耦接到該第一汲極電極，並且該第一寄生二極體的第一陰極耦接到該第一源極電極， 其中第二源極電極和第二柵極佈線形成在該第二半導體晶片的前表面上， 其中第二汲極電極形成在該第二半導體晶片的後表面上， 其中該第二寄生二極體的第二陽極耦接到該第二源極電極，並且該第二寄生二極體的第二陰極耦接到該第二汲極電極，以及 其中該第二半導體晶片的該後表面和該第一半導體晶片的該前表面彼此面對，使得該第二汲極電極和該第一源極電極經由導電構件彼此接觸。
  2. 如請求項1所述的半導體裝置， 其中該第一柵極佈線電固定到地電位。
  3. 如請求項2所述的半導體裝置，更包括第三半導體晶片，該第三半導體晶片包括電連接到該第二柵極佈線的控制電路， 其中該控制電路具有向該第二柵極佈線提供柵極電位以使該第二MOSFET在ON狀態與OFF狀態之間切換的功能。
  4. 如請求項2所述的半導體裝置， 其中該第二半導體晶片更包括電連接到該第二柵極佈線的控制電路，以及 其中該控制電路具有向該第二柵極佈線提供柵極電位以使該第二MOSFET在ON狀態與OFF狀態之間切換的功能。
  5. 如請求項1所述的半導體裝置，其中該第一半導體晶片包括： p型第一半導體襯底，具有前表面和後表面； n型第一本體區，在該第一半導體襯底的該前表面側，形成於該第一半導體襯底中； p型第一源極區，形成在該第一本體區中； 第一溝槽，在該第一半導體襯底的該前表面側，形成於該第一半導體襯底中，使得該第一溝槽的底部位於該第一本體區下方； 第一柵極絕緣膜，形成在該第一溝槽內； 第一柵極電極，形成在該第一柵極絕緣膜上以填充該第一溝槽的內部； 第一層間絕緣膜，形成在該第一半導體襯底的該前表面上； 該第一源極電極，形成在該第一層間絕緣膜上並且電連接到該第一本體區和該第一源極區； 該第一柵極佈線，形成在該第一層間絕緣膜上並且電連接到該第一柵極電極； p型第一汲極區，在該第一半導體襯底的該後表面側，形成於該第一半導體襯底中；以及 該第一汲極電極，形成在該第一半導體襯底的該後表面下方並且電連接到該第一汲極區， 其中該第二半導體晶片包括： n型第二半導體襯底，具有前表面和後表面； p型第二本體區，在該第二半導體襯底的該前表面側，形成於該第二半導體襯底中； n型第二源極區，形成在該第二本體區中； 第二溝槽，在該第二半導體襯底的該前表面側，形成於該第二半導體襯底中，使得該第二溝槽的底部位於該第二本體區下方； 第二柵極絕緣膜，形成在該第二溝槽內； 第二柵極電極，形成在該第二柵極絕緣膜上以填充該第二溝槽的內部； 第二層間絕緣膜，形成在該第二半導體襯底的該前表面上； 該第二源極電極，形成在該第二層間絕緣膜上並且電連接到該第二本體區和該第二源極區； 該第二柵極佈線，形成在該第二層間絕緣膜上並且電連接到該第二柵極電極； n型第二汲極區，在該第二半導體襯底的該後表面側，形成於該第二半導體襯底中；以及 該第二汲極電極，形成在該第二半導體襯底的該後表面下方並且電連接到該第二汲極區， 其中該第一寄生二極體由該第一本體區、以及位於該第一本體區下方的該第一半導體襯底和該第一汲極區組成，以及 其中該第二寄生二極體由該第二本體區、以及位於該第二本體區下方的該第二半導體襯底和該第二汲極區組成。
  6. 如請求項5所述的半導體裝置， 其中該第二半導體晶片更包括：p型柱區，形成在位於該第二本體區下方的該第二半導體襯底中。
  7. 一種使用如請求項1所述的半導體裝置作為開關的電路設備，包括： 電池，具有正極和負極；以及 負載， 其中該第一汲極電極電連接到該正極，並且 其中該第二源極電極經由該負載電連接到該負極。
TW112103210A 2022-02-03 2023-01-31 半導體裝置和電路設備 TW202333344A (zh)

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