TWI755485B - 用於使串擾減至最小之積體電路封裝設備及積體電路封裝方法 - Google Patents

用於使串擾減至最小之積體電路封裝設備及積體電路封裝方法 Download PDF

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TWI755485B
TWI755485B TW107105556A TW107105556A TWI755485B TW I755485 B TWI755485 B TW I755485B TW 107105556 A TW107105556 A TW 107105556A TW 107105556 A TW107105556 A TW 107105556A TW I755485 B TWI755485 B TW I755485B
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semiconductor die
integrated circuit
bottom semiconductor
electrically connected
backside
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TW107105556A
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TW201842639A (zh
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尚暉 杜
麥可 A. 斯圖柏
比夫魯茲 塔斯巴斯
斯圖爾特 B. 摩林
蔣鑫
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新加坡商西拉娜亞洲私人有限公司
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

一種半導體封裝包括：一引線框架，該引線框架具有周邊封裝引線及一接地電壓引線；一底部半導體晶粒，該底部半導體晶粒倒裝安裝至該引線框架；及一頂部半導體晶粒。該底部半導體晶粒具有：一第一前側主動層，該第一前側主動層具有電連接至該引線框架之第一前側電接點；一第一背側部分；及一內埋氧化物層，該內埋氧化物層位於該第一前側主動層與該第一背側部分之間。該頂部半導體晶粒安裝至該第一背側部分。該第一前側主動層包括藉由穿過該內埋氧化物層之一背側電連接件而電連接至該第一背側部分之一電路。該底部半導體晶粒之該第一背側部分經由該等第一前側電接點中之一第一電接點電連接至該接地電壓引線，以使串擾減至最小。

Description

用於使串擾減至最小之積體電路封裝設備及積體電路封裝方 法 相關申請案之交叉參考
本申請案主張於2017年12月22日申請且標題為「INTEGRATED CIRCUIT CONNECTION ARRANGEMENT FOR MINIMIZING CROSSTALK」之美國非臨時專利申請案第15/853,357號之優先權；該美國非臨時專利申請案主張於2017年2月20日申請且標題為「Backside Contact Integrated Laterally Diffused MOS Apparatus and Methods」之美國臨時申請案第62/461,117號之權益，所有案出於所有目的以引用之方式併入。
本發明係有關於一種用於使串擾減至最小之積體電路連接配置。
半導體功率裝置為通常用作功率電子電路中之開關或整流器之專用裝置。半導體功率裝置可使用諸如橫向擴散金屬氧化物半導體(LDMOS)電晶體之橫向擴散場效應電晶體(LDFET)來實施。此等類型之電晶體特徵在於與汲極區域之延伸相對應之「橫向擴散」區域(或低摻雜或輕摻雜汲極(LDD)區域)，該汲極區域比核心汲極區域之摻雜度低且自通道橫向延伸。橫向擴散區域藉由吸收原本將會引起源極-汲極穿通的電場之部分來增大LDFET處置關斷狀態中之較高電壓之能力，且藉由防止大電位降在汲極-本體界面上累積來增大LDFET處 置導通狀態中之較大電流的能力，大電位降原本將會由於將熱載體注入至裝置本體內而導致裝置劣化。
切換電壓調節器通常包括兩個半導體功率裝置，該兩個半導體功率裝置以同步方式恆定地接通及關斷以調節電壓。此切換可能產生電氣干擾，對周圍電路造成在某些情況下表現為串擾之負面影響。串擾係由自一個電路至另一電路之不希望的(例如，電感性、電容性或導電)耦接引起之現象。在用於控制功率電子電路之積體電路與功率電子電路本身一起封裝的緊密封裝之半導體封裝中，功率電子電路與控制器電路之間的串擾可能導致不希望之系統表現或行為。
在一些實施例中，一種積體電路(IC)封裝包括：一引線框架，該引線框架具有周邊封裝引線及一接地電壓引線；一底部半導體晶粒；及一頂部半導體晶粒。該底部半導體晶粒倒裝安裝至該引線框架。該底部半導體晶粒包括：i)一第一前側主動層，該第一前側主動層具有電連接至該引線框架之第一前側電接點，ii)一第一背側部分及iii)一內埋氧化物層。該內埋氧化物層位於該第一前側主動層與該第一背側部分之間。該頂部半導體晶粒包括：i)一第二前側，及ii)一第二背側。該頂部半導體晶粒之該第二背側安裝至該底部半導體晶粒之該第一背側部分。該底部半導體晶粒之該第一前側主動層包括藉由穿過該內埋氧化物層之一背側電連接件而電連接至該第一背側部分之一電路。該等第一前側電接點中之一第一電接點電連接至該背側電連接件，且該底部半導體晶粒之該第一背側部分經由該第一電接點電連接至該引線框架之該接地電壓引線，以使串擾減至最小。
在一些實施例中，一種用於將一半導體裝置封裝在一IC封裝中之方法涉及提供具有周邊封裝引線及一接地電壓引線之一引線框架。形成一底部半導體晶粒，該底部半導體晶粒包括：i)具有第一前側電接點之一第一前側主動層， ii)一第一背側部分，及iii)一內埋氧化物層。該內埋氧化物層位於該第一前側主動層與該第一背側部分之間。將該底部半導體晶粒倒裝安裝至該引線框架。該倒裝安裝包括將該底部半導體晶粒之該等第一前側電接點電連接且實體安裝至該引線框架，該等第一前側電接點中之一第一電接點電連接且實體安裝至該引線框架之該接地電壓引線。提供一頂部半導體晶粒。該頂部半導體晶粒包括：i)具有第二前側電接點之一第二前側，及ii)一第二背側。將該頂部半導體晶粒安裝至該底部半導體晶粒，該頂部半導體晶粒之該第二背側附接至該底部半導體晶粒之該第一背側部分。該底部半導體晶粒之該第一前側主動層包括一電路，該電路藉由各別第一前側電連接件電連接至該等第一前側電接點且藉由穿過該內埋氧化物化層之一第一背側連接件電連接至該第一背側部分。該底部半導體晶粒之該第一背側部分經由該第一背側連接件及該等第一前側電接點中之該第一電接點電連接至該引線框架之該接地電壓引線，以使串擾減至最小。
10:高功率半導體開關電路
12:高側場效應電晶體(FET)
14:低側FET
16:相位節點
18:高側閘極節點
20:低側閘極節點
23:電壓輸入節點
32、34:橫向擴散場效應電晶體(LDFET)
42:前側主動層
44:內埋氧化物層
45:基板
46、46’:源極區域
47:介電隔離障壁
48、48’、51、51’:摻雜區域
49、49’:延伸區域
50、50’:LDD區域
52、52’:汲極區域
54、54’:源極接點
56、56’:汲極接點
60、60’:本體區域
62、62’:深井區域
66、66’:閘極屏蔽物
68、68’:閘電極
70、70’、72、72’:介電材料
74:絕緣材料
200:積體電路(IC)封裝
215:安裝介質
220:引線框架
222:頂部半導體晶粒
223a:前側
223b:背側
224:頂部電接點
230:底部半導體晶粒
231a:背側部分
231b:前側
233a-b:切割線
275a、275b、275c:電連接器
280:第一前側電接點
282:第二前側電接點
284:第三前側電接點
286:第四前側電接點
291a-h:周邊封裝引線
292a-d:結合線
300:積體電路(IC)封裝
圖1為併有一些實施例之高功率半導體開關之示例之電路圖。
圖2A為根據一些實施例之積體電路封裝之簡化圖解頂部正視圖。
圖2B為根據一些實施例之積體電路封裝之簡化圖解橫截面。
圖2C為根據一些實施例之積體電路封裝之簡化圖解橫截面。
圖3為根據一些實施例之積體電路封裝之簡化圖解橫截面。
在以下描述中，相同附圖標記用於識別相同之元件。此外，附圖旨在以圖解方式說明示例性實施例之主要特徵。附圖不旨在描繪實際實施例之每個特徵或所描繪之元件之相對尺寸，且並非按比例繪製。
本文描述之一些實施例提供一種半導體裝置，其包括安裝在底部半導體晶粒之頂部上之頂部半導體晶粒。該底部半導體晶粒倒裝安裝至半導體裝 置封裝之引線框架上，使得底部半導體晶粒之背側部分朝上，且底部半導體晶粒之前側部分朝下。
底部半導體晶粒之背側部分包括半導體基板，諸如處置晶圓。底部半導體之背側部分經由底部半導體晶粒之前側部分之電接點電連接至引線框架之接地引線。在一些實施例中，此電連接包括穿過底部半導體之內埋絕緣體層之導電路徑。因此接地的底部半導體之背側部分有利地形成位於頂部半導體晶粒下方及底部半導體晶粒之前側主動層上方之接地平面。此接地平面之存在有利地使頂部半導體晶粒與底部半導體晶粒之間的串擾減至最小。
在一些實施例中，頂部半導體晶粒為向在底部半導體晶粒中形成之電路節點(例如，電晶體之閘極節點)提供控制信號之控制器晶粒。在一些實施例中，底部半導體晶粒包括整合式橫向擴散場效應電晶體(LDFET)電路。此LDFET電路包括與底部半導體晶粒之背側部分之至少一個基板接點，以減少所需之前側電連接件之數目。以此方式，可用於容納相對較大之高效能電連接件(例如引線框架之電連接器，諸如能夠傳導高電流之金屬條帶)之底部半導體晶粒之前側空間增大。此又增大了整合式LDFET功率裝置電路之電路設計靈主動、效能及可製造性。在一些實施例中，具有基板接點之LDFET與同一電路中之其他LDFET電隔離，以藉由防止在連接至基板之LDFET與不連接之LDFET之間形成公共節點而進一步改良電路之效能。
僅出於說明之目的，本發明描述在類似於圖1中所展示之示例性高功率半導體開關電路10之實施例之背景下的單半導體晶粒整合式LDFET電路之具體示例。可使用相同或類似之教示來製造適用於功率及非功率應用之其他單半導體晶粒整合式LDFET電路。
高功率半導體開關電路10包括高側場效應電晶體(FET)12及低側FET 14。高側FET 12之高側源極在相位節點16(VPHASE)處耦接至低側FET 14之 低側汲極。高側閘極節點18及低側閘極節點20控制高側FET 12及低側FET 14之工作循環，以將高側FET 12之高側汲極處的電壓輸入節點23處之輸入電壓(VIN)轉換為相位節點16之輸出電壓(VPHASE)。通常，FET 12、14可使用各種各樣之半導體材料系統及技術中之任一種製造，包括矽、鍺及化合物半導體技術。
圖2A展示根據一些實施例之積體電路(IC)封裝200之一部分之簡化示例之頂部正視圖，該封裝通常包括引線框架220、頂部半導體晶粒222及底部半導體晶粒230。IC封裝200通常亦包括結合線292a-d。
通常，引線框架220包括電連接器275a-c及周邊封裝引線291a-h。圖2A或本文之任一圖中展示之電連接器及/或周邊封裝引線之數目展示為簡化示例。在一些實施例中，可使用更多或更少之電連接器及/或周邊封裝引線。稍後參考圖2B至圖2C論述橫截面切割線233a-b。
在所展示之示例中，底部半導體晶粒230體現了整合式負載點(POL)電壓轉換器，該電壓轉換器體現了圖1所示之高功率半導體開關電路10之示例性實施。然而，底部半導體晶粒230之半導體裝置可為此項技術中已知之另一半導體裝置。在所示之示例中，底部半導體晶粒230通常包括背側部分231a(例如處置晶圓)及與背側部分相對之前側(圖2B中所示之231b)。
頂部半導體晶粒222通常包括在前側223a上之頂部電接點224及與前側223a相對之背側部分(例如，諸如處置晶圓之基板)(圖2B中所示之223b)。在一些實施例中，頂部半導體晶粒222為以下各項中的一者：(i)控制器晶粒，(ii)塊體半導體晶粒，(iii)微處理器，(iv)微控制器，(v)數位信號處理器或(vi)如此項技術中已知之另一種半導體。在本文描述之示例性實施例中，頂部半導體晶粒222為用於功率開關電路之控制器晶粒。在此情況下，頂部半導體222經組態以同步底部半導體晶粒230之POL電壓轉換器之電晶體的相應開/關狀態。
如圖所示，與前側223a相對之頂部半導體晶粒222之背側實體安裝至底部半導體晶粒230之背側部分231a。與背側部分231a相對之底部半導體晶粒230之前側的相應電接點(在圖2B及圖2C中展示)電耦接至且實體安裝至引線框架之電連接器275a-c。底部半導體晶粒230之背側部分231a有利地形成接地平面，頂部半導體晶粒222安裝在該接地平面上，由此減小頂部半導體晶粒222與底部半導體晶粒230之間的串擾。
頂部半導體晶粒222之一或多個導電接點224電耦接至周邊封裝引線291a-h中之一或多者、引線框架220及/或底部半導體晶粒230以接收或發送用於控制底部半導體晶粒230中之高功率半導體開關電路之電子組件(例如，電晶體)之信號、命令及/或回饋。作為示例，頂部半導體晶粒222之頂部電接點224中的若干接點藉由結合線292a-b電連接至周邊封裝引線291a-b，且藉由結合線292c-d電連接至電連接器275b-c。
圖2B展示根據一些實施例之包括用於圖2A中引入之半導體裝置之引線框架220之簡化示例性積體電路(IC)封裝200之一部分之圖解橫截面圖。IC封裝200之橫截面圖為穿過圖2A之IC封裝200之一部分截取之橫截面，如圖2A之切割線233a所指示。
圖2B之IC封裝200包括圖2A中引入之元件，以及安裝介質215、頂部半導體晶粒222之背側223b及底部半導體晶粒230之前側231b。
如圖所示，結合線292a將周邊封裝引線291a電耦接至頂部半導體晶粒222之頂部電接點224之前側電接點。頂部半導體晶粒222之背側223b藉由安裝介質215實體安裝至底部半導體晶粒230之背側部分231a。在一些實施例中，安裝介質215包括附著黏合劑、燒結銀、焊膏、導熱黏合劑或適合於形成實體、熱島及/或電連接之任何物質。在一些實施例中，安裝介質215為電絕緣 材料。在一些實施例中，一或多個其他介入層(例如，金屬層或絕緣層)位於頂部半導體晶粒222與底部半導體晶粒230之間。
在一些實施例中，底部半導體晶粒230之前側電接點包括銅柱或焊料凸塊。底部半導體晶粒230之第一前側電接點280電連接且實體安裝至電連接器275a，底部半導體晶粒230之第二前側電接點282電連接且實體安裝至電連接器275b，且底部半導體晶粒230之第三前側電接點284電連接且實體安裝至電連接器275c(例如，各自藉由晶粒附著黏合劑或其他合適之安裝技術)。
在一些實施例中，底部半導體晶粒230之第一前側電接點280、第二前側電接點282及第三前側電接點284通常表示底部半導體晶粒230之多個金屬層中之頂部金屬層。底部半導體晶粒230被倒置或成倒裝組態，因此底部半導體晶粒230之「頂部」/「前側」及「底部」/「背側」分別展示在圖中之底部及頂部。為簡單起見，省略了一些金屬層、連接件、結合線或其他特徵。可存在介入金屬層、導電黏合劑、銅柱、焊料凸塊或其他金屬黏合結構。
在一些實施例中，在底部半導體晶粒230、引線框架220及/或頂部半導體晶粒222之間形成至少五個電連接件。在圖1中，此等五個電連接件包括至電壓輸入節點23(VIN)之電連接件、至相位節點16(VPHASE)之電連接件、低側FET 14之低側源極至接地節點之電連接件、至高側閘極節點18之電連接件及至低側閘極節點20之電連接件。
在一些實施例中，頂部半導體晶粒222之背側223b上之背側電接點(未展示)電耦接至底部半導體晶粒230之背側部分231a。在安裝介質215導電之一些實施例中，安裝介質215用於此電耦接。在安裝介質215電絕緣之其他實施例中，頂部半導體晶粒222之背側223b藉由安裝介質215與底部半導體晶粒230之背側部分231a基本上電隔離。在任一實施例中，底部半導體晶粒230之背側 部分231a有利地提供接地平面，用於使頂部半導體晶粒222與底部半導體晶粒230之間的串擾減至最小。
圖2C展示根據一些實施例之包括用於半導體裝置之引線框架220之簡化示例性積體電路(IC)封裝200之一部分之圖解橫截面圖。圖2C所示之IC封裝200之橫截面圖為穿過圖2A之IC封裝200之一部分截取之橫截面，如圖2A之切割線233b所指示。
圖2C之IC封裝200可包括圖2A至圖2B中引入之元件以及底部半導體晶粒230之第四前側電接點286。在一些實施例中，第四前側電接點286電耦接至底部半導體晶粒230之電晶體之閘極接點。如圖所示，第四前側電接點286電耦接至且實體安裝至在底部半導體晶粒230下方延伸之周邊封裝引線291b。雖然第四前側電接點286展示為實體安裝至周邊封裝引線291b，但在其他實施例中，第四前側電接點286電耦接至周邊封裝引線291b(例如，藉由結合線)，但並不實體安裝至周邊封裝引線291b。
在所示之實施例中，結合線292b將周邊封裝引線291b電耦接至頂部半導體晶粒222之頂部電接點224之前側電接點，且由此將第四前側電接點286電耦接至頂部半導體晶粒222之前側電接點。
在一些實施例中，第四前側電接點286通常表示底部半導體晶粒230之多個金屬層中之頂部金屬層。為了簡單起見，省略了一些金屬層、連接件、結合線或其他特徵。可存在介入金屬層、導電黏合劑、銅柱、焊料凸塊或其他金屬黏合結構。
圖3展示根據一些實施例之積體電路(IC)封裝300之一部分之簡化圖解橫截面側視圖，其包括在圖2A至圖2C中引入之元件，包括引線框架220。為了簡單起見，在前圖中展示之引線框架220之部分已被省略。舉例而言，圖3中已省略圖2A之周邊封裝引線291a-h，儘管其為引線框架220之一部分。
在所示之簡化示例性實施例中，半導體晶粒230為功率半導體晶粒，體現圖1之高功率半導體開關電路10。在此示例中，LDFET 32實施開關電路10之高側FET 12，且LDFET 34實施開關電路10之低側FET 14。在一個示例性組態中，高側LDFET 32之第一前側電接點280對應於開關電路10之電壓輸入節點23，第二前側電接點282對應於開關電路10之相位節點16，且電連接至第三前側電接點284之基板45(例如，處置晶圓)對應於開關電路10之接地節點。
LDFET 32之汲極區域52電耦接至連接至第一前側電接點280之汲極接點56。LDFET 32之源極區域46電耦接至源極接點54，該源極接點電連接至第二前側電接點282。LDFET 34之汲極區域52'電耦接至電連接至第二前側電接點282之汲極接點56'。LDFET 34之源極區域46'電耦接至電連接至第三前側電接點284之源極接點54，。因此，底部半導體晶粒230之基板45經由源極接點54'電耦接至第三前側電接點284。
第三前側電接點284又電連接至電連接器275c，該電連接器為引線框架220之接地電壓引線。藉由將基板45耦接至接地，在頂部半導體晶粒222與底部半導體晶粒230之間形成接地平面，此係由於基板45插入在大部分(若非全部)頂部半導體晶粒222與底部半導體晶粒230之其餘層之間，由此使得頂部半導體晶粒222與底部半導體晶粒230之間的串擾減至最小。
在一些實施例中，頂部半導體晶粒222之前側電接點(例如，圖2A中所示之電接點224)經由線結合及/或或引線框架220而電耦接至LDFET 32及/或LDFET 34之閘極節點。此組態使得頂部半導體晶粒222能夠控制高側LDFET 32及低側LDFET 34之開/關狀態。在一些實施例中，高側LDFET 32為p型電晶體，而低側LDFET 34為n型電晶體。在其他實施例中，LDFET 32、34兩者皆為n型電晶體。在一些實施例中，LDFET 32、34兩者同時切換，或與兩個閘 極接點分開地切換，或使用單個閘極接點一起切換(例如，其中高側LDFET 32之閘極及低側LDFET 34之閘極電耦接至單個閘極接觸)。
在圖3所示之高功率半導體開關電路10之示例性實施中，高側LDFET 32之汲極接點56連接至電壓輸入節點23(參考圖1)，高側LDFET 32之源極接點54及低側LDFET 34之汲極接點56'皆連接至相位節點16(參考圖1)，且低側LDFET 34之源接點54'連接至接地節點(參考圖1)。如上所述，其他節點連接配置係可能的。舉例而言，此等其他連接配置包括第一LDFET與第二LDFET之間的任何連接配置，其包括(i)公共節點電連接至第一LDFET之源極及第二LDFET之汲極，(ii)第一LDFET之汲極、第二LDFET之源極及公共節點中之至少一者電連接至半導體基板，及(iii)至少兩個前側電接點連接至第一LDFET之汲極、第二LDFET之源極及並未電連接至半導體基板之公共節點中的至少兩者。
高側及低側LDFET 32、34在底部半導體晶粒230之前側主動層42中實施。基板45在底部半導體晶粒230之背側部分231a中。前側主動層42可為半導體晶圓塊體之摻雜部分、形成在半導體晶圓之較大摻雜部分中之局部化井、絕緣體上半導體(SOI)晶圓之主動層及形成在SOI晶圓中的局部化井中之任一者。在所說明之示例中，前側主動層42為在基板45(例如，SOI基板)上之內埋氧化物層44上形成之薄膜。在所說明之示例中，介電隔離障壁47在高側與低側LDFET 32、34之間自前側主動層42之頂部延伸至內埋氧化物層44。在一些示例中，使用淺溝槽隔離(STI)製程形成介電隔離障壁47。
高側LDFET 32包括在摻雜區域48中形成之源極區域46、在摻雜區域51中形成之具有較重摻雜延伸區域49之輕摻雜汲極(LDD)區域50，及汲極區域52。源極區域46、摻雜區域48、LDD區域50、延伸區域49及汲極區域52可包括藉由例如將雜質植入前側主動層42中而形成之摻雜半導體材料。每個區 域46及48至52之摻雜半導體材料具有類似之導電類型(例如，n型或p型)。因此，每個區域46及48至52可由相同之摻雜劑物質形成，諸如藉由植入一種摻雜劑原子。LDD區域50具有比汲極區域52低之摻雜劑濃度，且亦可具有比源極區域46低之摻雜劑濃度。LDD區域50就其耐受大電壓且在接收大電流時不劣化的能力方面為LDFET提供極佳效能以作為功率發裝置。LDD區域50之存在為LDFET提供了具有不對稱源極與汲極區域之特性。在一些方法中，隨著摻雜區域48自源極區域46延伸，LDD區域50通常橫向延伸至少兩倍於汲極區域52之距離。
高側LDFET 32亦包括具有與區域46及48至52之導電類型相反之導電類型的本體區域60及深井區域62。深井區域62在源極區域46及本體區域60之形成有通道之部分下方橫向延伸。深井區域62增強高側LDFET 32承受大電壓之能力，且用於自本體區域60移除不需要之電荷載流子，以防止寄生雙極接面電晶體在高側LDFET 32之導通狀態期間啟動。
在前側主動層42上方，高側LDFET 32包括閘極結構，其包括閘極屏蔽物66及閘電極68。閘電極68分別藉由介電材料70、72與前側主動層42及閘極屏蔽物66電絕緣。
汲極區域52可為高度摻雜之汲極區域，且可在汲極接點56與LDD區域50之間形成導電路徑。電絕緣材料74(例如層間介電質)電隔離，且防止前側主動層42上的電組件之意外耦接。通常，電絕緣材料74與介電材料70、72可為相同或類似之材料。另外，在某些方法中，絕緣材料74與介電材料70、72之組合可被概念化為成品裝置中之單個絕緣層，而不管其何時及如何形成。
回應於將電壓施加至閘電極68(例如，藉由頂部半導體晶粒222)，在源極接點54與汲極接點56之間形成導電路徑。在源極接觸54與汲極接觸56之間的導電路徑包括在施加至閘電極68之上述電壓之影響下在本體區域60中 選擇性地形成之通道。在形成通道之同時，可稱電晶體接通。在未形成通道，且在源極接點54與汲極接點56之間無導電路徑時，可稱電晶體關斷。在此情況下無導電路徑，此係因為源極區域46及汲極區域50、52具有與本體區域60相反之導電類型，使得在其界面處形成二極體接面。
閘極屏蔽物66與源極接點54歐姆接觸。閘極屏蔽物66為使得高側FET 32更適合高功率應用之另一特徵。藉由將閘極屏蔽物66加偏壓至給定電壓，汲極接點56上之高功率信號被屏蔽，從而不會對閘極區域產生明顯影響。雖然閘極屏蔽66被說明為歐姆地耦接至源極接點54，但閘極屏蔽物66亦可被獨立地加偏壓。在一些示例中，閘極屏蔽物66與源極接點54可以兩個不同之步驟形成，且可包括兩種不同類型之材料。然而，在此情況下，此等特徵對裝置之操作係無關緊要的，因為閘極屏蔽物66及源極接點54為高導電材料之一個連續區域，始終具有自絕緣材料74上方至前側主動層42之表面之不間斷歐姆接觸。因此，閘極屏蔽物66與源極接點54之組合可被概念化為單個源極接點。
通常，源極接點54及汲極接點56實現自在同一積體電路上可或可不與LDFET整合之其他電路至高側LDFET 32之電連接。源極區域46可經由形成在源極區域46之表面上的矽化物層電耦接至源極接點54。更一般地，源極區域46可使用在結構之兩個區域之間任何形成歐姆或非整流接觸的任何製程耦接至源極接點54。汲極接點56與汲極區域52之間的連接可包括上面參考源極接點54及源極區域46所描述之任何變型。源極接點54及汲極接點56可包括金屬、金屬合金、金屬矽化物或諸如摻雜多晶矽之導電半導體材料。示例性金屬、金屬合金及金屬矽化物可各自包括銅、鎢、鉬及鋁。
在圖3所示之示例中，前側主動層42之低側LDFET 34之一些元件以與前側主動層42之高側LDFET 32之對應元件類似之方式起作用。就此而言，低側LDFET 34之功能上類似之元件被標記有高側LDFET 32之對應元件之附圖 標記，後面跟有撇號。舉例而言，對應於高側LDFET 32之功能上類似之汲極區域52之低側LDFET 34之汲極區域以附圖標記52'標記。因此，低側LDFET 34包括以下元件：在摻雜區域51'中形成之具有較重摻雜延伸區域49'之源極區域46'、摻雜區域48'、LDD區域50'，汲極區域52'，源極接點54'，汲極接點56'，本體區域60'，深井區域62'，閘極屏蔽物66'，閘電極68'及介電材料70'、72'。
在此示例中，低側LDFET 34之源極接點54'不僅自前側主動層42上方延伸，穿過源極區域46'及摻雜區域48'延伸至深井區62'，而且其亦延伸穿過深井區域62'及內埋氧化物層44且進入基板45。以此方式，低側LDFET 34之源極接點54'提供至基板45且由此至對應於用於高功率半導體開關電路10之接地節點的基板45之源極關斷電連接。
第二前側電接點282(相位節點)將高側LDFET 32之源極接點54與低側LDFET 34之汲極接點56'電互連，從而形成高側LDFET 32之源極區域46及低側LDFET 34之汲極區域52'之公共節點。注意，內埋氧化物層44及介電隔離障壁47將高側LDFET 32與基板45電隔離以防止在功率開關電路10之操作期間與低側LDFET 34之源極接點54'形成公共節點。
半導體晶粒230安裝在IC封裝300之引線框架220之部分上及內部。如圖所示，底部半導體晶粒230之第一前側電接點280電耦接至且實體安裝至電連接器275a(引線框架220之輸入電壓節點引線)，第二前側電接點282電耦接至且實體安裝至電連接器275b(引線框架220之相位節點引線)，且第三前側電接點284電耦接至且實體安裝至電連接器275c(引線框架220之接地電壓引線)。
頂部半導體晶粒222與底部半導體晶粒230之間的額外電連接件，類似於圖2A至圖2C所示之電連接件，經形成但在圖3中為簡單起見而省略。
頂部半導體晶粒222之背側223b實體安裝至底部半導體晶粒230之背側部分231a。包括基板45之背側部分231a耦接至引線框架220之電連接器275c(接地電壓引線)。這有利地在頂部半導體晶粒222與底部半導體晶粒230之間形成接地平面，以使此等晶粒之間的串擾減至最小。
圖3中所示之金屬層(例如，第一前側電接點280)通常表示根據需要對連接件進行佈線之多個金屬層，包括用於半導體晶粒焊墊之頂部金屬層及半導體晶粒焊墊與前側主動層42之絕緣材料(例如，74)之間的額外金屬層。一些金屬層、連接件、結合線或其他特徵為簡單起見被省略。可存在介入金屬層、導電黏合劑、銅柱、焊料凸塊或其他金屬黏合結構。
為簡單起見，簡化之圖解橫截面側視圖僅展示單個電晶體「指形件」。在一些實施例中，多個電晶體指形件並聯連接以增大所體現之電路之功率處置能力且通過應用所體現之電路而根據需要降低總電阻。
已經詳細參考了所公開之本發明之實施例，其一或多個示例已經在附圖中展示。已經藉由解釋本技術而非作為對本技術之限制來提供每個示例。實際上，雖然已經參考本發明之具體實施例詳細描述了說明書，但應認識到，熟習此項技術者在獲得對前述內容之理解之後可容易地想到對本發明之改變、變化及此等實施例之等效物。舉例而言，作為一個實施例之一部分而說明或描述之特徵可與另一實施例一起使用以產生又一個實施例。因此，希望本發明之主題涵蓋所附申請專利範圍及其等效物之範圍內之所有此等修改及變化。在不脫離本發明之範圍之情況下，熟習此項技術者可實踐本發明之此等及其他修改及變化，本發明之範圍在所附申請專利範圍中更具體地闡述。此外，熟習此項技術者將理解，前文之描述僅僅係作為示例，且不意欲限制本發明。
32、34:橫向擴散場效應電晶體(LDFET)
42:前側主動層
44:內埋氧化物層
45:基板
46、46’:源極區域
47:介電隔離障壁
48、48’、51、51’:摻雜區域
49、49’:延伸區域
50、50’:LDD區域
52、52’:汲極區域
54、54’:源極接點
56、56’:汲極接點
60、60’:本體區域
62、62’:深井區域
66、66’:閘極屏蔽物
68、68’:閘電極
70、70’、72、72’:介電材料
74:絕緣材料
215:安裝介質
220:引線框架
222:頂部半導體晶粒
223a:前側
223b:背側
230:底部半導體晶粒
231a:背側部分
275a、275b、275c:電連接器
280:第一前側電接點
282:第二前側電接點
284:第三前側電接點
300:積體電路(IC)封裝

Claims (20)

  1. 一種積體電路封裝設備，該設備包括：一引線框架，該引線框架具有周邊封裝引線及一接地電壓引線；一底部半導體晶粒，該底部半導體晶粒倒裝安裝至該引線框架，該底部半導體晶粒包括：i)一第一前側主動層，該第一前側主動層具有電連接至該引線框架之第一前側電接點，ii)一第一背側部分及iii)一內埋氧化物層，該內埋氧化物層位於該第一前側主動層與該第一背側部分之間；及一頂部半導體晶粒，該頂部半導體晶粒包括：i)一第二前側，及ii)一第二背側，該頂部半導體晶粒之該第二背側安裝至該底部半導體晶粒之該第一背側部分；其中：該底部半導體晶粒之該第一前側主動層包括藉由穿過該內埋氧化物層之一背側電連接件而電連接至該第一背側部分之一電路；該等第一前側電接點中之一第一電接點電連接至該背側電連接件；且該底部半導體晶粒之該第一背側部分經由該第一電接點電連接至該引線框架之該接地電壓引線，以使串擾減至最小。
  2. 如請求項1之積體電路封裝設備，其中：該底部半導體晶粒為一功率半導體晶粒。
  3. 如請求項1之積體電路封裝設備，其中：該頂部半導體晶粒之該第二前側之一電接點電耦接至該等周邊封裝引線中之第一組。
  4. 如請求項3之積體電路封裝設備，其中：該頂部半導體晶粒為一控制器晶粒。
  5. 如請求項1之積體電路封裝設備，其中： 該底部半導體晶粒之該電路包括兩個或更多個電晶體；該兩個或更多個電晶體中之至少一個電連接至該底部半導體晶粒之該等第一前側電接點；且該兩個或更多個電晶體中之至少一個電連接至該底部半導體晶粒之該第一背側部分。
  6. 如請求項5之積體電路封裝設備，其中：該兩個或更多個電晶體包括一高側電晶體及一低側電晶體；該高側電晶體包括一高側源極、一高側汲極及一高側閘極；該低側電晶體包括一低側源極、一低側汲極及一低側閘極；且該底部半導體晶粒之該第一背側部分經由該內埋氧化物層電連接至該低側源極。
  7. 如請求項6之積體電路封裝設備，其中：該頂部半導體晶粒之該第二前側之一電接點電連接至該高側閘極或該低側閘極中之一者或兩者。
  8. 如請求項7之積體電路封裝設備，其中：該頂部半導體晶粒之該第二前側之該電接點經由該引線框架之一周邊封裝引線電連接至該高側閘極或該低側閘極中之該一者或兩者。
  9. 如請求項6之積體電路封裝設備，其中：該底部半導體晶粒之該等第一前側電接點中之該第一電接點電連接至該低側源極。
  10. 如請求項9之積體電路封裝設備，其中：該底部半導體晶粒之該等第一前側電接點中之一第二電接點將該低側汲極電耦接至該高側源極；且該第二電接點電耦接且實體安裝至該引線框架之一相位節點引線。
  11. 如請求項10之積體電路封裝設備，其中：該底部半導體晶粒之該等第一前側電接點中之一第三電接點電耦接至該高側汲極；且該第三電接點電耦接且實體安裝至該引線框架之一輸入電壓節點引線。
  12. 一種積體電路封裝方法，該方法包括：提供具有周邊封裝引線及一接地電壓引線之一引線框架；形成一底部半導體晶粒，該底部半導體晶粒包括：i)具有第一前側電接點之一第一前側主動層，ii)一第一背側部分，及iii)一內埋氧化物層，該內埋氧化物層位於該第一前側主動層與該第一背側部分之間；將該底部半導體晶粒倒裝安裝至該引線框架，該倒裝安裝包括將該底部半導體晶粒之該等第一前側電接點電連接且實體安裝至該引線框架，該等第一前側電接點中之一第一電接點電連接且實體安裝至該引線框架之該接地電壓引線；提供一頂部半導體晶粒，該頂部半導體晶粒包括：i)具有第二前側電接點之一第二前側，及ii)一第二背側；及將該頂部半導體晶粒安裝至該底部半導體晶粒，該頂部半導體晶粒之該第二背側附接至該底部半導體晶粒之該第一背側部分；其中：該底部半導體晶粒之該第一前側主動層包括一電路，該電路藉由各別第一前側電連接件電連接至該等第一前側電接點且藉由穿過該內埋氧化物化層之一第一背側連接件電連接至該第一背側部分；且該底部半導體晶粒之該第一背側部分經由該第一背側連接件及該等第一前側電接點中之該第一電接點電連接至該引線框架之該接地電壓引線，以使串擾減至最小。
  13. 如請求項12之積體電路封裝方法，其中：該頂部半導體晶粒之該等第二前側電接點中之一電接點電耦接至該等周邊封裝引線中之第一組。
  14. 如請求項12之積體電路封裝方法，其中：該底部半導體晶粒包括兩個或更多個電晶體；該兩個或更多個電晶體中之至少一個電連接至該底部半導體晶粒之該等第一前側電接點；且該兩個或更多個電晶體中之至少一個電連接至該底部半導體晶粒之該第一背側部分。
  15. 如請求項14之積體電路封裝方法，其中：該兩個或更多個電晶體包括一高側電晶體及一低側電晶體；該高側電晶體包括一高側源極、一高側汲極及一高側閘極；該低側電晶體包括一低側源極、一低側汲極及一低側閘極；且該底部半導體晶粒之該第一背側部分經由該內埋氧化物層電連接至該低側源極。
  16. 如請求項15之積體電路封裝方法，其中：該頂部半導體晶粒之該等第二前側電接點中之一頂部電接點電連接至該高側閘極或該低側閘極中之一者或兩者。
  17. 如請求項16之積體電路封裝方法，其中：該頂部電接點經由該引線框架之一周邊封裝引線電連接至該高側閘極或該低側閘極中之該一者或兩者。
  18. 如請求項15之積體電路封裝方法，其中：該底部半導體晶粒之該等第一前側電接點中之該第一電接點電連接至該低側源極。
  19. 如請求項18之積體電路封裝方法，其中：該底部半導體晶粒之該等第一前側電接點中之一第二電接點將該低側汲極電耦接至該高側源極；且該第二電接點電耦接且實體安裝至該引線框架之一相位節點引線。
  20. 如請求項19之積體電路封裝方法，其中：該底部半導體晶粒之該等第一前側電接點中之一第三電接點電耦接至該高側汲極；且該第三電接點電耦接且實體安裝至該引線框架之一輸入電壓節點引線。
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