TW201643996A - 堆疊封裝構件及其製作方法 - Google Patents

堆疊封裝構件及其製作方法 Download PDF

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TW201643996A
TW201643996A TW104122464A TW104122464A TW201643996A TW 201643996 A TW201643996 A TW 201643996A TW 104122464 A TW104122464 A TW 104122464A TW 104122464 A TW104122464 A TW 104122464A TW 201643996 A TW201643996 A TW 201643996A
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wafer
package
tsv
layer
bumps
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TW104122464A
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TWI616980B (zh
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施信益
施能泰
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華亞科技股份有限公司
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Abstract

一種PoP堆疊封裝構件，包含有一底部晶片封裝以及一上部晶片封裝，疊設於該底部晶片封裝上。底部晶片封裝包含一中介層，具有一第一面以及一相對第一面的第二面；至少一主動晶片，經由複數個第一凸塊安裝在第一面，且位於一晶片接合區域內；至少一矽穿通孔(TSV)晶片，安裝在第一面，位於晶片接合區域旁的一周邊區域內，其中TSV晶片包含至少一TSV連接結構，經由周邊區域內的複數個第二凸塊安置在第一面上；一成型模料，設於第一面，覆蓋主動晶片及TSV晶片；以及複數個焊接錫球，設於第二面。

Description

堆疊封裝構件及其製作方法
本發明係有關於半導體封裝技術領域，特別是有關於一種封裝上封裝(Package-on-Package, PoP)堆疊封裝構件及其製作方法。
隨著半導體製造技術的進步，微電子元件變得更小，元件內部的電路變得越來越密集。為了減少微電子元件的尺寸，這些微電子元件的封裝構件結構必須變得更加緊密。為了滿足在更小的空間達到更高密度的要求，業界於是發展出3D堆疊封裝，例如，PoP堆疊封裝。
PoP堆疊封裝構件通常包括一個頂部封裝，其內有一晶片，與具有另一晶片的底部封裝接合。在PoP堆疊封裝構件的設計中，頂部封裝可以通過外圍焊球互連到底部封裝。然而，現有技術的PoP堆疊封裝構件無法提供非常緊密間距的堆疊。此外，現有技術的PoP堆疊封裝構件外形較大且翹曲控制不良。
晶圓級封裝製程中，通常會在晶圓及安裝在晶圓上的晶片表面覆蓋一相對較厚的成型模料。此成型模料與積體電路基底的熱膨脹係數(CTE)差異，易導致封裝翹曲變形，也使得封裝整體的厚度增加。晶圓翹曲一直是該領域關注的問題。晶圓翹曲使晶片與晶圓間的接合不易維持，易造成“晶片對晶圓接合”(chip to wafer)的組裝失敗。翹曲問題在大尺寸晶圓上更是明顯，特別是對於具有小間距重佈線層的晶圓級半導體封裝製，問題更為嚴重。
本發明主要目的在提供一具有堆疊封裝組態的半導體裝置，以解決上述先前技藝的不足與缺點。
本發明一實施例提供一種PoP堆疊封裝構件，包含有一底部晶片封裝以及一上部晶片封裝，疊設於該底部晶片封裝上。該底部晶片封裝包含一中介層，具有一第一面以及一相對該第一面的第二面；至少一主動晶片，經由複數個第一凸塊安裝在該第一面，且位於一晶片接合區域內；至少一矽穿通孔(TSV)晶片，安裝在該第一面，位於該晶片接合區域旁的一周邊區域內，其中該TSV晶片包含至少一TSV連接結構，經由該周邊區域內的複數個第二凸塊安置在該第一面上；一成型模料，設於該第一面，覆蓋該主動晶片以及該TSV晶片；以及複數個焊接錫球，設於該第二面。
根據本發明一實施例，該上部晶片封裝經由複數個設於該TSV晶片上的第三凸塊安裝在該底部晶片封裝上。
本發明另一實施例提供一種PoP堆疊封裝構件，包含有一底部晶片封裝以及一上部晶片封裝，疊設於該底部晶片封裝上。該底部晶片封裝包含一中介層，具有一第一面以及一相對該第一面的第二面；至少一主動晶片，經由複數個第一凸塊安裝在該第一面，且位於一晶片接合區域內；至少一虛設晶片，安裝在該第一面，位於該晶片接合區域旁的一周邊區域內，該虛設晶片直接設於該中介層的一鈍化層上；一介電層，覆蓋該主動晶片以及該虛設晶片；至少一穿矽通孔(TSV)連接結構，貫穿該介電層與該虛設晶片；一成型模料，設於該第一面，覆蓋該主動晶片以及該虛設晶片；以及複數個焊接錫球，設於該第二面。
無庸置疑的，該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後，均可了解本發明的目的。
接下來的詳細敘述須參照相關圖式所示內容，用來說明可依據本發明具體實行的實施例。這些實施例提供足夠的細節，可使此領域中的技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，可做結構、邏輯和電性上的修改應用在其他實施例上。
因此，接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求界定。與本發明權利要求具同等意義者，也應屬本發明涵蓋的範圍。本發明實施例所參照的附圖為示意圖，並未按比例繪製，且相同或類似的特徵通常以相同的附圖標記描述。在本說明書中，“晶粒”、“半導體晶片”與“半導體晶粒”具相同含意，可交替使用。
在本說明書中，“晶圓”與“基板”意指任何包含一暴露面，可依據本發明實施例所示在其上沉積材料，製作積體電路結構的結構物，例如重佈線層(RDL)。須了解的是“基板”包含半導體晶圓，但並不限於此。“基板”在製程中也意指包含製作於其上的材料層的半導體結構物。
請參照第1圖至第9圖。第1圖至第9圖為根據本發明一實施例的示意性剖面圖，例示製作PoP堆疊封裝構件的方法。
如第1圖所示，提供一載板300，可以是一可撕除的基板材料。載板300還可包括一黏著層(圖未示)，但不限於此。在載板300的上表面，可以形成至少一介電層或者鈍化層310。鈍化層310可以包含有機材料，例如，聚亞醯胺(polyimide, PI)，或無機材料，例如氮化矽、氧化矽或類似的材料。
如第2圖所示，接著，在鈍化層310上形成一重佈線層(RDL)410。重佈線層410可以包含至少一介電層412以及至少一金屬層414。上述介電層412可以包含有機材料，例如聚亞醯胺(polyimide, PI)，或無機材料，例如氮化矽、氧化矽或類似的材料，但不限於此。金屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似的材料。
根據所述實施例，金屬層414可包含複數個第一凸塊墊415a及第二凸塊墊415b，自介電層412的頂面暴露出來。第一凸塊墊415a設置於一晶片接合區域102內，而第二凸塊墊415b設置於晶片接合區域102外，例如設置在晶片接合區域102旁的一周邊區域104內。
隨後，可以在介電層412上形成一鈍化層413，例如聚亞醯胺或防焊遮罩材料。鈍化層413可以設有多個開孔，分別顯露出第一凸塊墊415a及第二凸塊墊415b。繼之，可以進行一電鍍焊錫凸塊製程，分別在第一凸塊墊415a及第二凸塊墊415b上形成第一凸塊416a以及第二凸塊416b。
如第3圖所示，將個別的覆晶晶片或晶粒420a以主動面朝下面對重佈線層410，藉由第一凸塊416a安裝至重佈線層410上，形成“晶片對晶圓接合”的堆疊結構。這些個別的覆晶晶片或晶粒420a為具有特定功能的主動積體電路晶片，例如繪圖處理器(GPU)、中央處理器(CPU)、記憶體晶片等等。
根據所述實施例，複數個穿矽通孔(TSV)晶片420b藉由第二凸塊416b安裝至晶片接合區域102旁的周邊區域104內。各TSV晶片420b可以包含一基材440，例如矽基材。在基材440內製作有複數個穿矽通孔(TSV)連接結構441。在基材440相對於第二凸塊416b的上表面，可以形成有複數個凸塊442。
上述步驟完成後，可選擇性地在每一晶片或晶粒420a/420b下方填充底膠(圖未示)。隨後，可以進行熱處理，使第一凸塊416a和第二凸塊416b迴焊。
完成晶粒接合後，接著在上方覆蓋一成型模料500。成型模料500覆蓋住安裝在重佈線層410上的主動晶片420a與TSV晶片420b，同時也覆蓋住重佈線層410的頂面。成型模料500隨後會藉由一固化製程使之固化。成型模料500例如為環氧樹脂與二氧化矽填充劑的混和物，但並不限於此。
如第4圖所示，接著，可選擇性地研磨移除部分成型模料500的上部，使主動晶片420a與TSV晶片420b的凸塊442被暴露出來。在研磨成型模料過程中，部分的主動晶片420a可以被去除，但不限於此。當研磨完成時，主動晶片420a的上表面與成型模料500的上表面齊平。
如第5圖所示，再進行一凸塊製作步驟，分別在顯露出來的TSV晶片420b的凸塊442上直接形成凸塊444。這些凸塊444突出於成型模料500的上表面，用做後續連結。根據所述實施例，凸塊444可以利用電鍍方式形成，但不限於此。凸塊444可以包含銅、鎳、錫或任何已知的合適材料。
如第6圖所示，接著將此晶圓級封裝貼合另一載板600，使凸塊444面向且可以接觸到載板600。載板600可以包括一玻璃基板，但不限於此。可以選擇利用一黏著層或膠層602進行貼合。接下來，將載板300撕除剝離，顯露出鈍化層310的主表面。根據本發明實施例，重佈線層410與鈍化層310作為一中介層(interposer)。根據本發明實施例，可利用雷射剝離技術或紫外光照射技術來剝離載板300，但不限於此。
如第7圖所示，在剝離載板300之後，可以繼續在鈍化層310中形成多個開口，分別顯露出相應的焊墊，然後，分別在這些焊墊上形成焊錫凸塊或焊接錫球520。隨後，將載板600以及膠層602去除，顯露出凸塊444。
如第8圖所示，將載板600以及膠層602去除之後，將此晶圓級封裝切割分隔出個別的晶片封裝10。例如，進行切割時，可以先將此晶圓級封裝貼合一切割膠帶(圖未示)，其中凸塊520面向且可以接觸此切割膠帶。
如第9圖所示，再將一晶片封裝20，其包含一模塑的半導體晶片201，安置在晶片封裝10上方，如此形成一PoP堆疊封裝構件1。根據本發明實施例，晶片封裝20可以透過凸塊444以及TSV晶片420b與晶片封裝10電連接。
本發明的優點在於大部分晶片接合區域102旁的周邊區域104被TSV晶片420b佔據，如此可以減少成型模料500的使用量，因此，晶圓或晶片封裝的翹曲可以減輕或避免。
請參照第10圖至第20圖。第10圖至第20圖為根據本發明另一實施例的示意性剖面圖，例示製作PoP堆疊封裝構件的方法，其中仍沿用相同的標號表示相同的層、區域或部件。
如第10圖所示，同樣的，提供一載板300，可以是一可撕除的基板材料。載板300還可包括一黏著層(圖未示)，但不限於此。在載板300的上表面，可以形成至少一介電層或者鈍化層310。鈍化層310可以包含有機材料，例如，聚亞醯胺(polyimide, PI)，或無機材料，例如氮化矽、氧化矽或類似的材料。
如第11圖所示，接著，在鈍化層310上形成一重佈線層410。重佈線層410可以包含至少一介電層412以及至少一金屬層414。上述介電層412可以包含有機材料，例如聚亞醯胺，或無機材料，例如氮化矽、氧化矽或類似的材料，但不限於此。金屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似的材料。
根據所述實施例，金屬層414可包含複數個凸塊墊415a，自介電層412的頂面暴露出來。凸塊墊415a設置於一晶片接合區域102內。金屬層414可包含複數個接墊415b設於晶片接合區域102旁的周邊區域104內。
隨後，可以在介電層412上形成一鈍化層413，例如聚亞醯胺或防焊遮罩材料。鈍化層413可以設有多個開孔，分別顯露出凸塊墊415a。繼之，可以進行一電鍍焊錫凸塊製程，在凸塊墊415a上形成凸塊416a。
如第12圖所示，將個別的覆晶晶片或晶粒420a以主動面朝下面對重佈線層410，藉由凸塊416a安裝至重佈線層410上，形成“晶片對晶圓接合”的堆疊結構。這些個別的覆晶晶片或晶粒420a為具有特定功能的主動積體電路晶片，例如繪圖處理器(GPU)、中央處理器(CPU)、記憶體晶片等等。
根據所述實施例，複數個虛設晶片(或稱翹曲控制晶片)420c被安裝至晶片接合區域102旁的周邊區域104內。根據本發明實施例，虛設晶片420c可以包含矽或不用的矽晶片，但不限於此。根據本發明實施例，虛設晶片420c可以藉由一黏著層(圖未示)黏貼在鈍化層413上。
上述步驟完成後，可選擇性地在每一晶片420a下方填充底膠(圖未示)。隨後，可以進行熱處理，使凸塊416a迴焊。
完成晶粒接合後，接著在上方覆蓋一成型模料500。成型模料500覆蓋住主動晶片420a與虛設晶片420c，同時也覆蓋住重佈線層410的頂面。成型模料500隨後會藉由一固化製程使之固化。成型模料500例如為環氧樹脂與二氧化矽填充劑的混和物，但並不限於此。
如第13圖所示，接著，可研磨移除部分成型模料500的上部，使主動晶片420a與虛設晶片420c的上表面被暴露出來。在研磨成型模料過程中，部分的主動晶片420a可以被去除，但不限於此。當研磨完成時，主動晶片420a與虛設晶片420c的上表面與成型模料500的上表面齊平。
如第14圖所示，接著在主動晶片420a的上表面、虛設晶片420c的上表面與成型模料500的上表面形成一介電層610，例如，矽氧層。根據本發明實施例，介電層610係整面沉積。然後，進行一蝕刻製程，在介電層610及虛設晶片420c內形成穿矽通孔(TSV)620。穿矽通孔620分別顯露出周邊區域104內的接墊415b。
如第15圖所示，在穿矽通孔620的側壁上形成一隔離氧化層630。例如，在介電層610表面、穿矽通孔620的側壁上以及底部沉積一共形的矽氧層。然後，進行一乾蝕刻製程，蝕刻掉位於穿矽通孔620底部的矽氧層，顯露出接墊415b。
如第16圖所示，接著進行一金屬填充製程，在穿矽通孔620內填入一金屬層650。根據本發明實施例，穿矽通孔620可以被金屬層650完全填滿。可以進行一微影及蝕刻製程，在介電層610上形成一金屬導線圖案652，例如，凸塊焊墊。
如第17圖所示，接著將此晶圓級封裝貼合另一載板600，使金屬導線圖案652面向且可以接觸到載板600。載板600可以包括一玻璃基板，但不限於此。可以選擇利用一黏著層或膠層(圖未示)進行貼合。接下來，將載板300撕除剝離，顯露出鈍化層310的主表面。根據本發明實施例，重佈線層410與鈍化層310作為一中介層(interposer)。根據本發明實施例，可利用雷射剝離技術或紫外光照射技術來剝離載板300，但不限於此。
如第18圖所示，在剝離載板300之後，可以繼續在鈍化層310中形成多個開口，分別顯露出相應的焊墊，然後，分別在這些焊墊上形成焊錫凸塊或焊接錫球520。隨後，將載板600去除，顯露出金屬導線圖案652。
如第19圖所示，將載板600去除之後，將此晶圓級封裝切割分隔出個別的晶片封裝10。例如，進行切割時，可以先將此晶圓級封裝貼合一切割膠帶700，其中焊接錫球520面向且可以接觸切割膠帶700。
如第20圖所示，再將一晶片封裝20，其包含一模塑的半導體晶片201，安置在晶片封裝10上方，如此形成一PoP堆疊封裝構件1a。根據本發明實施例，晶片封裝20可以透過凸塊252、金屬導線圖案652以及穿矽通孔620與晶片封裝10電連接。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1‧‧‧PoP堆疊封裝構件
1a‧‧‧PoP堆疊封裝構件
10‧‧‧晶片封裝
20‧‧‧晶片封裝
102‧‧‧晶片接合區域
104‧‧‧周邊區域
201‧‧‧半導體晶片
300‧‧‧載板
310‧‧‧鈍化層
410‧‧‧重佈線層
412‧‧‧介電層
413‧‧‧鈍化層
414‧‧‧金屬層
415a‧‧‧第一凸塊墊(凸塊墊)
415b‧‧‧第二凸塊墊(接墊)
416a‧‧‧第一凸塊(凸塊)
416b‧‧‧第二凸塊
420a‧‧‧晶粒(晶片)
420b‧‧‧TSV晶片
420c‧‧‧虛設晶片(翹曲控制晶片)
440‧‧‧基材
441‧‧‧TSV連接結構
442‧‧‧凸塊
444‧‧‧凸塊
500‧‧‧成型模料
520‧‧‧焊接錫球
600‧‧‧載板
602‧‧‧膠層
610‧‧‧介電層
620‧‧‧穿矽通孔(TSV)
630‧‧‧隔離氧化層
650‧‧‧金屬層
652‧‧‧金屬導線圖案
700‧‧‧切割膠帶
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。   第1圖至第9圖為根據本發明一實施例的示意性剖面圖，例示製作PoP堆疊封裝構件的方法。   第10圖至第20圖為根據本發明另一實施例的示意性剖面圖，例示製作PoP堆疊封裝構件的方法。
1‧‧‧PoP堆疊封裝構件
10‧‧‧晶片封裝
20‧‧‧晶片封裝
201‧‧‧半導體晶片
310‧‧‧鈍化層
410‧‧‧重佈線層
412‧‧‧介電層
413‧‧‧鈍化層
414‧‧‧金屬層
415a‧‧‧第一凸塊墊
415b‧‧‧第二凸塊墊
416a‧‧‧第一凸塊
416b‧‧‧第二凸塊
420a‧‧‧晶粒
420b‧‧‧TSV晶片
440‧‧‧基材
441‧‧‧TSV連接結構
442‧‧‧凸塊
444‧‧‧凸塊
500‧‧‧成型模料
520‧‧‧焊接錫球

Claims (9)

  1. 一種PoP堆疊封裝構件，包含有：        一底部晶片封裝，包含： 一中介層，具有一第一面以及一相對該第一面的第二面；       至少一主動晶片，經由複數個第一凸塊安裝在該第一面，且位於一晶片接合區域內；       至少一矽穿通孔(TSV)晶片，安裝在該第一面，位於該晶片接合區域旁的一周邊區域內，其中該TSV晶片包含至少一TSV連接結構，經由該周邊區域內的複數個第二凸塊安置在該第一面上；       一成型模料，設於該第一面，覆蓋該主動晶片以及該TSV晶片；以及       複數個焊接錫球，設於該第二面；        一上部晶片封裝，疊設於該底部晶片封裝上。
  2. 如申請專利範圍第1項所述的PoP堆疊封裝構件，其中該中介層包含一重佈線層。
  3. 如申請專利範圍第2項所述的PoP堆疊封裝構件，其中該重佈線層包含至少一介電層以及至少一金屬層。
  4. 如申請專利範圍第1項所述的PoP堆疊封裝構件，其中該上部晶片封裝包含至少一模塑的半導體晶片。
  5. 如申請專利範圍第1項所述的PoP堆疊封裝構件，其中該上部晶片封裝經由複數個設於該TSV晶片上的第三凸塊安裝在該底部晶片封裝上。
  6. 一種PoP堆疊封裝構件，包含有：        一底部晶片封裝，包含： 一中介層，具有一第一面以及一相對該第一面的第二面；       至少一主動晶片，經由複數個第一凸塊安裝在該第一面，且位於一晶片接合區域內；       至少一虛設晶片，安裝在該第一面，位於該晶片接合區域旁的一周邊區域內，該虛設晶片直接設於該中介層的一鈍化層上；       一介電層，覆蓋該主動晶片以及該虛設晶片；       至少一穿矽通孔(TSV)連接結構，貫穿該介電層與該虛設晶片；       一成型模料，設於該第一面，覆蓋該主動晶片以及該虛設晶片；以及       複數個焊接錫球，設於該第二面；        一上部晶片封裝，疊設於該底部晶片封裝上。
  7. 如申請專利範圍第6項所述的PoP堆疊封裝構件，其中該虛設晶片係以一膠層直接貼合於該鈍化層上。
  8. 如申請專利範圍第6項所述的PoP堆疊封裝構件，其中該TSV連接結構係與一位於該介電層上的金屬導線圖案電連接。
  9. 如申請專利範圍第8項所述的PoP堆疊封裝構件，其中該上部晶片封裝經由複數個設於該金屬導線圖案上的第二凸塊安裝在該底部晶片封裝上。
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