CN106252324A - 封装上封装堆叠封装构件 - Google Patents

封装上封装堆叠封装构件 Download PDF

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Publication number
CN106252324A
CN106252324A CN201610003082.4A CN201610003082A CN106252324A CN 106252324 A CN106252324 A CN 106252324A CN 201610003082 A CN201610003082 A CN 201610003082A CN 106252324 A CN106252324 A CN 106252324A
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chip
package
encapsulation
silicon
layer
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CN201610003082.4A
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CN106252324B (zh
Inventor
施信益
施能泰
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Micron Technology Inc
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Inotera Memories Inc
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Abstract

本发明公开了一种封装上封装(PoP)堆叠封装构件，包括一底部芯片封装以及一上部芯片封装，叠设于所述底部芯片封装上。其中底部芯片封装包括一中介层，具有一第一面以及一相对第一面的第二面；至少一有源芯片，通过多个第一凸块安装在第一面，且位于一芯片接合区域内；至少一穿硅通孔(TSV)芯片，安装在第一面，位于芯片接合区域旁的一周边区域内，其中TSV芯片包括至少一TSV连接结构，通过周边区域内的多个第二凸块安置在第一面上；一模塑料，设于第一面，覆盖有源芯片及TSV芯片；以及多个焊接锡球，设于第二面。

Description

封装上封装堆叠封装构件
技术领域
本发明涉及半导体封装技术领域，特别涉及一种封装上封装(Package-on-Package,PoP)堆叠封装构件及其制作方法。
背景技术
随着半导体制造技术的进步，微电子器件变得更小，器件内部的电路变得越来越密集。为了减少微电子器件的尺寸，这些微电子器件的封装构件结构必须变得更加紧密。为了满足在更小的空间达到更高密度的要求，业界于是发展出3D堆叠封装，例如，PoP(Package-on-Package)堆叠封装。
PoP堆叠封装构件通常包括一个顶部封装，其内有一芯片，与具有另一芯片的底部封装接合。在PoP堆叠封装构件的设计中，顶部封装可以通过外围焊球互连到底部封装。然而，现有技术的PoP堆叠封装构件无法提供非常紧密间距的堆叠。此外，现有技术的PoP堆叠封装构件外形较大且翘曲控制不良。
晶圆级封装工艺中，通常会在晶圆及安装在晶圆上的芯片表面覆盖一相对较厚的模塑料。此模塑料与集成电路衬底的热膨胀系数(CTE)差异，易导致封装翘曲变形，也使得封装整体的厚度增加。晶圆翘曲一直是该领域关注的问题。晶圆翘曲使芯片与晶圆间的接合不易维持，易造成“芯片对晶圆接合”(chip to wafer)的组装失败。翘曲问题在大尺寸晶圆上更是明显，特别是对于具有小间距重分布层的晶圆级半导体封装工艺，问题更为严重。
发明内容
有鉴于此，本发明主要目的在于提供一具有PoP堆叠封装组态的半导体装置，以解决上述先前技艺的不足与缺点。
本发明一实施例提供一种PoP堆叠封装构件，包括有一底部芯片封装以及一上部芯片封装，叠设于所述底部芯片封装上。所述底部芯片封装包括一中介层，具有一第一面以及一相对所述第一面的第二面；至少一有源芯片，通过多个第一凸块安装在所述第一面，且位于一芯片接合区域内；至少一穿硅通孔(TSV)芯片，安装在所述第一面，位于所述芯片接合区域旁的一周边区域内，其中所述TSV芯片包括至少一TSV连接结构，通过所述周边区域内的多个第二凸块安置在所述第一面上；一模塑料，设于所述第一面，覆盖所述有源芯片以及所述TSV芯片；以及多个焊接锡球，设于所述第二面。
根据本发明一实施例，所述上部芯片封装通过多个设于所述TSV芯片上的第三凸块安装在所述底部芯片封装上。
本发明另一实施例提供一种PoP堆叠封装构件，包括有一底部芯片封装以及一上部芯片封装，叠设于所述底部芯片封装上。所述底部芯片封装包括一中介层，具有一第一面以及一相对所述第一面的第二面；至少一有源芯片，通过多个第一凸块安装在所述第一面，且位于一芯片接合区域内；至少一虚设芯片，安装在所述第一面，位于所述芯片接合区域旁的一周边区域内，所述虚设芯片直接设于所述中介层的一钝化层上；一介电层，覆盖所述有源芯片以及所述虚设芯片；至少一穿硅通孔(TSV)连接结构，贯穿所述介电层与所述虚设芯片；一模塑料，设于所述第一面，覆盖所述有源芯片以及所述虚设芯片；以及多个焊接锡球，设于所述第二面。
毋庸置疑的，所述领域的技术人员读完接下来本发明优选实施例的详细描述与附图后，均可了解本发明的目的。
附图说明
图1至图9为根据本发明一实施例的示意性剖面图，为制作PoP堆叠封装构件的方法。
图10至图20为根据本发明另一实施例的示意性剖面图，为制作PoP堆叠封装构件的方法。
其中，附图标记说明如下：
1 PoP堆叠封装构件
1a PoP堆叠封装构件
10 芯片封装
20 芯片封装
102 芯片接合区域
104 周边区域
201 半导体芯片
252 凸块
300 载板
310 钝化层
410 重分布层
412 介电层
413 钝化层
414 金属层
415a 第一凸块垫(凸块垫)
415b 第二凸块垫(接垫)
416a 第一凸块(凸块)
416b 第二凸块
420a 晶粒(芯片)
420b TSV芯片
420c 虚设芯片(翘曲控制芯片)
440 基材
441 TSV连接结构
442 凸块
444 凸块
500 模塑料
520 焊接锡球
600 载板
602 胶层
610 介电层
620 穿硅通孔(TSV)
630 隔离氧化层
650 金属层
652 金属导线图案
700 切割胶带
具体实施方式
接下来的详细说明须参照相关附图所示内容，用来说明可依据本发明具体实施的实施例。这些实施例提供足够的细节，可使此领域中的技术人员充分了解并具体实施本发明。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改应用在其他实施例上。
因此，接下来的详细描述并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具同等意义，也应属本发明涵盖的范围。本发明实施例所参照的附图为示意图，并未按比例绘制，且相同或类似的特征通常以相同的附图标记描述。在本说明书中，“晶粒”、“半导体芯片”与“半导体晶粒”具相同含意，可交替使用。
在本说明书中，“晶圆”与“基板”意指任何包括一暴露面，可依据本发明实施例所示在其上沉积材料，制作集成电路结构的结构物，例如重分布层(RDL)。须了解的是“基板”包括半导体晶圆，但并不限于此。“基板”在工艺中也意指包括制作于其上的材料层的半导体结构物。请参照图1到图9。图1到图9为根据本发明一实施例的示意性剖面图，为制作PoP堆叠封装构件的方法。
如图1所示，提供一载板300，可以是一可撕除的基板材料。载板300还可包括一黏着层(图未示)，但不限于此。在载板300的上表面，可以形成至少一介电层或者钝化层310。钝化层310可以包括有机材料，例如，聚亚酰胺(polyimide,PI)，或无机材料，例如氮化硅、氧化硅或类似的材料。
如图2所示，接着，在钝化层310上形成一重分布层(RDL)410。重分布层410可以包括至少一介电层412以及至少一金属层414。上述介电层412可以包括有机材料，例如聚亚酰胺(polyimide,PI)，或无机材料，例如氮化硅、氧化硅或类似的材料，但不限于此。金属层414可包括铝、铜、钨、钛、氮化钛或类似的材料。
根据所述实施例，金属层414可包括多个第一凸块垫415a及第二凸块垫415b，自介电层412的上表面暴露出来。第一凸块垫415a设置在一芯片接合区域102内，而第二凸块垫415b设置在芯片接合区域102外，例如设置在芯片接合区域102旁的一周边区域104内。
随后，可以在介电层412上形成一钝化层413，例如聚亚酰胺或阻焊遮罩材料。钝化层413可以设有多个开孔，分别显露出第一凸块垫415a及第二凸块垫415b。接下来，可以进行一电镀焊锡凸块工艺，分别在第一凸块垫415a及第二凸块垫415b上形成第一凸块416a以及第二凸块416b。
如图3所示，将个别的覆晶芯片或晶粒420a以有源面朝下面对重分布层410，通过第一凸块416a安装到重分布层410上，形成“芯片对晶圆接合”的堆叠结构。这些个别的覆晶芯片或晶粒420a为具有特定功能的有源集成电路芯片，例如绘图处理器(GPU)、中央处理器(CPU)、存储器芯片等等。
根据所述实施例，多个穿硅通孔(TSV)芯片420b通过第二凸块416b安装到芯片接合区域102旁的周边区域104内。各TSV芯片420b可以包括一基材440，例如硅基材。在基材440内制作有多个穿硅通孔(TSV)连接结构441。在基材440相对于第二凸块416b的上表面，可以形成有多个凸块442。
上述步骤完成后，可选择性的在每一芯片或晶粒420a/420b下方填充底胶(图未示)。随后，可以进行热处理，使第一凸块416a和第二凸块416b回焊。
完成晶粒接合后，接着在上方覆盖一模塑料500。模塑料500覆盖住安装在重分布层410上的有源芯片420a与TSV芯片420b，同时也覆盖住重分布层410的上表面。模塑料500随后会通过一固化工艺使之固化。模塑料500例如为环氧树脂与二氧化硅填充剂的混和物，但并不限于此。
如图4所示，接着，可选择性的研磨移除部分模塑料500的上部，使有源芯片420a与TSV芯片420b的凸块442被暴露出来。在研磨模塑料的过程中，部分的有源芯片420a可以被去除，但不限于此。当研磨完成时，有源芯片420a的上表面与模塑料500的上表面齐平。
如图5所示，再进行一凸块制作步骤，分别在显露出来的TSV芯片420b的凸块442上直接形成凸块444。这些凸块444突出于模塑料500的上表面，用做后续连结。根据所述实施例，凸块444可以利用电镀方式形成，但不限于此。凸块444可以包括铜、镍、锡或任何已知的合适材料。
如图6所示，接着将此晶圆级封装贴合另一载板600，使凸块444面向且可以接触到载板600。载板600可以包括一玻璃基板，但不限于此。可以选择利用一黏着层或胶层602进行贴合。接下来，将载板300撕除剥离，显露出钝化层310的主表面。根据本发明实施例，重分布层410与钝化层310作为一中介层(interposer)。根据本发明实施例，可利用激光剥离技术或紫外光照射技术来剥离载板300，但不限于此。
如图7所示，在剥离载板300之后，可以继续在钝化层310中形成多个开口，分别显露出相应的焊盘，然后，分别在这些焊盘上形成焊锡凸块或焊接锡球520。然后，将载板600以及胶层602去除，显露出凸块444。
如图8所示，将载板600以及胶层602去除之后，将此晶圆级封装切割分隔出个别的芯片封装10。例如，进行切割时，可以先将此晶圆级封装贴合一切割胶带(图未示)，其中凸块520面向且可以接触此切割胶带。
如图9所示，再将一芯片封装20，其包括一模塑的半导体芯片201，安置在芯片封装10上方，如此形成一PoP堆叠封装构件1。根据本发明实施例，芯片封装20可以通过凸块444以及TSV芯片420b与芯片封装10电连接。
本发明的优点在于大部分芯片接合区域102旁的周边区域104被TSV芯片420b占据，如此可以减少模塑料500的使用量，因此，晶圆或芯片封装的翘曲可以减轻或避免。
请参照图10到图20。图10到图20为根据本发明另一实施例的示意性剖面图，为制作PoP堆叠封装构件的方法，其中仍沿用相同的标号表示相同的层、区域或部件。
如图10所示，同样的，提供一载板300，可以是一可撕除的基板材料。载板300还可包括一黏着层(图未示)，但不限于此。在载板300的上表面，可以形成至少一介电层或者钝化层310。钝化层310可以包括有机材料，例如，聚亚酰胺(polyimide,PI)，或无机材料，例如氮化硅、氧化硅或类似的材料。
如图11所示，接着，在钝化层310上形成一重分布层410。重分布层410可以包括至少一介电层412以及至少一金属层414。上述介电层412可以包括有机材料，例如聚亚酰胺，或无机材料，例如氮化硅、氧化硅或类似的材料，但不限于此。金属层414可包括铝、铜、钨、钛、氮化钛或类似的材料。
根据所述实施例，金属层414可包括多个凸块垫415a，自介电层412的上表面暴露出来。凸块垫415a设置在一芯片接合区域102内。金属层414可包括多个接垫415b设于芯片接合区域102旁的周边区域104内。
随后，可以在介电层412上形成一钝化层413，例如聚亚酰胺或阻焊遮罩材料。钝化层413可以设有多个开孔，分别显露出凸块垫415a。接着，可以进行一电镀焊锡凸块工艺，在凸块垫415a上形成凸块416a。
如图12所示，将个别的覆晶芯片或晶粒420a以有源面朝下面对重分布层410，通过凸块416a安装到重分布层410上，形成“芯片对晶圆接合”的堆叠结构。这些个别的覆晶芯片或晶粒420a为具有特定功能的有源集成电路芯片，例如绘图处理器(GPU)、中央处理器(CPU)、存储器芯片等等。
根据所述实施例，多个虚设芯片(或称翘曲控制芯片)420c被安装到芯片接合区域102旁的周边区域104内。根据本发明实施例，虚设芯片420c可以包括硅或不用的硅芯片，但不限于此。根据本发明实施例，虚设芯片420c可以通过一黏着层(图未示)黏贴在钝化层413上。
上述步骤完成后，可选择性的在每一芯片420a下方填充底胶(图未示)。随后，可以进行热处理，使凸块416a回焊。
完成晶粒接合后，接着在上方覆盖一模塑料500。模塑料500覆盖住有源芯片420a与虚设芯片420c，同时也覆盖住重分布层410的上表面。模塑料500随后会通过一固化工艺使之固化。模塑料500例如为环氧树脂与二氧化硅填充剂的混和物，但并不限于此。
如图13所示，接着，可研磨移除部分模塑料500的上部，使有源芯片420a与虚设芯片420c的上表面被暴露出来。在研磨模塑料过程中，部分的有源芯片420a可以被去除，但不限于此。当研磨完成时，有源芯片420a与虚设芯片420c的上表面与模塑料500的上表面齐平。
如图14所示，接着在有源芯片420a的上表面、虚设芯片420c的上表面与模塑料500的上表面形成一介电层610，例如，硅氧层。根据本发明实施例，介电层610是整面沉积。然后，进行一蚀刻工艺，在介电层610及虚设芯片420c内形成穿硅通孔(TSV)620。穿硅通孔620分别显露出周边区域104内的接垫415b。
如图15所示，在穿硅通孔620的侧壁上形成一隔离氧化层630。例如，在介电层610表面、穿硅通孔620的侧壁上以及底部沉积一共形的硅氧层。然后，进行一干蚀刻工艺，蚀刻掉位于穿硅通孔620底部的硅氧层，显露出接垫415b。
如图16所示，接着进行一金属填充工艺，在穿硅通孔620内填入一金属层650。根据本发明实施例，穿硅通孔620可以被金属层650完全填满。可以进行一光刻及蚀刻工艺，在介电层610上形成一金属导线图案652，例如，凸块焊盘。
如图17所示，接着将此晶圆级封装贴合另一载板600，使金属导线图案652面向且可以接触到载板600。载板600可以包括一玻璃基板，但不限于此。可以选择利用一黏着层或胶层(图未示)进行贴合。接下来，将载板300撕除剥离，显露出钝化层310的主表面。根据本发明实施例，重分布层410与钝化层310作为一中介层(interposer)。根据本发明实施例，可利用激光剥离技术或紫外光照射技术来剥离载板300，但不限于此。
如图18所示，在剥离载板300之后，可以继续在钝化层310中形成多个开口，分别显露出相应的焊盘，然后，分别在这些焊盘上形成焊锡凸块或焊接锡球520。随后，将载板600去除，显露出金属导线图案652。
如图19所示，将载板600去除之后，将此晶圆级封装切割分隔出个别的芯片封装10。例如，进行切割时，可以先将此晶圆级封装贴合一切割胶带700，其中焊接锡球520面向且可以接触切割胶带700。
如图20所示，再将一芯片封装20，其中包括一模塑的半导体芯片201，安置在芯片封装10上方，如此形成一PoP堆叠封装构件1a。根据本发明实施例，芯片封装20可以通过凸块252、金属导线图案652以及穿硅通孔620与芯片封装10电连接。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

1.一种封装上封装堆叠封装构件，其特征在于，包括：
一底部芯片封装，包括：
一中介层，具有一第一面以及一相对所述第一面的第二面；
至少一有源芯片，通过多个第一凸块安装在所述第一面，且位于一芯片接合区域内；
至少一穿硅通孔芯片，安装在所述第一面，位于所述芯片接合区域旁的一周边区域内，其中所述穿硅通孔芯片包括至少一穿硅通孔连接结构，通过所述周边区域内的多个第二凸块安置在所述第一面上；
一模塑料，设于所述第一面，覆盖所述有源芯片以及所述穿硅通孔芯片；以及
多个焊接锡球，设于所述第二面；
一上部芯片封装，叠设于所述底部芯片封装上。
2.根据权利要求1所述的封装上封装堆叠封装构件，其特征在于，所述中介层包括一重分布层。
3.根据权利要求2所述的封装上封装堆叠封装构件，其特征在于，所述重分布层包括至少一介电层以及至少一金属层。
4.根据权利要求1所述的封装上封装堆叠封装构件，其特征在于，所述上部芯片封装包括至少一模塑的半导体芯片。
5.根据权利要求1所述的封装上封装堆叠封装构件，其特征在于，所述上部芯片封装通过多个设于所述穿硅通孔芯片上的第三凸块安装在所述底部芯片封装上。
6.一种封装上封装堆叠封装构件，其特征在于，包括：
一底部芯片封装，包括：
一中介层，具有一第一面以及一相对所述第一面的第二面；
至少一有源芯片，通过多个第一凸块安装在所述第一面，且位于一芯片接合区域内；
至少一虚设芯片，安装在所述第一面，位于所述芯片接合区域旁的一周边区域内，所述虚设芯片直接设于所述中介层的一钝化层上；
一介电层，覆盖所述有源芯片以及所述虚设芯片；
至少一穿硅通孔连接结构，贯穿所述介电层与所述虚设芯片；
一模塑料，设于所述第一面，覆盖所述有源芯片以及所述虚设芯片；以及
多个焊接锡球，设于所述第二面；
一上部芯片封装，叠设于所述底部芯片封装上。
7.根据权利要求6所述的封装上封装堆叠封装构件，其特征在于，所述虚设芯片是以一胶层直接贴合于所述钝化层上。
8.根据权利要求6所述的封装上封装堆叠封装构件，其特征在于，所述穿硅通孔连接结构是与一位于所述介电层上的金属导线图案电连接。
9.根据权利要求8所述的封装上封装堆叠封装构件，其特征在于，所述上部芯片封装通过多个设于所述金属导线图案上的第二凸块安装在所述底部芯片封装上。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108695267A (zh) * 2017-03-30 2018-10-23 台湾积体电路制造股份有限公司 封装结构
CN110416175A (zh) * 2018-04-30 2019-11-05 爱思开海力士有限公司 包括与半导体晶片间隔开的桥式晶片的半导体封装
CN110867434A (zh) * 2018-08-28 2020-03-06 爱思开海力士有限公司 包括桥接晶片的堆叠封装
WO2020103162A1 (zh) * 2018-11-23 2020-05-28 华为技术有限公司 一种芯片以及芯片封装方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9704790B1 (en) * 2016-03-14 2017-07-11 Micron Technology, Inc. Method of fabricating a wafer level package
US9748167B1 (en) * 2016-07-25 2017-08-29 United Microelectronics Corp. Silicon interposer, semiconductor package using the same, and fabrication method thereof
TWI647805B (zh) * 2016-09-09 2019-01-11 矽品精密工業股份有限公司 電子封裝件及其製法
US9922964B1 (en) * 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
US10297471B2 (en) * 2016-12-15 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out structure and method of fabricating the same
US9865567B1 (en) * 2017-02-02 2018-01-09 Xilinx, Inc. Heterogeneous integration of integrated circuit device and companion device
US9923059B1 (en) * 2017-02-20 2018-03-20 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors
US10083897B2 (en) 2017-02-20 2018-09-25 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
KR101901711B1 (ko) 2017-09-27 2018-09-27 삼성전기 주식회사 팬-아웃 반도체 패키지
US10665582B2 (en) * 2017-11-01 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor package structure
KR101963293B1 (ko) * 2017-11-01 2019-03-28 삼성전기주식회사 팬-아웃 반도체 패키지
KR101982057B1 (ko) 2017-11-30 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지
KR102450580B1 (ko) 2017-12-22 2022-10-07 삼성전자주식회사 금속 배선 하부의 절연층 구조를 갖는 반도체 장치
US10522512B2 (en) 2018-05-02 2019-12-31 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
KR102536269B1 (ko) * 2018-09-14 2023-05-25 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US10867955B2 (en) 2018-09-27 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having adhesive layer surrounded dam structure
US11063019B2 (en) * 2019-07-17 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure, chip structure and method of fabricating the same
KR20210015071A (ko) * 2019-07-31 2021-02-10 삼성전자주식회사 반도체 패키지
US11239217B2 (en) * 2020-03-30 2022-02-01 Nanya Technology Corporation Semiconductor package including a first sub-package stacked atop a second sub-package

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100133704A1 (en) * 2008-12-01 2010-06-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias
CN102034718A (zh) * 2009-09-23 2011-04-27 新科金朋有限公司 半导体器件和在tsv转接板中形成开口腔以在wlcsmp中容纳半导体裸片的方法
US20140103527A1 (en) * 2012-03-23 2014-04-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9230898B2 (en) * 2009-08-17 2016-01-05 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8987896B2 (en) * 2009-12-16 2015-03-24 Intel Corporation High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same
US8508045B2 (en) * 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US8686570B2 (en) * 2012-01-20 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-dimensional integrated circuit structures and methods of forming the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100133704A1 (en) * 2008-12-01 2010-06-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias
CN102034718A (zh) * 2009-09-23 2011-04-27 新科金朋有限公司 半导体器件和在tsv转接板中形成开口腔以在wlcsmp中容纳半导体裸片的方法
US20140103527A1 (en) * 2012-03-23 2014-04-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108695267A (zh) * 2017-03-30 2018-10-23 台湾积体电路制造股份有限公司 封装结构
US11417620B2 (en) 2017-03-30 2022-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device encapsulated by molding material attached to redestribution layer
US11887952B2 (en) 2017-03-30 2024-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device encapsulated by molding material attached to redistribution layer
CN110416175A (zh) * 2018-04-30 2019-11-05 爱思开海力士有限公司 包括与半导体晶片间隔开的桥式晶片的半导体封装
CN110867434A (zh) * 2018-08-28 2020-03-06 爱思开海力士有限公司 包括桥接晶片的堆叠封装
WO2020103162A1 (zh) * 2018-11-23 2020-05-28 华为技术有限公司 一种芯片以及芯片封装方法
CN112219276A (zh) * 2018-11-23 2021-01-12 华为技术有限公司 一种芯片以及芯片封装方法

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