WO2020103162A1 - 一种芯片以及芯片封装方法 - Google Patents

一种芯片以及芯片封装方法

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Publication number
WO2020103162A1
WO2020103162A1 PCT/CN2018/117314 CN2018117314W WO2020103162A1 WO 2020103162 A1 WO2020103162 A1 WO 2020103162A1 CN 2018117314 W CN2018117314 W CN 2018117314W WO 2020103162 A1 WO2020103162 A1 WO 2020103162A1
Authority
WO
WIPO (PCT)
Prior art keywords
die
chip
semiconductor
insulating material
wiring layer
Prior art date
Application number
PCT/CN2018/117314
Other languages
English (en)
French (fr)
Inventor
张晓东
官勇
李珩
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201880094194.2A priority Critical patent/CN112219276A/zh
Priority to PCT/CN2018/117314 priority patent/WO2020103162A1/zh
Publication of WO2020103162A1 publication Critical patent/WO2020103162A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Definitions

  • the present application relates to the technical field of integrated circuits, in particular to a chip and a chip packaging method.
  • the package packaging (POP) technology used in the industry is combined with fan-out wafer level packaging (FOWLP) technology to stack chips in the thickness direction to improve the integration of chip packaging .
  • the chips are interconnected by solder balls / micro bumps, which cannot meet the requirements of high interconnect density chip packaging, so hybrid bonding (HB) technology should be applied.
  • the upper and lower two-layer chips usually have a hybrid bonding structure, an insulating layer through hole (TIV) and a wiring layer (redistribution) in the filling material between the upper and lower two-layer chips layer, RDL) to achieve interconnection.
  • TIV insulating layer through hole
  • RDL wiring layer
  • the feature size of the insulating layer via is large, and the interconnect density is low, which limits the number of vertical interconnect channels between the upper and lower chips, thereby limiting the upper chip (such as memory (memory )) Bandwidth, if the package requires a certain number of through holes in the insulating layer, the area of the package must be increased.
  • the existing manufacturing process of the through hole of the insulating layer is immature and the cost is high, which will lead to a high packaging cost of the chip.
  • the present application provides a chip and a chip packaging method to solve the problems of low bandwidth and high packaging cost of existing chips.
  • the present application provides a chip including: a wiring layer; a first bare chip and a semiconductor board provided on the wiring layer; wherein, the semiconductor board is provided with a first semiconductor channel; A second die provided on the first die and the semiconductor board; wherein the second die is coupled to the wiring layer through the first semiconductor channel.
  • the first die and the semiconductor board in the chip are arranged on the wiring layer, the second die is arranged on the first die and the semiconductor board, and the second die passes through the The semiconductor channel is coupled with the wiring layer so that the second die can interconnect with the first die through the semiconductor channel and the wiring layer.
  • the feature size of manufacturing the semiconductor channels in the semiconductor board is smaller, which can effectively increase the number of the semiconductor channels per unit area, and furthermore Improve interconnection density and chip bandwidth, and control the chip package area.
  • the cost of manufacturing the semiconductor channel in the semiconductor board is lower, and the manufacturing process is more mature.
  • the semiconductor channel is fabricated in the semiconductor board in the chip, compared with the prior art, less insulating material is filled in the chip.
  • the first die may be a logic die (logic die), such as a processor or an intellectual property IP core
  • the second die may be a memory (including random access memory SRAM and dynamic random access) Memory DRAM), microelectromechanical system MEMS, passive devices or adapter boards, etc .; or, the first die may be memory, MEMS, passive devices or adapter boards, etc.
  • the second die may be logic Bare chips, such as processors or intellectual property cores.
  • the semiconductor board may be a silicon board or a silicon bridge, and the semiconductor channel may be a through silicon via TSV.
  • the wiring layer may be a fan-out rewiring FO-RDL layer or an Mz metal wiring layer.
  • the active surface of the first die and the active surface of the second die both face the wiring layer, and the active surface of the second die and the first A plurality of pads are provided on the passive surface of a die; the second die is coupled to the first semiconductor channel through a part of the plurality of pads, and the second die passes through the multiple The other part of the pads is coupled to the first die.
  • the active surface of the first die faces the wiring layer
  • the active surface of the second die faces the first die
  • the second die has A plurality of pads are provided on the source surface and the active surface of the first die; the second die is coupled to the first semiconductor channel through a portion of the plurality of pads, the second The die is coupled to the first die through another part of the plurality of pads.
  • a second semiconductor channel is provided in the semiconductor substrate of the first die, and the first die also communicates with the second die and the wiring through the second semiconductor channel Layer coupling can further effectively shorten the signal transmission path between the first die and the second die, and improve the response speed of the chip.
  • the material of the semiconductor substrate in the first die and the material of the semiconductor substrate in the second die are the same as the thermal expansion coefficient of the semiconductor board (Or similar).
  • the semiconductor substrate in the first die and the semiconductor substrate in the second die and the semiconductor board use the same material.
  • the chip further includes an insulating material that encapsulates the first die, the semiconductor board, and the second die.
  • the insulating material includes a first insulating material and a second insulating material, wherein the first insulating material wraps the first die and the semiconductor board, and the second insulating material wraps the second Die.
  • the first insulating material may be silicon oxide or silicon nitride.
  • the second insulating material can also use underfill, molding compound, or other epoxy resins in scenarios where the thickness of the chip package is not required, which can effectively reduce the chip The difficulty of making insulating materials during packaging.
  • underfill, molding compound, or other epoxy resin is used as the second insulating material, the thickness of the package is relatively thick, and a silicon carrier is not required when manufacturing the wiring layer. The process is simple and the cost is low.
  • the chip further includes a solder ball, the solder ball is disposed under the wiring board, and is used to realize the first die and the second die and the external (such as a printed circuit board PCB, other chips, etc.), so that the chip can be directly interconnected with the outside through the solder ball, without the need for a substrate, thereby reducing the package thickness of the chip, while improving heat dissipation performance.
  • the solder ball is disposed under the wiring board, and is used to realize the first die and the second die and the external (such as a printed circuit board PCB, other chips, etc.), so that the chip can be directly interconnected with the outside through the solder ball, without the need for a substrate, thereby reducing the package thickness of the chip, while improving heat dissipation performance.
  • the chip includes at least two of the first dies, or includes at least two of the second dies, or includes at least two of the first dies and at least two The second die.
  • the plurality of first dies may be distributed on the same layer or different layers, and the plurality of second dies may be distributed on the same layer or different layers.
  • the at least two first dies are stacked, and active surfaces of two adjacent first dies are coupled to each other.
  • the at least two second dies are stacked, and active surfaces of two adjacent second dies are coupled to each other.
  • the present application provides an integrated chip.
  • the integrated chip includes a first chip and a second chip.
  • the first chip is the chip described in any one of the possible implementation manners of the first aspect above.
  • the first chip and the second chip are packaged together.
  • the first chip may be packaged with the second chip by stacking and packaging POP.
  • the present application provides a chip packaging method, the method comprising: bonding a semiconductor board and a first bare die on a first carrier; wherein, a first semiconductor channel is processed in the semiconductor board; The second die is bonded to the semiconductor board and the first die; the first carrier is removed, and the semiconductor board and the first die are bonded to the first carrier A wiring layer is prepared on the surface; wherein the second die is coupled to the wiring layer through the first semiconductor channel.
  • bonding the second die with the semiconductor board and the first die specifically includes: preparing a first insulating material to form a first package; wherein, the first An insulating material wraps the semiconductor board and the first die; prepare a plurality of pads on the first insulating material to form a second package; pass the second die through the plurality of pads One part is coupled to the first semiconductor channel, and the other part of the plurality of pads is coupled to the first die to form a third package.
  • the first insulating material is polished to expose the first in the semiconductor board Semiconductor channel.
  • chemical mechanical polishing CMP can be used for polishing.
  • a second die is coupled to the first semiconductor channel through a portion of the plurality of pads, through the plurality of pads Before another part of the pad is coupled with the first die, a polishing (such as CMP) process may also be performed to discard the excess bonding dielectric layer structure on the multiple pads.
  • CMP polishing
  • the semiconductor board and the first die after bonding the semiconductor board and the first die on the first carrier, and before preparing the first insulating material, the semiconductor board and the first die may be thinned to the same thickness .
  • the fourth package is bonded to a second carrier; after preparing a wiring layer on the surface where the semiconductor board and the first die are bonded to the first carrier, the second carrier is removed .
  • a plurality of solder balls may be further formed under the wiring layer .
  • Fig. 1 is a schematic diagram of the existing 3D IC package chip using HB technology
  • FIG. 2 is a schematic structural diagram of a chip provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a die provided by an embodiment of the present application.
  • FIG. 4 is a second structural schematic diagram of a chip provided by an embodiment of the present application.
  • 5a is a third structural diagram of a chip provided by an embodiment of the present application.
  • 5b is a fourth structural schematic diagram of a chip provided by an embodiment of the present application.
  • FIG. 6 is a fifth schematic structural diagram of a chip provided by an embodiment of the present application.
  • FIG. 7 is a sixth structural diagram of a chip provided by an embodiment of the present application.
  • FIG. 8 is a seventh structural schematic diagram of a chip provided by an embodiment of the present application.
  • 9a is a schematic structural diagram of an integrated chip provided by an embodiment of the present application.
  • 9b is a schematic structural diagram of another integrated chip provided by an embodiment of the present application.
  • FIG. 10 is a schematic flowchart of a chip packaging method according to an embodiment of the present application.
  • FIG. 11 is a schematic flowchart of another chip packaging method provided by an embodiment of the present application.
  • FIG. 12 is a schematic flowchart of a chip packaging method provided by a specific embodiment of the present application.
  • HB hybrid bonding
  • a common 3-D integrated circuit (3-Dimentional Integrated Circuit, 3D) package chip structure using HB technology is composed of an upper layer 100, a lower layer 200, a wiring layer 300 (redistribution layer, RDL) and a solder ball 400
  • the upper layer 100 and the lower layer 200 are bonded together through a hybrid bonding structure 500.
  • the upper layer 100 includes an upper layer die 101 and a filling material 102
  • the lower layer 200 includes a lower layer die 201 and a filling material 202.
  • An insulating layer through hole (TIV) 203 is formed in the filling material 202, and the upper layer bare
  • the active surface 103 of the chip 101 is connected to the wiring layer 300 through the hybrid bonding structure 500 and TIV 203, the active surface 204 of the lower die 201 is connected to the wiring layer 300, and the solder ball 400 is used to realize the upper die 101 and the lower layer bare
  • the sheet 201 is interconnected with an external printed circuit board (PCB).
  • PCB printed circuit board
  • the upper die 101 and the wiring layer 300 realize vertical interconnection through the TIV 203 in the filling material 202, and the TIV manufactured under the existing process technology capability has a large feature size and a low interconnect density, thereby limiting the verticality in the chip
  • the number of interconnect channels limits the bandwidth of the upper die. If the chip package requires a certain number of TIVs, the area of the chip package must be increased. Moreover, under the condition of the existing process technology capabilities, the manufacturing process of TIV is immature and the cost is high, which will result in a low chip yield after packaging.
  • the present application proposes a chip and a chip packaging method to increase the number of interconnect channels in the chip per unit area, thereby increasing the chip bandwidth and controlling the cost of chip packaging .
  • a chip 200 provided by an embodiment of the present application includes: a wiring layer 210, a first die 220, a semiconductor board 230 and a second die 240.
  • the first die 220 and the semiconductor board 230 are disposed on the wiring layer 210, and the semiconductor board 230 is provided with a first semiconductor channel 231;
  • the second die 240 is disposed on the first On a die 220 and the semiconductor board 230, the second die 240 is coupled to the wiring layer 210 through the first semiconductor channel 231.
  • a die is a die before the IC is unpackaged. Each die is an independent chip that has not been packaged. It can be composed of one or more circuits.
  • the bare chip is generally composed of a semiconductor substrate and a circuit layer disposed on the semiconductor substrate, and semiconductor devices such as transistors are formed on the semiconductor substrate, and a plurality of circuit layers are provided in the circuit layer.
  • the circuit layer is usually provided with various functional circuits, which are coupled with the semiconductor devices on the semiconductor substrate to form a complete chip circuit structure.
  • the surface on the side where the circuit layer in the bare chip is located is called an active surface
  • the surface on the side where the semiconductor substrate in the bare chip is located is called a passive surface.
  • the first die 220 may be a logic die (logic die), such as a processor or an intellectual property (IP) core (Cores), and the second die 240 may be a memory (including random Memory (static random-access memory, SRAM) and dynamic random access memory (dynamic random access memory (DRAM)), micro-electro-mechanical system (MEMS), passive device (passive) device or adapter board ( interposer); etc .; alternatively, the first die 220 may be a memory, a MEMS, a passive device or an adapter board, etc., and the second die 240 may be a logic die, such as a processor or an intellectual property core.
  • the semiconductor board 230 may be a silicon board or a dummy bridge.
  • the semiconductor channel 231 may be a through silicon via (TSV).
  • TSV through silicon via
  • the semiconductor channel 231 is coated with a metal layer or filled with metal pillars. Therefore, the semiconductor channel can be used as a signal path, and the TIV in the prior art is similar.
  • the wiring layer 210 may be a fan-out redistribution (FO-RDL) layer or a common metal wiring layer with signal traces.
  • FO-RDL fan-out redistribution
  • the present application does not limit the specific shape of the semiconductor board 230.
  • the shape of the semiconductor board is not limited to a flat plate-like structure. Anything that can make the semiconductor channel 231 can be realized by the semiconductor channel 231.
  • the semiconductor boards coupled with the second die 240 and the wiring layer 210 and the first die 220 are all applicable to the present application.
  • the second die 240 may be coupled to the semiconductor channel 231 in the semiconductor board 230 and the first die 220 in any one of but not limited to the following two ways:
  • the active surface 221 of the first die 220 faces the wiring layer 210
  • the active surface 241 of the second die 240 faces the first die 220.
  • a plurality of pads 250 are provided on the active surface 241 of the second die 240 and the active surface 221 of the first die 220.
  • the second die 240 is coupled to the first semiconductor channel 231 through a part of the plurality of pads 250, and the second die 240 is connected to the first semiconductor channel 231 through another part of the plurality of pads 250
  • the first die 220 is coupled.
  • Manner 2 As shown in FIG. 4, the active surface 221 of the first die 220 and the active surface 241 of the second die 240 both face the wiring layer 210, and the A plurality of pads 250 are provided on the active surface 241 and the passive surface 222 of the first die 220.
  • the second die 240 is coupled to the first semiconductor channel 231 through a part of the plurality of pads 250, and the second die 240 is connected to the first semiconductor channel 231 through another part of the plurality of pads 250 The first die 220 is coupled.
  • pads 250 may vertically correspond to the first semiconductor channel 231, or the pads 250 may not vertically correspond to the first semiconductor channel 231.
  • the first semiconductor channel 231 realizes interconnection.
  • a second semiconductor 223 channel is provided in the semiconductor substrate of the first die 220, and the first die 220 also passes through the second semiconductor channel 223 and the The coupling of the second die 240 and the wiring layer 210 can effectively shorten the signal transmission path between the first die 220 and the second die 220, and improve the response speed of the chip.
  • the TIV is formed in an insulating material.
  • the insulating material is usually silicon oxide or silicon nitride, and the periphery of the die is usually wrapped by the insulating material.
  • the bare semiconductor substrate is mainly made of silicon, and the thermal expansion coefficients of the bare semiconductor substrate and the insulating material do not match, resulting in a greater risk of warpage in the entire chip packaging process.
  • the present invention reduces the volume of the insulating material around or between the dies by placing the semiconductor board between the second die 240 and the wiring layer 230.
  • the material of the semiconductor substrate in the first die 220 and the material of the semiconductor substrate in the second die 240 have the same thermal expansion coefficient as the semiconductor board 230 (or similar). Since the circuit layer in the die is relatively thin and most of them are semiconductor substrates (as shown in FIG.
  • the material of the semiconductor substrate in the first die 220 and the material of the semiconductor substrate in the second die 240 are
  • the thermal expansion coefficients of the semiconductor board 230 match, the deformation of the first die 220, the semiconductor board 230, and the second die 240 under the same conditions can be substantially the same, further reducing the Warpage risk.
  • the semiconductor substrate in the first die 220 and the semiconductor substrate in the second die 240 and the semiconductor board 230 use the same material.
  • the arrangement of the die 220, the semiconductor board 230, and the second die 240 is limited.
  • the chip structure shown in FIG. 2 is merely an example, and does not limit the application.
  • the number of the first die 220, the semiconductor board 230, and the semiconductor channels 231 in the semiconductor board 230 in the chip 200, and the number of the second die 240 are based on the specific performance of the chip 200 (such as bandwidth, Area, processing speed, etc.) requirements are determined, for example, the chip 200 is required to have a larger bandwidth, and the chip 200 may include more semiconductor boards 230 and semiconductor channels 231.
  • the chip 220 includes at least two of the first dies 220, or includes at least two of the second dies 240, or includes at least two of the first dies 220 ⁇ At least two of the second dies 240.
  • the plurality of first dies 210 may be distributed on the same layer or different layers, and the plurality of second dies 240 may be distributed on the same layer (for example, the second die 240 in FIG. 2 ), Can also be distributed in different layers.
  • the at least two first dies 210 may be stacked and the active surfaces of two adjacent first dies 210 are coupled to each other. .
  • the active surface of the upper first die can pass through the semiconductor channel (such as TSV) provided in the lower first die and the active surface of the lower first die coupling.
  • the at least two second dies 240 may be stacked and the active surfaces of two adjacent second dies 240 are coupled to each other, as shown in FIG. 6 shown.
  • the active surface of the upper second die can pass through the semiconductor channel (such as TSV) provided in the lower second die and the active surface of the lower second die coupling.
  • the direction of the active surface (or passive surface) of each first die 220 in at least two of the first die 220 that are not stacked on the stack, and the The direction of the active surface (or passive surface) of each second die 240 of at least two of the second dies 240 is defined.
  • each first die 220 in at least two of the first dies 220 may all face the wiring layer 210, or, each of the first die 220 in at least two of the first
  • the passive side of the die 220 faces the wiring layer 210; or, the passive side of a part of the first die 220 of at least two of the first die 220 faces the wiring layer 210, and the other part
  • the active surface of the sheet 220 faces the wiring layer 210.
  • the direction of the active surface (or passive surface) of each second die 220 in at least two of the second dies 240 is similar to that of the first die 220 described above, and will not be repeated here.
  • the chip 200 further includes an insulating material 260 that surrounds the first die 220, the semiconductor board 230 and the second die 240.
  • the insulating material 260 includes a first insulating material 261 and a second insulating material 262, wherein the first insulating material 261 wraps the first die 220 and the semiconductor board 230 , The second insulating material 262 wraps the second die 240.
  • the thickness of the first insulating material 261 is generally high, so the first insulating material 261 generally uses silicon oxide (Silicon Oxide) or silicon nitride (Nitride Oxide).
  • silicon oxide Silicon Oxide
  • silicon nitride silicon nitride
  • the second insulating material 262 in addition to silicon oxide or silicon nitride, in some scenarios where the thickness of the chip package is not required, underfill, molding compound, or Other epoxy resins can effectively reduce the difficulty of manufacturing insulating materials during chip packaging.
  • underfill, molding compound, or other epoxy resin is used as the second insulating material 262, the thickness of the package is relatively thick, and no silicon support is required when manufacturing the wiring layer, the process is simple and the cost is simple low.
  • the chip 200 further includes solder balls 270 disposed under the wiring board 210 for implementing the first die 210 and the second die 240 interconnects with the outside (such as PCB, other chips, etc.), so that the chip 200 can be directly interconnected with the outside through the solder ball 270 without the need for a substrate, thereby reducing the package thickness of the chip 200, while improving Cooling performance.
  • solder balls 270 disposed under the wiring board 210 for implementing the first die 210 and the second die 240 interconnects with the outside (such as PCB, other chips, etc.), so that the chip 200 can be directly interconnected with the outside through the solder ball 270 without the need for a substrate, thereby reducing the package thickness of the chip 200, while improving Cooling performance.
  • the first die and the semiconductor board 230 in the chip 200 are disposed on the wiring layer 210, and the second die 240 is disposed on the first die 220 and the semiconductor board 230, and the second bare The chip 240 is coupled to the wiring layer 210 through the semiconductor channel 231 in the semiconductor board 230 so that the second die 240 can pass through the semiconductor channel 231 and the wiring layer 210 to realize the connection with the first die 220 interconnection.
  • the feature size of the semiconductor channel 231 in the semiconductor board 230 is smaller, which can effectively increase the number of the semiconductor channels per unit area. In turn, the interconnect density and chip bandwidth can be increased, and the chip package area can be controlled.
  • the cost of manufacturing the semiconductor channel 231 in the semiconductor board 230 is lower, and the manufacturing process is more mature.
  • the semiconductor channel 231 is fabricated in the semiconductor board 230 in the chip 200, compared to the prior art, the chip 200 is filled with less insulating material.
  • the material of the semiconductor board 230 is When the thermal expansion coefficients of the materials of the first die 220 and the second die 240 are close to each other, the risk of the chip 200 warping can be reduced.
  • the present application also provides an integrated chip, the integrated chip includes a first chip and a second chip, the first chip is the chip 200 described in a possible implementation manner, The first chip and the second chip are packaged together.
  • the first chip may be packaged with the second chip through a package on package (POP).
  • POP package on package
  • the first chip may be packaged with the second chip by FOWLP, or the first chip may be packaged with the second chip by other POP methods.
  • Figure 9b As shown in Figure 9b.
  • the present application also provides a chip packaging method for packaging to form the above-mentioned chip 200, as shown in FIG. 10, the method mainly includes the following steps:
  • S1003 Remove the first carrier, and prepare a wiring layer 210 on the surface where the semiconductor board 230 and the first die 220 are bonded to the first carrier; wherein, the second die 240 The first semiconductor 231 channel is coupled to the wiring layer 210.
  • step 1002 bonding the second die 240 to the semiconductor board 230 and the first die 220, specifically including:
  • a first insulating material 261 to form a first package; wherein, the first insulating material 261 wraps the semiconductor board 230 and the first die 220;
  • the pad 250 can be manufactured by photolithography and electroplating processes, and as the HB metal structure, the dielectric layer structure of the HB bonding layer is manufactured by a chemical vapor deposition (CVD) process.
  • CVD chemical vapor deposition
  • the first insulating material 261 is also polished to expose the first in the semiconductor board 230 Semiconductor channel 231. Specifically, chemical mechanical polishing (CMP) can be used for polishing.
  • CMP chemical mechanical polishing
  • the second die 240 is coupled to the first semiconductor channel 231 through a portion of the plurality of pads 250, and passes through the plurality of pads 250 Before the other part is coupled with the first die 220, a polishing (such as CMP) process may be performed to discard the excess bonding dielectric layer structure on the plurality of pads 250.
  • a polishing such as CMP
  • the semiconductor board 230 and the thickness of the first die 220 are not necessarily the same, after performing step S1001 and before preparing the first insulating material 261, the semiconductor board and the first The die is thinned to the same thickness.
  • the semiconductor board 230 and the first bare The thinned surface of the wafer 220 is bonded to the third carrier, so that the active surface of the first die 220 is upward, and the first carrier is removed, and then the subsequent packaging process is continued.
  • a second insulating material 262 is also prepared to form a fourth package; wherein the second insulating material 262 wraps the second die 240. After the second insulating material 262 is prepared, the second insulating material 262 can also be polished.
  • the thickness of the second insulating material 262 is less than the set value, before the wiring layer 210 is prepared on the surface where the semiconductor board 230 and the first die 220 are bonded to the first carrier, The fourth package is bonded to the second carrier; after the wiring layer 210 is prepared on the surface where the semiconductor board 230 and the first die 220 are bonded to the first carrier, the first package is removed Two slides, as shown in Figure 11.
  • step S1003 a plurality of solder balls can also be formed under the wiring layer.
  • Packaging to form the chip 200 shown in FIG. 4 mainly includes the following steps:
  • S1201 bonding the semiconductor board 230 and the first die 220 to the first carrier; wherein, the semiconductor board 230 is processed with a first semiconductor channel 231.
  • S1202 Thin the semiconductor board 230 and the first die to the same thickness (usually thinned to about 20 microns).
  • S1203 Prepare a first insulating material 261, where the first insulating material 261 may be silicon oxide or silicon nitride.
  • S1204 Perform CMP processing, discard the excess first insulating material 261, and expose the semiconductor channel 231 in the semiconductor board 230.
  • the HB bonding structure includes an HB bonding layer metal structure and an HB bonding layer dielectric structure.
  • S1207 Use the HB technology to bond the second die 240 to the package obtained in step 6.
  • a plurality of pads 250 are also prepared on the bonding surface of the second die 240 as an HB bonding structure, so that the second die 240 can be combined with the semiconductor board 230 after bonding
  • the semiconductor channels 231 are interconnected.
  • a second insulating layer 262 is prepared. The thickness of the second insulating layer 262 is greater than the set value.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种芯片以及芯片封装方法，以增加单位面积内芯片中互连通道的数目，进而提升芯片的带宽，并控制芯片封装的成本。所述芯片包括：布线层；设置在所述布线层上的第一裸片以及半导体板；其中，所述半导体板中设置有第一半导体通道；设置在所述第一裸片以及所述半导体板上的第二裸片；其中，所述第二裸片通过所述第一半导体通道与所述布线层耦合。

Description

一种芯片以及芯片封装方法 技术领域
本申请涉及集成电路技术领域，尤其涉及一种芯片以及芯片封装方法。
背景技术
随着半导体技术的发展，电子设备向着轻薄短小的趋势发展，将更多性能和特征集成在越来越小的空间中，因此芯片封装技术在电子设备产业链中的地位也变得更加重要。
目前，业内采用的堆叠封装(package on package，POP)技术与扇出型晶圆级封装(fan out wafer level package，FOWLP)技术相结合，在厚度方向对芯片进行堆叠以提高芯片封装的集成度。由于上述封装技术中芯片之间通过焊球(solder ball)/微凸点(micro bump)实现互连，无法满足高互连密度芯片封装的要求，因此混合键合(hybrid bonding，HB)技术应运而生。
现有技术中采用HB封装技术的芯片封装结构中上下两层芯片通常通过混合键合结构、上下两层芯片之间填充材料内的绝缘层通孔(through insulator via,TIV)以及布线层(redistribution layer,RDL)实现互连。但是，在现有的工艺技术能力条件下，绝缘层通孔的特征尺寸大，互连密度低，限制了上下层芯片之间的垂直互连通道数，从而限制了上层芯片(例如存储器(memory))的带宽，如果封装要求达到一定数量的绝缘层通孔，必须增大封装的面积。另外，现有的绝缘层通孔的制作工艺不成熟，成本高，会导致芯片的封装成本较高。
发明内容
本申请提供一种芯片以及芯片封装方法，用以解决现有芯片带宽低、封装成本高的问题。
第一方面，本申请提供了一种芯片，所述芯片包括：布线层；设置在所述布线层上的第一裸片以及半导体板；其中，所述半导体板中设置有第一半导体通道；设置在所述第一裸片以及所述半导体板上的第二裸片；其中，所述第二裸片通过所述第一半导体通道与所述布线层耦合。
通过上述方案，所述芯片中第一裸片以及半导体板设置在布线层，第二裸片设置在所述第一裸片以及所述半导体板上，所述第二裸片通过半导体板中的半导体通道与所述布线层耦合，使得所述第二裸片能够通过所述半导体通道以及所述布线层，实现与所述第一裸片互连。相较于现有技术中制作在绝缘材料中的制作TIV，在所述半导体板中制作所述半导体通道的的特征尺寸较小，可以有效提高单位面积内所述半导体通道的个数，进而可以提高互连密度以及芯片的带宽，并控制芯片封装的面积。并且，相较于现有技术中制作在绝缘材料中的制作TIV，在所述半导体板中制作所述半导体通道的成本更低，且制作工艺更为成熟。
另外，由于所述芯片中在所述半导体板中制作所述半导体通道，相较于现有技术所述芯片中填充的绝缘材料较少，当所述半导体板材料与所述第一裸片以及所述第二裸片的材料的热膨胀系数接近时，可以降低所述芯片翘曲的风险。
一种可能的实施方式中，所述第一裸片可以为逻辑裸片(logic die)，如处理器或知识产权IP核，所述第二裸片可以为存储器(包括随机存储器SRAM和动态随机存储器DRAM)，微机电系统MEMS、无源器件或转接板等；或者，所述第一裸片可以为存储器，MEMS、无源器件或转接板等，所述第二裸片可以为逻辑裸片，如处理器或知识产权核。所述半导体板可以为硅板或硅桥，所述半导体通道可以为硅通孔TSV。所述布线层可以为扇出再布线FO-RDL层或者Mz金属布线层。
一种可能的实施方式中，所述第一裸片的有源面以及所述第二裸片的有源面均朝向所述布线层，所述第二裸片的有源面以及所述第一裸片的无源面上设置有多个接垫；所述第二裸片通过所述多个接垫中的一部分与所述第一半导体通道耦合，所述第二裸片通过所述多个接垫中的另一部分与所述第一裸片耦合。
一种可能的实施方式中，所述第一裸片的有源面朝向所述布线层，所述第二裸片的有源面朝向所述第一裸片，所述第二裸片的有源面以及所述第一裸片的有源面上设置有多个接垫；所述第二裸片通过所述多个接垫中的一部分与所述第一半导体通道耦合，所述第二裸片通过所述多个接垫中的另一部分与所述第一裸片耦合。
一种可能的实施方式中，所述第一裸片的半导体基板中设置有第二半导体通道，所述第一裸片还通过所述第二半导体通道与所述第二裸片以及所述布线层耦合，进而能够有效缩短所述第一裸片与所述第二裸片之间信号传输的路径，提升芯片的响应速度。
一种可能的实施方式中，为了降低所述芯片的翘曲风险，所述第一裸片中半导体基板的材料、所述第二裸片中半导体基板的材料与所述半导体板的热膨胀系数相同(或相近)。例如，所述第一裸片中半导体基板、所述第二裸片中半导体基板与所述半导体板采用相同的材料。
一种可能的实施方式中，所述芯片还包括绝缘材料，所述绝缘材料包裹所述第一裸片、所述半导体板以及所述第二裸片。
进一步地，所述绝缘材料包括第一绝缘材料和第二绝缘材料，其中，所述第一绝缘材料包裹所述第一裸片和所述半导体板，所述第二绝缘材料包裹所述第二裸片。其中，所述第一绝缘材料可以为氧化硅或者氮化硅。所述第二绝缘材料除了可以用氧化硅或者氮化硅，在一些对芯片封装体厚度要求不高的场景下，也可以使用底部填充胶、模塑料或者其他环氧树脂，进而可以有效降低芯片封装过程中绝缘材料的制作难度。另外，使用底部填充胶、模塑料或者其他环氧树脂作为所述第二绝缘材料，封装体的厚度较厚，在制作布线层时，不需要硅载片，工艺简单，成本低。
一个可能的实施方式中，所述芯片还包括焊球，所述焊球设置在所述布线板下面，用于实现所述第一裸片以及所述第二裸片与外部(如印刷电路板PCB、其它芯片等)的互连，使得所述芯片可以直接通过所述焊球与外部互连，不需要基板，进而降低了所述芯片的封装厚度，同时提高了散热性能。
一个可能的实施方式中，所述芯片包括至少两个所述第一裸片，或者，包括至少两个所述第二裸片，或者，包括至少两个所述第一裸片和至少两个所述第二裸片。其中，所述多个第一裸片可以分布在同一层，也可以分布在不同层，所述多个第二裸片可以分布在同一层，也可以分布在不同层。
一个可能的实施方式中，所述至少两个第一裸片堆叠设置，相邻两个所述第一裸片的有源面相互耦合。
一个可能的实施方式中，所述至少两个第二裸片堆叠设置，相邻两个所述第二裸片的有源面相互耦合。
第二方面，本申请提供了一种集成芯片，所述集成芯片包括第一芯片和第二芯片，所述第一芯片为上述第一方面任意一种可能的实施方式中所述的芯片，所述第一芯片与所述第二芯片封装在一起。
一个可能的实施方式中，所述第一芯片可以通过堆叠封装POP的方式与所述第二芯片封装在一起。
第三方面，本申请提供了一种芯片封装方法，所述方法包括：将半导体板以及第一裸片键合在第一载片上；其中，所述半导体板中加工有第一半导体通道；将第二裸片与所述半导体板以及所述第一裸片键合在一起；去掉所述第一载片，在所述半导体板及所述第一裸片与所述第一载片键合的面上制备布线层；其中，所述第二裸片通过所述第一半导体通道与所述布线层耦合。
一个可能的实施方式中，将第二裸片与所述半导体板以及所述第一裸片键合在一起，具体包括：制备第一绝缘材料，以形成第一封装体；其中，所述第一绝缘材料包裹所述半导体板及所述第一裸片；在所述第一绝缘材料上制备多个接垫，以形成第二封装体；将第二裸片通过所述多个接垫的一部分与所述第一半导体通道耦合，通过所述多个接垫中的另一部分与所述第一裸片耦合，以形成第三封装体。
一个可能的实施方式中，制备第一绝缘材料之后，在所述第一绝缘材料上制备多个接垫之前，还要对所述第一绝缘材料进行抛光，露出所述半导体板中的第一半导体通道。具体地，可以采用化学机械抛光CMP方式进行抛光。
一个可能的实施方式中，在所述第一绝缘材料上制备多个接垫之后，将第二裸片通过所述多个接垫的一部分与所述第一半导体通道耦合，通过所述多个接垫中的另一部分与所述第一裸片耦合之前，还可以进行抛光(如CMP)处理，将所述多个接垫上多余的键合介质层结构抛掉。
一个可能的实施方式中，将半导体板以及第一裸片键合在第一载片上之后，制备第一绝缘材料之前，还可以将所述半导体板以及所述第一裸片减薄到相同厚度。
一个可能的实施方式中，若第二绝缘材料的厚度小于设定值，在所述半导体板及所述第一裸片与所述第一载片键合的面上制备布线层之前，还将所述第四封装体键合到第二载片上；在所述半导体板及所述第一裸片与所述第一载片键合的面上制备布线层之后，去掉所述第二载片。
一个可能的实施方式中，在所述半导体板及所述第一裸片与所述第一载片键合的面上制备布线层之后，还可以在所述布线层的下面制作多个焊球。
附图说明
图1为现有采用HB技术的3D IC封装的芯片结构示意图；
图2为本申请实施例提供的一种芯片的结构示意图之一；
图3为本申请实施例提供的裸片的结构示意图；
图4为本申请实施例提供的一种芯片的结构示意图之二；
图5a为本申请实施例提供的一种芯片的结构示意图之三；
图5b为本申请实施例提供的一种芯片的结构示意图之四；
图6为本申请实施例提供的一种芯片的结构示意图之五；
图7为本申请实施例提供的一种芯片的结构示意图之六；
图8为本申请实施例提供的一种芯片的结构示意图之七；
图9a为本申请实施例提供的一种集成芯片的结构示意图；
图9b为本申请实施例提供的另一种集成芯片的结构示意图；
图10为本申请实施例提供的一种芯片封装方法的流程示意图；
图11为本申请实施例提供的另一种芯片封装方法的流程示意图；
图12为本申请具体实施例提供的一种芯片封装方法的流程示意图。
具体实施方式
为了满足高互连密度芯片封装的要求，业界开始采用混合键合(hybrid bonding，HB)技术进行芯片封装。如图1所示，常见的采用HB技术的三维集成电路(3-Dimentional Integrated Circuit，3D IC)封装的芯片结构由上层100、下层200以及布线层300(redistribution layer,RDL)和焊球400组成，上层100和下层200通过混合键合结构500键合在一起。其中，上层100包括上层裸片(die)101以及填充材料102，下层200包括下层裸片201和填充材料202，填充材料202中制作有绝缘层通孔(through insulator via，TIV)203，上层裸片101的有源面103通过混合键合结构500以及TIV 203与布线层300连接，下层裸片201的有源面204与布线层300连接，焊球400用于实现上层裸片101、下层裸片201与外部印刷电路板(printed circuit board，PCB)实现互连。
上层裸片101与布线层300通过填充材料202中的TIV 203实现垂直互连，而现有的工艺技术能力条件下所制作的TIV的特征尺寸大，互连密度低，从而限制了芯片中垂直互连通道个数，进而限制了上层裸片的带宽。如果芯片封装要求达到一定数量的绝缘层通孔(TIV)，必须增大芯片封装的面积。并且，在现有的工艺技术能力条件下，TIV的制作工艺不成熟，成本高，会导致封装后的芯片良率不高。
为了解决现有芯片封装结构中存在的上述问题，本申请提出了一种芯片以及芯片封装方法，以增加单位面积内芯片中互连通道的数目，进而提升芯片的带宽，并控制芯片封装的成本。
需要说明的是，本申请实施例中所涉及的多个，是指两个或两个以上。另外，需要理解的是，在本申请实施例的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
如图2所示，本申请实施例提供的一种芯片200包括：布线层210，第一裸片220、半导体板230以及第二裸片240。其中，所述第一裸片220以及所述半导体板230设置在所述布线层210上，所述半导体板230中设置有第一半导体通道231；所述第二裸片240设置在所述第一裸片220以及所述半导体板230上，所述第二裸片240通过所述第一半导体通道231与所述布线层210耦合。
裸片(die)是IC未封装前的晶粒，每一个裸片就是一个独立的功能尚未封装的芯片，它可由一个或多个电路组成。如图3所示，裸片通常由半导体基板和布设于半导体基板上 的电路层组成，所述半导体基板上形成有晶体管等半导体器件，所述电路层中设置有多层的电路层，所述电路层通常设置有各种功能电路，这些电路与半导体基板上的半导体器件耦合，从而构成完整的芯片电路结构。其中，裸片中的电路层所处的一侧的表面称为有源面，裸片中的半导体基板所处的一侧的表面称为无源面。
具体地，所述第一裸片220可以为逻辑裸片(logic die)，如处理器或知识产权(intellectual property，IP)核(Cores)，所述第二裸片240可以为存储器(包括随机存储器(static random-access memory，SRAM)和动态随机存储器(dynamic random access memory，DRAM))，微机电系统(micro-electro-mechanical system，MEMS)、无源器件(passive device)或转接板(interposer)等；或者，所述第一裸片220可以为存储器，MEMS、无源器件或转接板等，所述第二裸片240可以为逻辑裸片，如处理器或知识产权核。所述半导体板230可以为硅板或硅桥(dummy si bridge)，所述半导体通道231可以为硅通孔(through silicon via，TSV)，半导体通道231中涂镀有金属层或者填充有金属柱，因而半导体通道能够作为信号路径，现有技术中的TIV也是类似情况。所述布线层210可以为扇出再布线(fan out redistribution layer，FO-RDL)层或者普通的布设有信号走线的金属布线层。
需要说明的是，本申请并不对所述半导体板230的具体形状进行限定，所述半导体板的形状不限于扁平板状结构，凡是能够制作所述半导体通道231，通过所述半导体通道231实现所述第二裸片240与所述布线层210以及所述第一裸片220耦合的半导体板均适用于本申请。
具体实施中，所述第二裸片240可以通过但不限于以下两种方式中的任意一种，与所述半导体板230中的半导体通道231以及所述第一裸片220耦合：
方式一、如图2所示，所述第一裸片220的有源面221朝向所述布线层210，所述第二裸片240的有源面241朝向所述第一裸片220，所述第二裸片240的有源面241以及所述第一裸片220的有源面221上设置有多个接垫(pad)250。所述第二裸片240通过所述多个接垫250中的一部分与所述第一半导体通道231耦合，所述第二裸片240通过所述多个接垫250中的另一部分与所述第一裸片220耦合。
方式二、如图4所示，所述第一裸片220的有源面221以及所述第二裸片240的有源面241均朝向所述布线层210，所述第二裸片240的有源面241以及所述第一裸片220的无源面222上设置有多个接垫250。所述第二裸片240通过所述多个接垫250中的一部分与所述第一半导体通道231耦合，所述第二裸片240通过所述多个接垫250中的另一部分与所述第一裸片220耦合。
需要说明的是，部分的所述接垫250可以与所述第一半导体通道231垂直对应，所述接垫250也可以不与所述第一半导体通道231垂直对应，通过布线的方式与所述第一半导体通道231实现互连。
进一步地，如图5a或图5b所示，所述第一裸片220的半导体基板中设置有第二半导体223通道，所述第一裸片220还通过所述第二半导体通道223与所述第二裸片240以及所述布线层210耦合，进而能够有效缩短所述第一裸片220与所述第二裸片220之间信号传输的路径，提升芯片的响应速度。
现有技术中制作TIV是形成在绝缘材料中，绝缘材料通常为氧化硅或者氮化硅，裸片的周围也通常都是被所述绝缘材料包裹。而裸片的半导体基板的材料主要是硅(Silicon)，裸片的半导体基板和绝缘材料的热膨胀系数不匹配，导致整个芯片在封装的过程中存在较 大的翘曲(warpage)风险。而本发明通过将半导体板设置在第二裸片240和布线层230之间，减小了裸片周围或者裸片之间的绝缘材料的体积。无论是裸片还是半导体板都是可以通过预加工的工艺制作出的实体，其形态和应力较在封装过程中填充的绝缘材料更为稳固，进而通过半导体板来替代绝缘材料，也就减小在封装中能够产生的应力，降低了翘曲风险。为了进一步的降低所述芯片200的翘曲风险，所述第一裸片220中半导体基板的材料、所述第二裸片240中半导体基板的材料与所述半导体板230的热膨胀系数相同(或相近)。由于裸片中电路层比较薄，大部分都是半导体基板(如图3所示)，因此所述第一裸片220中半导体基板的材料、所述第二裸片240中半导体基板的材料与所述半导体板230的热膨胀系数匹配时，可以使得所述第一裸片220、所述半导体板230以及所述第二裸片240在相同条件下的变形基本相同，进一步降低所述芯片200的翘曲风险。例如，所述第一裸片220中半导体基板、所述第二裸片240中半导体基板与所述半导体板230采用相同的材料。
本申请实施例中并不对所述芯片200中的第一裸片220、半导体板230以及半导体板230中半导体通道231的个数，还有所述第二裸片240的个数，以及第一裸片220、半导体板230以及所述第二裸片240的排布方式进行限定，图2所示的芯片结构仅为举例说明，并不对本申请构成限定。所述芯片200中的第一裸片220、半导体板230以及半导体板230中半导体通道231的个数，以及所述第二裸片240的个数根据所述芯片200的具体性能(如带宽、面积、处理速度等)要求确定，例如要求所述芯片200具有较大的带宽，所述芯片200可以包括较多的半导体板230以及半导体通道231。
一个可能的实施方式中，所述芯片220包括至少两个所述第一裸片220，或者，包括至少两个所述第二裸片240，或者，包括至少两个所述第一裸片220和至少两个所述第二裸片240。其中，所述多个第一裸片210可以分布在同一层，也可以分布在不同层，所述多个第二裸片240可以分布在同一层(例如，图2中的第二裸片240)，也可以分布在不同层。
具体地，当所述多个第一裸片210分布在不同层时，所述至少两个第一裸片210可以堆叠设置，相邻两个所述第一裸片210的有源面相互耦合。其中，相邻两个所述第一裸片210中，上层第一裸片的有源面可以通过下层第一裸片中设置的半导体通道(如TSV)与下层第一裸片的有源面耦合。
当所述多个第二裸片240分布在不同层时，所述至少两个第二裸片240可以堆叠设置，相邻两个所述第二裸片240的有源面相互耦合，如图6所示。其中，相邻两个所述第二裸片240中，上层第二裸片的有源面可以通过下层第二裸片中设置的半导体通道(如TSV)与下层第二裸片的有源面耦合。
需要说明的是，本申请实施例中并不对堆叠设置的至少两个所述第一裸片220中每个第一裸片220的有源面(或无源面)的方向，以及堆叠设置的至少两个所述第二裸片240中每个第二裸片240的有源面(或无源面)的方向进行限定。例如，至少两个所述第一裸片220中每个第一裸片220的有源面可以均朝向所述布线层210，或者，至少两个所述第一裸片220中每个第一裸片220的无源面均朝向所述布线层210；或者，至少两个所述第一裸片220中一部分第一裸片220的无源面朝向所述布线层210，另一部分第一裸片220的有源面朝向所述布线层210。至少两个所述第二裸片240中每个第二裸片220的有源面(或无源面)的方向与上述第一裸片220类似，此处不再赘述。
具体实施中，如图2所示，所述芯片200还包括绝缘材料260，所述绝缘材料260包 裹所述第一裸片220、所述半导体板230以及所述第二裸片240。进一步地，如图7所示，所述绝缘材料260包括第一绝缘材料261和第二绝缘材料262，其中，所述第一绝缘材料261包裹所述第一裸片220和所述半导体板230，所述第二绝缘材料262包裹所述第二裸片240。
在芯片封装过程中，通常对所述第一绝缘材料261的厚度要求较高，因此所述第一绝缘材料261一般采用氧化硅(Silicon Oxide)或者氮化硅(Nitride Oxide)。对于所述第二绝缘材料262，除了可以用氧化硅或者氮化硅，在一些对芯片封装体厚度要求不高的场景下，也可以使用底部填充胶(underfill)、模塑料(molding compound)或者其他环氧树脂(epoxy)，进而可以有效降低芯片封装过程中绝缘材料的制作难度。另外，使用底部填充胶、模塑料或者其他环氧树脂作为所述第二绝缘材料262，封装体的厚度较厚，在制作布线层时，不需要硅载片(support silicon)，工艺简单，成本低。
进一步地，如图8所示，所述芯片200还包括焊球270，所述焊球270设置在所述布线板210下面，用于实现所述第一裸片210以及所述第二裸片240与外部(如PCB、其它芯片等)的互连，使得所述芯片200可以直接通过所述焊球270与外部互连，不需要基板，进而降低了所述芯片200的封装厚度，同时提高了散热性能。
通过上述方案，所述芯片200中第一裸片以及半导体板230设置在布线层210，第二裸片240设置在所述第一裸片220以及所述半导体板230上，所述第二裸片240通过半导体板230中的半导体通道231与所述布线层210耦合，使得所述第二裸片240能够通过所述半导体通道231以及所述布线层210，实现与所述第一裸片220互连。相较于现有技术中制作在绝缘材料中的制作TIV，在所述半导体板230中制作所述半导体通道231的的特征尺寸较小，可以有效提高单位面积内所述半导体通道的个数，进而可以提高互连密度以及芯片的带宽，并控制芯片封装的面积。并且，相较于现有技术中制作在绝缘材料中的制作TIV，在所述半导体板230中制作所述半导体通道231的成本更低，且制作工艺更为成熟。
另外，由于所述芯片200中在所述半导体板230中制作所述半导体通道231，相较于现有技术所述芯片200中填充的绝缘材料较少，当所述半导体板230材料与所述第一裸片220以及所述第二裸片240的材料的热膨胀系数接近时，可以降低所述芯片200翘曲的风险。
基于以上实施例，本申请还提供了一种集成芯片，所述集成芯片包括第一芯片和第二芯片，所述第一芯片为上述然以一种可能的实施方式中所述的芯片200，所述第一芯片与所述第二芯片封装在一起。
其中，所述第一芯片可以通过堆叠封装(package on package，POP)与所述第二芯片封装在一起。例如，如图9a所示，所述第一芯片可以通过FOWLP方式与所述第二芯片封装在一起，或者，所述第一芯片也可以通过其它的POP方式与所述第二芯片封装在一起，如图9b所示。
基于以上实施例，本申请还提供了一种芯片封装方法，用于封装形成上述芯片200，如图10所示，所述方法主要包括以下步骤：
S1001：将第一裸片220以及半导体板230键合在第一载片上；其中，所述半导体板230中加工有第一半导体通道231；
S1002：将第二裸片240与所述半导体板230以及所述第一裸片220键合在一起；
S1003：去掉所述第一载片，在所述半导体板230及所述第一裸片220与所述第一载片键合的面上制备布线层210；其中，所述第二裸片240通过所述第一半导体231通道与所述布线层210耦合。
在步骤1002中，将第二裸片240与所述半导体板230以及所述第一裸片220键合在一起，具体包括：
i、制备第一绝缘材料261，以形成第一封装体；其中，所述第一绝缘材料261包裹所述半导体板230及所述第一裸片220；
ii、在所述第一绝缘材料261上制备多个接垫250，以形成第二封装体；
其中，可以通过光刻、电镀工艺制作所述接垫(pad)250，作为HB金属结构，通过化学气相沉积(chemical vapor deposition，CVD)工艺制作HB键合层介质层结构。
iii、将第二裸片240通过所述多个接垫250的一部分与所述第一半导体通道231耦合，通过所述多个接垫250中的另一部分与所述第一裸片220耦合，以形成第三封装体。所述第二裸片上也制备由多个所述接垫，用于与所述第二封装体进行键合。
其中，制备第一绝缘材料261之后，在所述第一绝缘材料261上制备多个接垫250之前，还要对所述第一绝缘材料261进行抛光，露出所述半导体板230中的第一半导体通道231。具体地，可以采用化学机械抛光(chemical mechanical polishing，CMP)方式进行抛光。
在所述第一绝缘材料261上制备多个接垫之后，将第二裸片240通过所述多个接垫250的一部分与所述第一半导体通道231耦合，通过所述多个接垫250中的另一部分与所述第一裸片220耦合之前，还可以进行抛光(如CMP)处理，将所述多个接垫250上多余的键合介质层结构抛掉。
进一步地，由于所述半导体板230的厚度与所述第一裸片220的厚度不一定相同，在执行步骤S1001之后，制备第一绝缘材料261之前，还将所述半导体板以及所述第一裸片减薄到相同厚度。
由于只能对所述第一裸片220的无源面进行减薄处理，在封装形成如图2所示的芯片时，进行减薄处理后，将所述半导体板230以及所述第一裸片220减薄处理后的表面键合在第三载片上，使得所述第一裸片220的有源面向上，并去掉所述第一载片，然后再继续后续的封装流程。
在执行步骤S1002之后，执行步骤S1003之前，还制备第二绝缘材料262，以形成第四封装体；其中，所述第二绝缘材料262包裹所述第二裸片240。其中，制备第二绝缘材料262之后，还可以对所述第二绝缘材料262进行抛光处理。
具体地，若第二绝缘材料262的厚度小于设定值，在所述半导体板230及所述第一裸片220与所述第一载片键合的面上制备布线层210之前，还将所述第四封装体键合到第二载片上；在所述半导体板230及所述第一裸片220与所述第一载片键合的面上制备布线层210之后，去掉所述第二载片，如图11所示。
另外，执行步骤S1003之后，还可以在所述布线层的下面制作多个焊球。
下面以封装形成如图4所示的芯片200为例，对本申请提供的芯片封装方法进行详细说明。
封装形成如图4所示的芯片200主要包括以下步骤：
S1201：将半导体板230以及第一裸片220键合在第一载片上；其中，所述半导体板 230中加工有第一半导体通道231。
S1202：将所述半导体板230以及所述第一裸片减薄到相同厚度(通常减薄至20微米左右)。
S1203：制备第一绝缘材料261，所述第一绝缘材料261可以是氧化硅或氮化硅。
S1204：进行CMP处理，抛掉多余的所述第一绝缘材料261，露出所述半导体板230中的半导体通道231。
S1205：在CMP后的表面上制备多个接垫250，作为HB键合结构。其中，HB键合结构包括HB键合层金属结构以及HB键合层介质结构。
S1206：进行CMP处理，抛掉多余的HB键合层介质结构。
S1207：利用HB技术将第二裸片240键合在步骤6得到的封装体上。其中，所述第二裸片240进行键合的面上也制备有多个接垫250，作为HB键合结构，以使键合后所述第二裸片240能够与所述半导体板230中的半导体通道231互连。
S1208：制备第二绝缘层262。其中，所述第二绝缘层262的厚度大于所述设定值。
S1209：去掉所述第一载片，制备布线层210以及焊球270。
封装形成如图2所示的芯片200的过程，除了在上述步骤S1202之后，将所述半导体板230以及所述第一裸片220减薄处理后的表面键合在第三载片上，使得所述第一裸片220的有源面向上，并去掉所述第一载片，然后再继续后续的封装流程，与S1203-S1209的过程相似，此处不再赘述。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (13)

  1. 一种芯片，其特征在于，包括：布线层；
    设置在所述布线层上的第一裸片以及半导体板；其中，所述半导体板中设置有第一半导体通道；
    设置在所述第一裸片以及所述半导体板上的第二裸片；其中，所述第二裸片通过所述第一半导体通道与所述布线层耦合。
  2. 如权利要求1所述的芯片，其特征在于，所述第一裸片的有源面以及所述第二裸片的有源面均朝向所述布线层，所述第二裸片的有源面以及所述第一裸片的无源面上设置有多个接垫；
    所述第二裸片通过所述多个接垫中的一部分与所述第一半导体通道耦合，所述第二裸片通过所述多个接垫中的另一部分与所述第一裸片耦合。
  3. 如权利要求1所述的芯片，其特征在于，所述第一裸片的有源面朝向所述布线层，所述第二裸片的有源面朝向所述第一裸片，所述第二裸片的有源面以及所述第一裸片的有源面上设置有多个接垫；
    所述第二裸片通过所述多个接垫中的一部分与所述第一半导体通道耦合，所述第二裸片通过所述多个接垫中的另一部分与所述第一裸片耦合。
  4. 如权利要求1-3任意一项所述的芯片，其特征在于，所述第一裸片的半导体基板中设置有第二半导体通道，所述第一裸片还通过所述第二半导体通道与所述第二裸片以及所述布线层耦合。
  5. 如权利要求1-4任意一项所述的芯片，其特征在于，所述第一裸片中半导体基板的材料、所述第二裸片中半导体基板的材料与所述半导体板的材料的热膨胀系数相同。
  6. 如权利要求1-5任意一项所述的芯片，其特征在于，所述芯片包括至少两个所述第一裸片；和/或，所述芯片包括至少两个所述第二裸片。
  7. 如权利要求6所述的芯片，其特征在于，所述至少两个第一裸片堆叠设置，相邻两个所述第一裸片的有源面相互耦合。
  8. 如权利要求6所述的芯片，其特征在于，所述至少两个第二裸片堆叠设置，相邻两个所述第二裸片的有源面相互耦合。
  9. 如权利要求1-8任意一项所述的芯片，其特征在于，还包绝缘材料，所述绝缘材料包裹所述第一裸片、所述半导体板以及所述第二裸片。
  10. 如权利要求9所述的芯片，其特征在于，所述绝缘材料包括第一绝缘材料和第二绝缘材料，其中，所述第一绝缘材料包裹所述半导体板及所述第一裸片，所述第二绝缘材料包裹所述第二裸片。
  11. 一种集成芯片，其特征在于，包括第一芯片和第二芯片，所述第一芯片为如权利要求1-9任意一项所述的芯片，所述第一芯片与所述第二芯片封装在一起。
  12. 一种芯片封装方法，其特征在于，包括：
    将半导体板以及第一裸片键合在第一载片上；其中，所述半导体板中加工有第一半导体通道；
    将第二裸片与所述半导体板以及所述第一裸片键合在一起；
    去掉所述第一载片，在所述半导体板及所述第一裸片与所述第一载片键合的面上制备 布线层；其中，所述第二裸片通过所述第一半导体通道与所述布线层耦合。
  13. 如权利要求12所述的方法，其特征在于，将第二裸片与所述半导体板以及所述第一裸片键合在一起，包括：
    制备第一绝缘材料，以形成第一封装体；其中，所述第一绝缘材料包裹所述半导体板及所述第一裸片；
    在所述第一绝缘材料上制备多个接垫，以形成第二封装体；
    将第二裸片通过所述多个接垫的一部分与所述第一半导体通道耦合，通过所述多个接垫中的另一部分与所述第一裸片耦合，以形成第三封装体。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114171406A (zh) * 2021-12-08 2022-03-11 通富微电子股份有限公司 扇出式堆叠芯片的封装方法及封装结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110037157A1 (en) * 2009-08-17 2011-02-17 Shin Hangil Integrated circuit packaging system with package-on-package and method of manufacture thereof
CN106252324A (zh) * 2015-06-09 2016-12-21 华亚科技股份有限公司 封装上封装堆叠封装构件
CN106486383A (zh) * 2015-08-31 2017-03-08 台湾积体电路制造股份有限公司 封装结构及其制造方法
CN107785358A (zh) * 2016-08-25 2018-03-09 Imec 非营利协会 半导体管芯封装及生产这种封装的方法
CN207149555U (zh) * 2017-07-25 2018-03-27 华天科技（昆山）电子有限公司 薄型3d扇出封装结构

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102593087B (zh) * 2012-03-01 2014-09-03 华进半导体封装先导技术研发中心有限公司 一种用于三维集成混合键合结构及其键合方法
US9972603B2 (en) * 2015-12-29 2018-05-15 Taiwan Semiconductor Manufacturing Co., Ltd. Seal-ring structure for stacking integrated circuits

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110037157A1 (en) * 2009-08-17 2011-02-17 Shin Hangil Integrated circuit packaging system with package-on-package and method of manufacture thereof
CN106252324A (zh) * 2015-06-09 2016-12-21 华亚科技股份有限公司 封装上封装堆叠封装构件
CN106486383A (zh) * 2015-08-31 2017-03-08 台湾积体电路制造股份有限公司 封装结构及其制造方法
CN107785358A (zh) * 2016-08-25 2018-03-09 Imec 非营利协会 半导体管芯封装及生产这种封装的方法
CN207149555U (zh) * 2017-07-25 2018-03-27 华天科技（昆山）电子有限公司 薄型3d扇出封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114171406A (zh) * 2021-12-08 2022-03-11 通富微电子股份有限公司 扇出式堆叠芯片的封装方法及封装结构

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