WO2020237685A1 - 一种芯片以及集成芯片 - Google Patents

一种芯片以及集成芯片 Download PDF

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Publication number
WO2020237685A1
WO2020237685A1 PCT/CN2019/089691 CN2019089691W WO2020237685A1 WO 2020237685 A1 WO2020237685 A1 WO 2020237685A1 CN 2019089691 W CN2019089691 W CN 2019089691W WO 2020237685 A1 WO2020237685 A1 WO 2020237685A1
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WO
WIPO (PCT)
Prior art keywords
chip
pins
layer
integrated
interconnection
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Application number
PCT/CN2019/089691
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English (en)
French (fr)
Inventor
张晓东
张童龙
官勇
李珩
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2019/089691 priority Critical patent/WO2020237685A1/zh
Priority to CN201980097019.3A priority patent/CN113939911A/zh
Publication of WO2020237685A1 publication Critical patent/WO2020237685A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • This application relates to the technical field of chip packaging, and in particular to a chip and an integrated chip.
  • the package on package (POP) technology is relatively mature and has high feasibility, can greatly improve the integration of chip packaging, and has higher benefits.
  • the upper chip and the lower chip of the integrated chip packaged with stacked packaging technology are interconnected through solder balls, wiring layers, vertical interconnection structures, and substrates.
  • the interconnection traces are long, resulting in The bandwidth of chips formed after stacking and packaging is small.
  • the common structure of integrated chips using stacked packaging technology is shown in Figure 1.
  • the upper chip is located above the lower chip, and the upper chip passes through solder balls, interconnection layer (wiring layer or substrate), vertical interconnection structure, fan-out wiring
  • the layer (fan out redistribution layer, FO-RDL), copper stud (copper stud) and the underlying chip are electrically interconnected.
  • the upper layer chip may be a dynamic random access memory (DRAM) chip
  • the lower layer chip may be a system on chip (SOC)
  • the DRAM chip is usually packaged directly purchased from a memory manufacturer DRAM package.
  • Multiple bare dies in the packaged memory are connected between different layers of bare dies through wire bonding (WB) or through silicon via (TSV) technologies. Interconnect to form a package body through plastic packaging.
  • the upper and lower chips are electrically interconnected through solder balls, interconnection layers, vertical interconnection structures, fan-out wiring layers and small copper pillars, and the interconnection path is long, resulting in a packaged integrated chip The bandwidth is small.
  • the lower-layer chips have begun to have the demand for multi-chip integration.
  • a memory chip will be packaged for the SOC in the lower chip. In this way, the data with high transmission rate required by the SOC can be stored in the memory chip in the lower chip without accessing the upper DRAM chip.
  • the packaging of the SOC and the memory chip in the lower chip is usually superimposed, for example, the SOC is set on the top of the memory chip, the active surface of the SOC is attached to the silicon layer of the memory chip, and then the SOC is placed on the memory chip.
  • the TSV is applied to the silicon layer to realize the interconnection between the SOC and the active surface of the memory chip.
  • This application provides a chip and an integrated chip to solve the problems of the prior art that the upper and lower chips in the packaged chip need to be interconnected by TSV method, which leads to high warpage risk, design complexity and difficulty in manufacturing process in the lower chip structure. .
  • the present application provides an integrated chip including an interconnection layer, a first chip, a second chip and a first vertical interconnection structure arranged on the interconnection layer.
  • the second chip includes a first part and a second part. The first part is arranged on the top surface of the first chip, and the second part protrudes from the side of the first chip; the first vertical interconnection structure is arranged on the top surface of the first chip. On the side, the second part of the second chip is electrically connected to the interconnection layer through the first vertical interconnection structure.
  • first chip and the second chip are arranged staggered, the first vertical interconnection structure and the second part of the second chip are arranged on the same side of the first chip, and the second part of the second chip bypasses the first chip and passes through the A vertical interconnect structure is electrically connected to the interconnect layer.
  • the second chip in the integrated chip is electrically connected to the first chip arranged on the interconnection layer through the first vertical interconnection structure, which can shorten the interconnection path between the second chip and the first chip as much as possible.
  • the second part of the second chip bypasses the first core and is electrically connected to the interconnection layer through the first vertical interconnection structure, so that there is no need to make TSVs in the first chip and the second chip, which can reduce the integrated chip.
  • the first chip and the second chip may be any combination of a processor chip and a memory chip, for example, the first chip is a processor chip, the second chip is a memory chip, or the first chip is a memory The second chip is a processor chip. In an alternative embodiment, the first chip and the second chip may also be any combination of other types of chips.
  • the structure of the integrated chip is a common stacked packaging structure, which has low technical risk and high technical feasibility, and has good packaging integration performance, making it easy for other chips to be packaged together.
  • the first vertical interconnection structure is a plurality of solder balls, or a plurality of copper pillars, or a plurality of molded vias TMV, or a plurality of dielectric layer vias TDV, or a plurality of Insulating layer through hole TIV.
  • One end of the first vertical interconnection structure is directly connected to the bottom of the second part of the second chip, and the other end of the first vertical interconnection structure is directly connected to the conductive layer in the interconnection layer.
  • data transmission pins are provided on the second chip, and all signal transmission pins on the second chip are provided at the bottom of the second part of the second chip, which can shorten the first chip and the second chip.
  • the data transmission path between them can increase the bandwidth of the integrated chip.
  • the pins of the first chip for connecting with the pins of the second chip can be arranged on the side of the first chip close to the second part of the second chip, so as to minimize the length of the first chip and the second chip.
  • the interconnection path to improve the bandwidth of the integrated chip.
  • the second chip is further provided with power supply pins, and the power supply pins on the second chip are all provided at the bottom of the second part of the second chip.
  • the data transmission pins and power supply pins of the second chip are distributed in an array to form a first pin array.
  • all the pins in any column of the first pin array are of the same type, and the types of pins in any two adjacent columns of the first pin array are different, that is, the types of pins in any two adjacent columns of the first pin array are different.
  • One column is signal transmission pins, and the other column is power supply pins; or, all pins in any row in the first pin array are of the same type, and any two adjacent rows in the first pin array are The types of pins are different, that is, in any two adjacent rows of the first pin array, one row is a signal transmission pin, and the other row is a power supply pin.
  • the signal transmission pins of the chip Compared with the power supply pins of the chip, the signal transmission pins of the chip have a larger area. Therefore, the signal transmission pins and the power supply pins of the second chip are distributed in rows or columns, which can reduce the number of pins in the second chip. The occupied area can further increase the number of pins per unit area of the second chip to meet the requirements of high chip integration. At the same time, the signal transmission pins and power supply pins of the second chip are arranged at intervals of rows or columns, which can separate the signal transmission pins of different columns, reduce the mutual influence between the signal transmission pins, and improve the signal transmission quality.
  • the first chip may be a processor chip
  • the second chip may be a memory chip
  • the first part of the second chip is fixed on the top surface of the first chip by an adhesive material.
  • the sticking material can be a chip adhesive or silver paste.
  • the integrated chip includes at least two first chips; or, the integrated chip includes at least two second chips; or, the integrated chip includes at least two first chips and at least two second chips.
  • the integrated chip further includes a third chip and a second vertical interconnection structure.
  • the third chip includes a third part and a fourth part, the third part is fixed on the top surface of the second chip, and the fourth part protrudes from the side of the second chip; the second vertical interconnection structure is arranged at On the side of the second chip, the fourth part of the third chip is electrically connected to the interconnection layer through the second vertical interconnection structure.
  • the second vertical interconnection structure is a plurality of solder balls, or a plurality of copper pillars, or a plurality of molded vias TMV, or a plurality of dielectric layer vias TDV, or a plurality of Insulating layer through hole TIV.
  • One end of the second vertical interconnect structure is directly connected to the bottom of the fourth part of the third chip, and the other end of the second vertical interconnect structure is directly connected to the conductive layer in the interconnect layer.
  • data transmission pins are provided on the third chip, and all signal transmission pins on the third chip are provided at the bottom of the fourth part of the third chip, which can shorten the first chip and the third chip.
  • the data transmission path between them can increase the bandwidth of the integrated chip.
  • the pins of the first chip for connecting with the pins of the third chip may be arranged on the side of the first chip close to the fourth part of the third chip, so as to minimize the length of the first chip and the third chip.
  • the interconnection path to improve the bandwidth of the integrated chip.
  • the third chip is further provided with power supply pins, and the power supply pins on the third chip are all provided at the bottom of the fourth part of the second chip.
  • the data transmission pins and power supply pins of the third chip are distributed in an array to form a second pin array.
  • all the pins in any column of the second pin array are of the same type, and the types of pins in any two adjacent columns of the second pin array are different, that is, any two adjacent columns of the second pin array Among them, one column is signal transmission pins, and the other column is power supply pins; or, all pins in any row in the second pin array are of the same type, and in any two adjacent rows in the second pin array
  • the types of pins are different, that is, in any two adjacent rows of the second pin array, one row is a signal transmission pin, and the other row is a power supply pin.
  • the signal transmission pins of the chip Compared with the power supply pins of the chip, the signal transmission pins of the chip have a larger area. Therefore, the signal transmission pins and power supply pins of the third chip are distributed in rows or columns, which can reduce the number of pins in the third chip. The occupied area can further increase the number of pins per unit area of the third chip to meet the requirements of high chip integration. At the same time, the signal transmission pins and power supply pins of the third chip are arranged at intervals of rows or columns, which can separate the signal transmission pins of different columns, reduce the mutual influence between the signal transmission pins, and improve the signal transmission quality.
  • the integrated chip further includes an insulating material, and the insulating material covers the first chip, the vertical interconnect structure, and the second chip.
  • the insulating material can be divided into a first insulating material and a second insulating material arranged up and down. At this time, the first insulating material wraps the first chip and the vertical interconnection structure, and the second The insulating material wraps the second chip.
  • the present application provides another integrated chip.
  • the integrated chip includes: a first interconnection layer, a first chip arranged on the first interconnection layer, and a second interconnection layer arranged on the top surface of the first chip.
  • the interconnection layer, the second chip and the first vertical interconnection structure arranged on the top surface of the second interconnection layer.
  • the second chip includes a first part and a second part, the first part coincides with the projection of the first chip on the second interconnection layer, and the second part protrudes from the first part along the second interconnection layer to the side of the first chip Square; the first vertical interconnection structure is arranged on the side of the first chip, the first chip and the second chip pass the second interconnection layer and the first vertical interconnection structure, bypass the first chip, and the first interconnection layer Connected.
  • the second part of the second chip in the integrated chip is electrically connected to the first chip provided on the first interconnection layer through the vertical interconnection structure, which can shorten the second part of the second chip and the first
  • the interconnection path between the chips to increase the data transmission rate of the integrated chip that is, increase the bandwidth of the integrated chip, and make the second part of the second chip bypass the first chip, and communicate with the first mutual through the first vertical interconnection structure.
  • the interconnection layers are electrically connected, so that no TSV is required in the first chip and the second chip, which can reduce the design and processing complexity of the integrated chip, as well as the risk of stress and warpage.
  • the second interconnection layer can not only fan out the pins at the bottom of the first part of the second chip from other sides of the second chip, but also increase the pin spacing to facilitate the interaction between the pins of the second chip and the first chip.
  • the connection can also be used as a stress buffer layer to reduce the stress generated when the second chip is interconnected with the vertical interconnect structure.
  • the structure of the integrated chip is a common stacked packaging structure, which has low technical risk and high technical feasibility, and has good packaging integration performance, making it easy for other chips to be packaged together.
  • the first vertical interconnection structure is a plurality of solder balls, or a plurality of copper pillars, or a plurality of molded vias TMV, or a plurality of dielectric layer vias TDV, or a plurality of Insulating layer through hole TIV.
  • One end of the first vertical interconnection structure is connected to the bottom of the second part of the second chip through the second interconnection layer, and the other end of the first vertical interconnection structure is directly connected to the conductive layer in the first interconnection layer.
  • the second chip is provided with signal transmission pins, and all the second signal transmission pins on the second chip are provided at the bottom (active surface) of the second part of the second chip, which can shorten
  • the data transmission path between the first chip and the second chip can further increase the bandwidth of the integrated chip.
  • the pins of the first chip for connecting with the pins of the second chip can be arranged on the side of the first chip close to the second part of the second chip, so as to minimize the length of the first chip and the second chip.
  • the interconnection path to improve the bandwidth of the integrated chip.
  • power supply pins are further provided on the second chip, and part or all of the power supply pins on the second chip are provided at the bottom of the second part of the second chip.
  • the signal transmission pins and power supply pins on the second chip are distributed in an array to form a first pin array. All the pins in any column of the first pin array are of the same type, and the pins in any two adjacent columns of the first pin array are of different types; or, all the pins in any row of the first pin array are different. The types of pins are the same, and the types of pins in any two adjacent rows in the first pin array are different.
  • the signal transmission pins of the chip Compared with the power supply pins of the chip, the signal transmission pins of the chip have a larger area. Therefore, the signal transmission pins and power supply pins of the second chip in the above solution are distributed in rows or columns, which can reduce the size of the second chip.
  • the area occupied by the middle pins can increase the number of pins per unit area of the second chip to meet the high integration requirements of the chip.
  • the signal transmission pins and power supply pins of the second chip are distributed in rows or columns. The signal transmission pins of different columns can be separated to reduce the mutual influence between the signal transmission pins and improve the signal transmission quality.
  • a high-speed signal pin is provided at the bottom of the second part of the second chip, and the high-speed signal pin is used to transmit high-speed signals (high-sensitivity signals), so that the high-speed signal pins of the second chip directly pass through
  • the first vertical interconnection structure is electrically connected to the first interconnection layer, which can shorten the interconnection path between the high-speed signal pins in the second chip and the first chip, and the high-speed signal pairs transmitted in the high-speed signal pins are integrated
  • the chip is the main factor that affects the bandwidth of the integrated chip. Therefore, the high-speed signal pins are arranged at the bottom of the second part of the second chip to effectively increase the bandwidth of the integrated chip.
  • the integrated chip includes at least two first chips; or, the integrated chip includes at least two second chips; or, the integrated chip includes at least two first chips and at least two second chips. chip.
  • the first chip is a processor chip
  • the second chip is a memory chip
  • the integrated chip further includes a third interconnect layer disposed on the top surface of the second chip and a third chip disposed on the top surface of the third interconnect layer.
  • the third chip includes a third part and a fourth part, the third part coincides with the projection of the second chip on the third interconnection layer, and the fourth part protrudes from the third part along the third interconnection layer
  • the second vertical interconnection structure is arranged on the side of the second chip, the third chip bypasses the first chip through the third interconnection layer and the second vertical interconnection structure, and interacts with the first Connected with layers.
  • the second vertical interconnection structure is a plurality of solder balls, or a plurality of copper pillars, or a plurality of molded vias TMV, or a plurality of dielectric layer vias TDV, or a plurality of Insulating layer through hole TIV.
  • One end of the second vertical interconnect structure is connected to the bottom of the fourth part of the third chip through the third interconnect layer, and the other end of the second vertical interconnect structure is directly connected to the conductive layer in the first interconnect layer.
  • the third chip is provided with signal transmission pins, and all the second signal transmission pins on the third chip are provided at the bottom (active surface) of the fourth part of the second chip, which can shorten
  • the data transmission path between the first chip and the third chip can further increase the bandwidth of the integrated chip.
  • the pins of the first chip for connecting with the pins of the third chip may be arranged on the side of the first chip close to the fourth part of the third chip, so as to minimize the length of the first chip and the third chip.
  • the interconnection path to improve the bandwidth of the integrated chip.
  • data transmission pins are provided on the third chip, and all signal transmission pins on the third chip are provided at the bottom of the fourth part of the third chip, which can shorten the first chip and the third chip.
  • the data transmission path between them can increase the bandwidth of the integrated chip.
  • the pins of the first chip for connecting with the pins of the third chip may be arranged on the side of the first chip close to the fourth part of the third chip, so as to minimize the length of the first chip and the third chip.
  • the interconnection path to improve the bandwidth of the integrated chip.
  • power supply pins are further provided on the third chip, and part or all of the power supply pins on the third chip are provided at the bottom of the fourth part of the third chip.
  • the data transmission pins and power supply pins of the third chip are distributed in an array to form a second pin array.
  • all the pins in any column of the second pin array are of the same type, and the types of pins in any two adjacent columns of the second pin array are different, that is, any two adjacent columns of the second pin array Among them, one column is signal transmission pins, and the other column is power supply pins; or, all pins in any row in the second pin array are of the same type, and in any two adjacent rows in the second pin array
  • the types of pins are different, that is, in any two adjacent rows of the second pin array, one row is a signal transmission pin, and the other row is a power supply pin.
  • the signal transmission pins of the chip Compared with the power supply pins of the chip, the signal transmission pins of the chip have a larger area. Therefore, the signal transmission pins and power supply pins of the third chip are distributed in rows or columns, which can reduce the number of pins in the third chip. The occupied area can further increase the number of pins per unit area of the third chip to meet the requirements of high chip integration. At the same time, the signal transmission pins and power supply pins of the third chip are arranged at intervals of rows or columns, which can separate the signal transmission pins of different columns, reduce the mutual influence between the signal transmission pins, and improve the signal transmission quality.
  • a high-speed signal pin is provided at the bottom of the fourth part of the third chip, and the high-speed signal pin is used to transmit a high-speed signal (high-sensitivity signal), so that the high-speed signal pin of the third chip directly passes through
  • the second vertical interconnection structure is electrically connected to the first interconnection layer, which can shorten the interconnection path between the high-speed signal pins in the third chip and the first chip, and the high-speed signal pairs transmitted in the high-speed signal pins are integrated
  • the chip is the main factor affecting the bandwidth of the integrated chip. Therefore, the high-speed signal pins are arranged at the bottom of the fourth part of the third chip to effectively increase the bandwidth of the integrated chip.
  • the integrated chip further includes an insulating material, and the insulating material covers the first chip, the vertical interconnect structure, and the second chip.
  • the insulating material can be further divided into a first insulating material and a second insulating material arranged up and down. At this time, the first insulating material wraps the first chip and the vertical interconnection structure, and the second The insulating material wraps the second chip.
  • the present application also provides a chip.
  • the chip includes a first part and a second part.
  • the first part is provided with pins of the first type for transmitting the first type of signals
  • the second part is provided with pins for transmitting the first type of signals.
  • the second type pin of the second type signal wherein the transmission rate of the first type signal is greater than the transmission rate of the second type signal.
  • the chip pins are divided into the first type of pins and the second type of pins according to the different transmission rates of the signals transmitted by the pins, and the first type of pins and the second type of pins are respectively set at The first part and the second part of the chip enable the chip to be packaged with other chips so that the first type pins of the chip can be connected to other chips through the shortest interconnection path to increase the bandwidth of the packaged chip.
  • the first type of signal includes at least one of a differential signal, an interrupt signal, a clock signal, and a reset signal.
  • FIG. 1 is a schematic diagram of the structure of stacked package integration in the prior art
  • Figure 2 is one of the schematic structural diagrams of an integrated chip provided by this application.
  • FIG. 3 is a schematic diagram of the structure of the chip provided by this application.
  • FIG. 4 is the second structural diagram of an integrated chip provided by this application.
  • FIG. 5a is the third schematic diagram of the structure of an integrated chip provided by this application.
  • FIG. 5b is the fourth structural diagram of an integrated chip provided by this application.
  • FIG. 6 is a schematic diagram of the pin distribution of the first chip and the second chip in an integrated chip provided by this application;
  • FIG. 7a is one of the schematic diagrams of the pin distribution of the second chip provided by this application.
  • FIG. 7b is the second schematic diagram of the pin distribution of the second chip provided by this application.
  • FIG. 8a is one of the schematic diagrams of the pin connection of the first chip and the second chip provided by this application.
  • 8b is the second schematic diagram of the pin connection of the first chip and the second chip provided by this application.
  • FIG. 9 is the fifth structural diagram of an integrated chip provided by this application.
  • FIG. 10 is a sixth structural diagram of an integrated chip provided by this application.
  • FIG. 11a is the seventh structural diagram of an integrated chip provided by this application.
  • FIG. 11b is the eighth schematic diagram of the structure of an integrated chip provided by this application.
  • FIG. 12a is one of the schematic structural diagrams after packaging an integrated chip and other chips provided by this application.
  • FIG. 12b is the second schematic diagram of the structure of an integrated chip and other chips provided by this application after packaging;
  • FIG. 13 is one of the schematic structural diagrams of another integrated chip provided by this application.
  • FIG. 14 is the second structural diagram of another integrated chip provided by this application.
  • Fig. 15a is the third structural diagram of another integrated chip provided by this application.
  • FIG. 15b is the fourth structural diagram of another integrated chip provided by this application.
  • 16 is a schematic diagram of the pin distribution of the first chip and the second chip in another integrated chip provided by this application;
  • FIG. 17 is the fifth structural diagram of another integrated chip provided by this application.
  • FIG. 18 is a sixth structural diagram of another integrated chip provided by this application.
  • FIG. 19a is the seventh structural diagram of another integrated chip provided by this application.
  • FIG. 19b is the eighth schematic diagram of another integrated chip structure provided by this application.
  • FIG. 20a is one of the schematic diagrams of another integrated chip packaged with other chips provided by this application.
  • FIG. 20b is the second schematic diagram of the structure of another integrated chip and other chips provided by this application after packaging;
  • FIG. 21 is a schematic structural diagram of a chip provided by this application.
  • FIG. 22 is a schematic flowchart of a chip packaging method provided by this application.
  • FIG. 23 is a schematic flowchart of a chip packaging method provided by a specific embodiment of this application.
  • this application proposes a chip and an integrated chip.
  • an embodiment of the present application provides an integrated chip 200.
  • the integrated chip 200 includes an interconnection layer 210, a first chip 220 disposed on the interconnection layer 210, a first vertical interconnection structure 230, and The second chip 240.
  • a part of the second chip 240 is disposed on the top surface of the first chip 220, and the other part extends from the top of the first chip 220 to the side of the first chip 220. Therefore, in the embodiment of the present application, the second chip 240 can be regarded as including two parts: a first part and a second part. The first part is attached to the top surface of the first chip 220.
  • the second part extends from the top of the first chip 220 close to the end of the second chip 240 to the side of the first chip 220 close to the first vertical interconnect structure 230.
  • the first vertical interconnect structure 230 and the second part are arranged on the same side of the first chip 220.
  • the second part is electrically connected to the interconnect layer 210 through the first vertical interconnect structure 230, so that the second chip 240 can be electrically connected to the first chip 220 through the first vertical interconnect structure 230 and the interconnect layer 210 .
  • the first chip 220 and the second chip 240 are arranged staggered, and the first part of the second chip 240 is supported by the first chip 220.
  • the second part of the second chip 240 protrudes from the side of the first chip 220 and is connected to the first vertical interconnection structure 230 at the same side of the first chip 220. That is, the second chip 240 bypasses the first chip 220 through the first vertical interconnect structure 230 and is electrically connected to the interconnect layer 210.
  • the first chip 220 and the second chip 240 implement signal transmission between each other through the interconnection layer 210.
  • the bottom of the interconnect layer 210 is also provided with an external interface, and the first chip 220 and the second chip 240 also transmit and receive signals with the outside of the integrated chip 200 through the interconnect layer 210.
  • a chip is usually composed of a semiconductor material and a circuit layer laid on the semiconductor material.
  • the semiconductor material is formed with semiconductor devices such as transistors.
  • the circuit layer is provided with multiple layers of circuits, usually with various functional circuits.
  • the circuit is coupled with the semiconductor device on the semiconductor material to form a complete chip circuit structure.
  • the surface on the side where the circuit layer in the chip is located is called the active surface
  • the surface on the side where the semiconductor material in the chip is located (the other surface corresponding to the active surface) is called the passive surface.
  • the bottom of the first chip 220 that is, the active surface 221 of the first chip 220 faces the interconnect layer 210
  • the bottom of the second chip 240 that is, the active surface 241 of the second chip 240 faces the interconnect layer. 210.
  • the active surface 241 of the second part of the second chip 240 is attached to the passive surface of the first chip 220 (that is, the top of the first chip 220). Since the active surface 221 of the first chip 220 and the active surface 241 of the second chip 240 both face the interconnection layer 210, the second part of the second chip 240 bypasses the first chip 220 and passes through the first vertical interconnection structure. 230 is electrically connected to the interconnection layer 210. Therefore, the first chip 220 does not need to provide a signal transmission channel to the second chip 240 by means of TSV, which reduces the risk of stress and warpage of the integrated chip 200, and the difficulty of the processing process And cost.
  • the first part of the second chip 240 is arranged on the top surface of the first chip 220, which means that the first part is directly mounted on the first part without being supported by other supporting structures such as solder balls and copper pillars.
  • an adhesive material can be applied between the first part of the second chip 240 and the top surface of the first chip 220 .
  • the first part of the second chip 240 is fixed on the top of the first chip 220 by the adhesive material 250, that is, the active surface 241 of the first part of the second chip 240 is covered by the adhesive material 250.
  • the adhesive material 250 may be a die attach epoxy (DAF) or silver plating (silver plating) or other materials.
  • DAF die attach epoxy
  • silver plating silver plating
  • the first part and the second chip 240 may also be A thermal or thermal insulation material is filled between a chip 220.
  • the above-mentioned adhesive material 250, thermally conductive material or heat insulating material can all be regarded as an auxiliary means required to fix the first part of the second chip 240 on the top surface of the first chip 220.
  • the interconnection layer 210 may be a so-called substrate.
  • the interconnection layer 210 may also be a redistribution layer (RDL) or a silicon substrate (also referred to as an interposer in English).
  • the interconnection layer 210 includes a multilayer dielectric layer 211 and a conductive layer 212 sandwiched between the dielectric layers 211.
  • the conductive layer 212 is provided with circuit wiring, and the dielectric layer 211 is provided with dielectric perforations for connecting the circuit wiring on different layers.
  • the interconnection layer 210 may be electrically connected to the first chip 220 through small copper pillars 260 as shown in FIG. 5a, or solder balls 270 as shown in FIG. 5b.
  • the solder balls 270 and the small copper pillars 260 are connected to the circuit wiring on the conductive layer 212 through dielectric through holes.
  • the thickness of RDL is smaller. Therefore, the use of RDL for the interconnect layer 210 can reduce the thickness of the integrated chip 200, and the first chip 220 dissipates heat downwards. Using a thinner RDL as the interconnect layer 210 is beneficial Heat dissipation of the first chip 220.
  • the first vertical interconnect structure 230 is a dielectric layer formed around the first chip 220, or a signal channel in the plastic encapsulation material that connects the second chip 220 and the interconnect layer 210.
  • the first vertical interconnection structure 230 may be implemented in multiple ways, for example, it may be a copper pillar standing on the side of the first chip 220; it may also be formed in a dielectric material on the side of the first chip 220 Through mold via (TMV), through dielectric via (TDV), or through insulator via (TIV), by plating or filling metal in the above holes To form a signal path; or, the first vertical interconnect structure 230 may also be a solder ball formed between the second chip 220 and the interconnect layer 210 (refer to the solder ball 230 in FIG. 5b).
  • One end of the first vertical interconnect structure 230 is directly connected to the bottom of the second part of the second chip 240, and the other end of the first vertical interconnect structure 230 is directly connected to the conductive layer in the interconnect layer 210.
  • the second chip 240 is provided with signal transmission pins (that is, input/output pads (input/output pad, I/O pad)), and all signal transmission pins on the second chip 240 are set at The bottom of the second part of the second chip 240, that is, all the signal transmission pins of the second chip 240 are arranged on the active surface 241 of the second part of the second chip 240, which can shorten the first chip 220 and the second chip 240. The signal transmission path between them can further increase the bandwidth of the integrated chip 200.
  • signal transmission pins that is, input/output pads (input/output pad, I/O pad)
  • the second chip 240 may also be provided with power supply pins, and all signal power supply pins on the second chip 240 are provided at the bottom of the second part of the second chip 240, that is, all the power supply pins of the second chip 240 are
  • the active surface 241 is provided on the second part of the second chip 240.
  • the pins of the first chip 220 for connecting with the pins of the second chip 240 can also be arranged on the side of the first chip 220 close to the second part of the second chip 240, as shown in FIG. 6 is a top view of the integrated chip 200 viewed from the top of the second chip 240) to minimize the interconnection path between the first chip 220 and the second chip 240 and increase the bandwidth of the integrated chip 200.
  • the signal transmission pins and power supply pins on the second chip 240 may be distributed in an array to form an entire column of the first pins.
  • FIG. 7a (FIG. 7a is a schematic diagram of the pin distribution of the second chip 240 shown in FIG. 6)
  • all the pins in any column of the first pin array are of the same type, and the first tube
  • the types of pins in any two adjacent columns of the pin array are different, that is, in any two adjacent columns of the first pin array, one column is a signal transmission pin, and the other column is a power supply pin.
  • FIG. 7b FIG. 7b is a schematic diagram of the pin distribution of the second chip 240 shown in FIG.
  • all the pins in any row in the first pin array are of the same type, and the first tube
  • the types of pins in any two adjacent rows of the pin array are different, that is, in any two adjacent rows of the first pin array, one row is a signal transmission pin, and the other row is a power supply pin.
  • the signal transmission pins of the chip have a larger area. Therefore, the signal transmission pins and the power supply pins of the second chip 240 are distributed in rows or columns at intervals, which can reduce the The area occupied by the pins in the second chip 240 can further increase the number of pins per unit area of the second chip 240 to meet the demand for high integration of the chip. At the same time, the signal transmission pins and power supply pins of the second chip 240 follow the line Or the column spacing distribution can separate the signal transmission pins of different columns to reduce the mutual influence between the signal transmission pins and improve the signal transmission quality.
  • the pins of the first chip 220 used to connect to the pins of the second chip 240 can also be arranged in an array corresponding to the pins of the second chip 240, as shown in FIG. 8a or FIG. 8b.
  • 8a and 8b are schematic diagrams of the distribution of the pins of the first chip 220 and the second chip 240 shown in FIG. 6.
  • the embodiment of the present application does not limit the shape of the array formed by the pins of the second chip 240, the number of pins included in each row of the array, and the number of pins included in each column of the array.
  • the number of pins included in each row in the array may be the same or different, and the number of pins included in each column in the array may be the same or different.
  • the first chip 220 may be a logic chip (logic die), such as a processor chip (such as an AP chip) or an intellectual property (IP) core (cores), and the second chip 240 may be Memory (including static random-access memory (SRAM) and DRAM), flip chip package, passive device, interposer, microelectromechanical system ( micro-electro-mechanical system, MEMS) and other chips or packages.
  • logic die such as a processor chip (such as an AP chip) or an intellectual property (IP) core (cores)
  • IP intellectual property
  • the second chip 240 may be Memory (including static random-access memory (SRAM) and DRAM), flip chip package, passive device, interposer, microelectromechanical system ( micro-electro-mechanical system, MEMS) and other chips or packages.
  • SRAM static random-access memory
  • MEMS microelectromechanical system
  • the integrated chip is usually filled with insulating materials around the chip.
  • the insulating material 280 wraps the first chip 220, the first vertical interconnection structure 230 and the second chip 240.
  • the insulating material 280 can be further divided into a first insulating material 281 and a second insulating material 282 arranged up and down.
  • the first insulating material 281 wraps the first chip 220 and the first vertical interconnection structure 230
  • the second insulating material 282 wraps the second chip 240.
  • the thickness of the second insulating material 282 needs to be greater than or equal to the thickness of the second chip 240. From the perspective of heat dissipation, the thinner the portion of the second insulating material 282 that is higher than the top of the second chip 240, the better the heat dissipation of the second chip 240.
  • the first insulating material 281 and the second insulating material 282 may be the same or different.
  • the first insulating material 281 and the second insulating material 282 may be silicon oxide (Silicon Oxide), silicon nitride (Nitride Oxide) or other epoxy resins (epoxy).
  • solder balls 270 are also provided at the bottom of the interconnection layer 210, which are used to realize the connection between the first chip 220 and the second chip 240 and the outside (such as a printed circuit board (PCB)). , Other chips, etc.), so that the integrated chip 200 can be directly connected to the outside through the solder balls 270.
  • PCB printed circuit board
  • the integrated chip 200 may include at least two first chips 220, or at least two second chips 240, or at least two first chips 220 and at least two second chips 240.
  • the integrated chip 200 includes two first chips 220 and a second chip 240.
  • the two first chips 220 are both disposed on the first interconnect layer 210, and the second chip 240 is disposed on the two first chips.
  • the second chip 240 includes two first parts and a second part located between the two first parts, and the two first parts of the second chip 240 are respectively Is arranged on the top surface of the two first chips 220, the first vertical interconnection structure 230 is located between the two first chips 220, one end is directly connected to the bottom of the second part of the second chip 240, and the other end is directly connected
  • the conductive layer 212 in the interconnection layer 210 is connected.
  • the integrated chip 200 includes a first chip 220 and two second chips 240, and the two second chips 240 are respectively disposed at two ends of the first chip 220.
  • the integrated chip 200 may further include a third chip 290 and a second vertical interconnection structure 300.
  • the third chip 290 is similar to the second chip 240 and includes two parts: a third part and a fourth part.
  • the third part is fixed on the top surface of the second chip 240 (the third part and the second chip 240
  • the fourth part protrudes from the side of the second chip 240 (the fourth part is similar to the second part of the second chip 240).
  • the second vertical interconnection structure 300 and the fourth part are disposed on the same side of the second chip 240, and the fourth part is electrically connected to the interconnection layer 210 through the second vertical interconnection structure 300, so that the third chip 290 can
  • the second vertical interconnection structure 300 and the interconnection layer 210 are electrically connected to the first chip 220.
  • the third part of the third chip 290 is arranged on the top surface of the second chip 220, which means that the third part is directly mounted without being supported by other supporting structures such as solder balls and copper pillars.
  • an adhesive material may be coated between the first part of the third chip 290 and the top surface of the second chip 240 . Specifically, as shown in FIG.
  • the third part of the third chip 290 is fixed on the top surface of the second chip 240 through the adhesive material 250, that is, the active surface of the third part of the third chip 290 is pasted
  • the material 250 is fixed on the passive surface of the second chip 240.
  • the third part and The second chip 240 is filled with a thermally conductive or heat insulating material.
  • the above-mentioned adhesive material 250, thermally conductive material or heat insulating material can all be regarded as an auxiliary means required to fix the third part of the third chip 290 on the top surface of the second chip 240.
  • the second vertical interconnection structure 300 is a dielectric layer formed around the first chip 220 and the second chip 240, or a signal channel in the plastic encapsulation material that connects the third chip 290 and the interconnection layer 210.
  • the second vertical interconnection structure 300 can be implemented in multiple ways, for example, it can be a copper pillar standing on the side of the first chip 220; it can also be TMV and TDV formed in the dielectric material on the side of the first chip 220. , Or TIV, a signal path is formed by plating or filling metal in the above-mentioned holes; or, the second vertical interconnection structure 300 may also be a solder ball formed between the third chip 290 and the interconnection layer 210.
  • One end of the second vertical interconnect structure 300 is directly connected to the bottom of the fourth part of the third chip 290, and the other end of the second vertical interconnect structure 300 is directly connected to the conductive layer in the interconnect layer 210.
  • the third chip 290 is provided with signal transmission pins, and all the signal transmission pins on the third chip 290 are provided at the bottom of the fourth part of the third chip 290, that is, all the signals of the third chip 290
  • the transmission pins are all arranged on the active surface of the fourth part of the third chip 290, which can shorten the signal transmission path between the first chip 220 and the third chip 290, thereby increasing the bandwidth of the integrated chip 200.
  • the third chip 290 may also be provided with power supply pins, and all the signal power supply pins on the third chip 290 are set at the bottom of the fourth part of the third chip 290, that is, all the power supply pins of the third chip 290 are It is arranged on the active surface of the fourth part of the third chip 290.
  • the pins of the first chip 220 for connecting with the pins of the third chip 290 can also be arranged on the side of the first chip 220 close to the fourth part of the third chip 290, so as to minimize the first chip.
  • the interconnection path between the chip 220 and the third chip 290 increases the bandwidth of the integrated chip 200.
  • the signal transmission pins and power supply pins on the third chip 290 may be distributed in an array to form a second pin array.
  • all the pins in any column of the second pin array are of the same type, and the types of pins in any two adjacent columns of the second pin array are different, that is, any two adjacent columns of the second pin array are different.
  • one column is signal transmission pins
  • the other column is power supply pins.
  • all the pins in any row in the second pin array are of the same type, and the pins in any two adjacent rows in the second pin array are of different types, that is, any two adjacent rows of the second pin array are different.
  • one row is a signal transmission pin
  • the other row is a power supply pin.
  • the signal transmission pins of the chip have a larger area. Therefore, the signal transmission pins and power supply pins of the third chip 290 are distributed in rows or columns at intervals, which can reduce the The area occupied by the pins of the three chips 290 can further increase the number of pins per unit area of the third chip 290 to meet the demand for high chip integration. At the same time, the signal transmission pins and power supply pins of the third chip 290 follow the same line as the power supply pins. Or the column spacing distribution can separate the signal transmission pins of different columns to reduce the mutual influence between the signal transmission pins and improve the signal transmission quality.
  • the pins of the first chip 220 for connecting with the pins of the third chip 290 may also be arranged in an array corresponding to the pins of the third chip 290.
  • a fourth chip may be provided on the top of the third chip 290 in the same way as the third chip 290 on the second chip 240, wherein a part of the fourth chip is fixed on the third chip.
  • another part of the fourth chip protrudes from the side of the third chip 290, and the bottom of the other part of the fourth chip is connected to the interconnection layer 210 through a third vertical interconnection structure.
  • a fifth chip and so on can be provided on top of the fourth chip.
  • the number of the first chip 220, the second chip 240 and the number of the third chip 290 in the integrated chip 200 are not limited in the embodiment of the present application.
  • the number of the first chip 220, the second chip 240, and the third chip 290 in the integrated chip 200 is determined according to the specific performance (such as bandwidth, area, processing speed, etc.) requirements of the integrated chip 200.
  • the chip type of the third chip 290 may be the same as or different from that of the second chip 240.
  • the second chip 240 in the integrated chip 200 is electrically connected to the first chip 220 disposed on the interconnection layer 210 through the first vertical interconnection structure 230, which can shorten the second chip 240 and the first chip 220 as much as possible.
  • the interconnection path between the integrated chip 200 to increase the data transmission rate that is, to increase the bandwidth of the integrated chip 200.
  • the active surface of the first chip 220 and the active surface of the second chip 240 in the integrated chip 200 both face the interconnection layer 210.
  • the second part of the second chip 240 bypasses the first chip 220 and passes through the first vertical
  • the interconnection structure 230 is electrically connected to the interconnection layer 210, so that no TSV is required in the first chip 220 and the second chip 240, which can reduce the design and processing complexity of the integrated chip 200, as well as stress and warpage risks of.
  • the structure of the integrated chip 200 is a common stacked packaging structure, which has low technical risk and high technical feasibility, and has good packaging integration performance, and is easy to package other chips together.
  • the integrated chip 200 may be packaged with other chips through stack packaging technology.
  • the integrated chip 200 may be packaged with other chips through FOPOP, or the integrated chip 200 may also be packaged with other chips through other POP methods, as shown in FIG. 12b.
  • an embodiment of the present application also provides another integrated chip 1300.
  • the integrated chip 1300 includes: a first interconnection layer 1310, a first chip 1320 disposed on the first interconnection layer 1310, and a first vertical The interconnect structure 1330, the second interconnect layer 1340 disposed on the top surface of the first chip, and the second chip 1350 disposed on the top surface of the second interconnect layer 1340. It can be seen from FIG. 13 that a part of the second chip 1350 is located on the part of the second interconnection layer 1340 that is coupled to the first chip 1320, and another part of the second chip 1350 is located on the second interconnection layer 1340 facing the first chip 1320.
  • the second chip 1350 includes two parts, a first part and a second part.
  • the first part coincides with the projection of the first chip 1320 on the second interconnection layer 1340, and the second part extends from the first part.
  • the second interconnection layer 1340 protrudes from the side of the first chip 1320.
  • the first vertical interconnection structure 1330 is arranged on the side of the first chip 1320.
  • the first chip 1320 and the second chip 1350 bypass the first chip 1320 through the second interconnection layer 1340 and the first vertical interconnection structure 1330, and
  • the first interconnect layer 1310 is electrically connected.
  • the top surface of the second chip 1350 and the second interconnection layer 1340 may also be filled with an adhesive material, a thermally conductive material or a heat insulating material.
  • the bottom of the second part of the second chip 1350 may be provided with a second interconnection layer 1340 or no second interconnection layer 1340, that is, the second interconnection layer 1340 may extend to the second part of the second chip 1350 It can also extend to the bottom of the first part of the second chip 1350 only.
  • the part of the second interconnection layer 1340 for connecting the second part of the second chip 1350 and the first vertical interconnection structure 1330 is also The electrical connection between the two is realized by means of vertical interconnection, that is, when the second interconnection layer 1340 is provided at the bottom of the second part of the second chip 1350, the second interconnection layer 1340 is used to connect the second chip 1350
  • the second part of and the part of the first vertical interconnection structure 1330 are also part of the first vertical interconnection structure 1330.
  • the second interconnection layer 1340 can not only fan out the pins at the bottom of the first part of the second chip 1350 from other sides of the second chip 1350, but also increase the pin spacing to facilitate the connection between the second chip 1350 and the first chip 1320.
  • the pin interconnection can also serve as a stress buffer layer to reduce the stress generated when the second chip 1350 is interconnected with the first vertical interconnect structure 1330.
  • the bottom of the first interconnect layer 1310 is also provided with an external interface, and the first chip 1320 and the second chip 1350 also transmit and receive signals with the outside of the integrated chip 1300 through the first interconnect layer 1310.
  • the active surface 1321 of the first chip 1320 faces the first interconnect layer 1310
  • the active surface 1351 of the second chip 1350 faces the second interconnect layer 1340
  • the first part of the second chip 1350 passes through the second interconnect layer 1340 and
  • the first vertical interconnection structure 1330 bypasses the first chip 1320 and is electrically connected to the first interconnection layer 1310.
  • the second part of the second chip 1350 is directly connected to the first interconnection layer 1310 through the first vertical interconnection structure 1330. It is electrically connected. Therefore, the second chip 1350 does not need to provide a signal transmission channel for the second chip 1350 by processing TSV, which reduces the risk of stress and warpage of the integrated chip 1300, the difficulty and cost of the processing process.
  • the first chip 1320 may be a logic chip, such as a processor or an intellectual property core
  • the second chip 1350 may be a memory (including SRAM and DRAM), flip chip packaging, passive devices, interposer boards, MEMS And other chips or packages.
  • the first chip 1320 may be fixed on the bottom of the second interconnection layer 1340 by an adhesive material 1360.
  • the pasting material 1360 can be DAF or silver paste.
  • the first interconnect layer 1310 may be an RDL or a silicon substrate, and the second interconnect layer 1340 may also be an RDL or a silicon substrate.
  • the first interconnection layer 1310 can pass through a plurality of small copper pillars 1370 (disposed on the top of the first interconnection layer 1310 (that is, facing the first chip 1320) as shown in FIG. 15a).
  • the circuit wiring on the conductive layer is connected.
  • the manner in which the second interconnection layer 1340 and the second chip 1350 are electrically connected is similar to the manner in which the first interconnection layer 1310 and the first chip 1320 are electrically connected, and will not be repeated here.
  • the thickness of RDL is smaller. Therefore, the use of RDL for the first interconnection layer 1310 and the second interconnection layer 1340 can reduce the thickness of the integrated chip 1300, and the first chip 1320 dissipates heat downward, using a thinner RDL As the first interconnect layer 1310, it is beneficial to the heat dissipation of the first chip 220.
  • the first vertical interconnection structure 1330 is a dielectric layer formed around the first chip 1320, or a signal channel connecting the second chip 1350 and the first interconnection layer 1310 in a plastic packaging material.
  • the first vertical interconnection structure 1330 can be implemented in multiple ways, for example, it can be a copper pillar standing on the side of the first chip 1320; it can also be TMV and TDV formed in the dielectric material on the side of the first chip 1320. , Or TIV, the signal path is formed by plating or filling metal in the above-mentioned holes; or, the first vertical interconnection structure 1330 can also be a solder formed between the second chip 1350 and the first interconnection layer 1310 ball.
  • One end of the first vertical interconnect structure 1330 is connected to the bottom of the second part of the second chip 1350 through the second interconnect layer 1340, and the other end of the second vertical interconnect structure 1330 is directly connected to the first interconnect layer 1310 The conductive layer.
  • the second chip 1350 is provided with signal transmission pins, and all the signal transmission pins on the second chip 1350 are provided at the bottom of the second part of the second chip 1350, that is, the second chip 1350 All signal transmission pins of the second chip 1350 are arranged on the active surface of the second part of the second chip 1350, which can shorten the signal transmission path between the first chip 1320 and the second chip 1350, thereby increasing the bandwidth of the integrated chip 1300.
  • the second chip 1350 may also be provided with power supply pins, and all signal power supply pins or part of the power supply pins on the second chip 1350 are provided at the bottom of the second part of the second chip 1350, that is, all the power supply pins of the second chip 1350
  • the power supply pins or part of the power supply pins are arranged on the active surface of the second part of the second chip 1350.
  • the pins of the first chip 1320 for connecting with the pins of the second chip 1350 can also be arranged on the side of the first chip 1320 close to the second part of the second chip 1350, so as to minimize the first chip.
  • the interconnection path between the chip 1320 and the second chip 1350 increases the bandwidth of the integrated chip 1300.
  • the bottom of the second part (active surface) of the second chip 1350 is provided with high-speed signal pins
  • the bottom of the first part (active surface) of the second chip 1350 is provided with non-high-speed signal pins.
  • the high-speed signal pins are used to transmit high-speed signals (high-sensitivity signals), so that the high-speed signal pins of the second chip 1350 are directly electrically connected to the first interconnection layer 1310 through the first vertical interconnection structure 1330, which can shorten
  • the interconnection path between the high-speed signal pins in the second chip 1350 and the first chip 1310, and the high-speed signal transmitted in the high-speed signal pins is the main factor affecting the bandwidth of the integrated chip 1300.
  • the The way that the high-speed signal pins are arranged at the bottom of the second part of the second chip 1350 can increase the bandwidth of the integrated chip 1300.
  • the signal when the signal meets any of the following conditions, the signal is considered to be a high-speed signal: a. Serious skin effect and ionization loss occur when the signal is transmitted along the transmission path; b. The rising or falling edge of the signal is less than 50ps; c. The length of the signal transmission path is greater than 1/6 ⁇ , where ⁇ is the wavelength of the signal; d. The frequency of the signal is greater than 50MHz, and the non-high-speed signals are signals other than the above-mentioned high-speed signals.
  • the pins of the first chip 1320 for connecting to the high-speed signal pins of the second chip 1350 are arranged on the side of the first chip 1320 close to the second part of the second chip 1350, as shown in FIG.
  • the interconnection path between the first chip 1320 and the second chip 1350 is shortened to the greatest extent, and the bandwidth of the integrated chip 1300 is increased.
  • the signal transmission pins and power supply pins on the second chip 1350 may be distributed in an array to form an entire column of the first pins.
  • all the pins in any column of the first pin array are of the same type, and the types of pins in any two adjacent columns of the first pin array are different, that is, the first pin In any two adjacent columns of the array, one column is a signal transmission pin, and the other column is a power supply pin.
  • FIG. 7a all the pins in any column of the first pin array are of the same type, and the types of pins in any two adjacent columns of the first pin array are different, that is, the first pin In any two adjacent columns of the array, one column is a signal transmission pin, and the other column is a power supply pin.
  • FIG. 7a all the pins in any column of the first pin array are of the same type, and the types of pins in any two adjacent columns of the first pin array are different, that is, the first pin In any two adjacent columns of the array, one column is a signal transmission pin, and the
  • all the pins in any row in the first pin array are of the same type, and the pins in any two adjacent rows in the first pin array are of different types, that is, the first pin In any two adjacent rows of the array, one row is a signal transmission pin, and the other row is a power supply pin.
  • the different types of the array formed by the pins of the second chip 1350 are distributed at intervals of rows or columns.
  • the pins of the first chip 1320 for connecting with the pins of the second chip 1350 may also be arranged in an array corresponding to the pins of the second chip 1350.
  • the signal transmission pins of the chip have a larger area. Therefore, the signal transmission pins and power supply pins of the second chip 1350 are distributed in rows or columns at intervals, which can reduce the number of The area occupied by the pins in the second chip 1350 can increase the number of pins per unit area of the second chip 1350 to meet the demand for high chip integration. At the same time, the signal transmission pins and power supply pins of the second chip 1350 follow the same line Or the column spacing distribution can separate the signal transmission pins of different columns to reduce the mutual influence between the signal transmission pins and improve the signal transmission quality.
  • the integrated chip is usually filled with insulating materials around the chip.
  • the insulating material 1390 wraps the first chip 1320, the first vertical interconnection structure 1330 and the second chip 1350.
  • the insulating material 1390 can be further divided into a first insulating material 1391 and a second insulating material 1392 arranged up and down.
  • the first insulating material 1391 wraps the first chip 1320 and the second insulating material 1392.
  • a vertical interconnect structure 1330, and a second insulating material 1392 encapsulates the second chip 1350.
  • the thickness of the second insulating material 1392 needs to be greater than or equal to the thickness of the second chip 1350, but from the perspective of chip heat dissipation, the thickness of the second insulating material 1392 is closer to the second chip 1350 The thickness is more conducive to the heat dissipation of the second chip 1350.
  • the first insulating material 1391 and the second insulating material 1392 may be the same or different.
  • the first insulating material 1391 and the second insulating material 1392 may be silicon oxide, silicon nitride, or other epoxy resins.
  • the bottom of the first interconnection layer 1310 is also provided with a plurality of solder balls 1380, which are used to realize the interaction between the first chip 1320 and the second chip 1350 and the outside (such as PCB, other chips, etc.). even.
  • the integrated chip 1300 includes at least two first chips 1320, or includes at least two second chips 1350 (for example, as shown in FIG. 19a), or includes at least two first chips 1320 and at least two The second chip 1350.
  • the integrated chip 1300 may further include a third interconnection layer 1400 disposed on the top surface of the second chip, a third chip 1410 disposed on the top surface of the third interconnection layer 1400, and a second vertical Interconnect structure 1420.
  • the third chip 1410 is similar to the second chip 1350 and includes a third part and a fourth part. The third part overlaps with the projection of the second chip 1350 on the third interconnection layer 1400. Partly protrudes from the side of the second chip 1350 along the third interconnect layer 1400; the second vertical interconnect structure 1420 is arranged on the side of the second chip 1350, and the third chip 1410 passes through the third interconnect layer 1400 and the second chip 1350.
  • the vertical interconnect structure 1420 bypasses the first chip 1320 and is connected to the first interconnect layer 1310.
  • the third interconnection layer 1400 may or may not be provided at the bottom of the fourth part of the third chip 1410, that is, the third interconnection layer 1400 may extend to the fourth part of the third chip 1410
  • the bottom of the third chip 1410 can also only extend to the bottom of the fourth part of the third chip 1410.
  • the part of the third interconnection layer 1400 for connecting the fourth part of the third chip 1410 and the second vertical interconnection structure 1420 is also The electrical connection between the two is achieved through a vertical interconnection, that is, when the third interconnection layer 1400 is provided at the bottom of the fourth part of the third chip 1410, the third interconnection layer 1400 is used to connect the third chip 1410
  • the fourth part of and the part of the second vertical interconnection structure 1420 are also part of the second vertical interconnection structure 1420.
  • the third interconnection layer 1400 can not only fan out the pins at the bottom of the third part of the third chip 1410 from other sides of the third chip 1410, but also increase the pin spacing to facilitate the third chip 1410 and the first chip 1320
  • the pin interconnection can also be used as a stress buffer layer to reduce the stress generated when the third chip 1410 is interconnected with the second vertical interconnect structure 1420.
  • the third interconnection layer 1400 is close to one end of the first part of the second chip 1350, and a vertical interconnection structure may also be provided, so that the first part of the second chip 1350 can pass through the third interconnection layer 1400 and the vertical interconnection.
  • the structure is electrically connected to the second interconnect layer 1340.
  • the second vertical interconnection structure 1420 is a dielectric layer formed around the second chip 1350, or a signal channel connecting the third chip 1410 and the first interconnection layer 1310 in a plastic packaging material.
  • the second vertical interconnect structure 1420 can be implemented in multiple ways, for example, it can be a copper pillar standing on the side of the second chip 1350; it can also be TMV and TDV formed in the dielectric material on the side of the second chip 1350. , Or TIV, the signal path is formed by plating or filling metal in the above-mentioned holes; or, the second vertical interconnection structure 1420 may also be a solder formed between the third chip 1410 and the first interconnection layer 1310 ball.
  • One end of the second vertical interconnect structure 1420 is connected to the bottom of the fourth part of the third chip 1410 through the third interconnect layer 1400, and the other end of the second vertical interconnect structure 1420 is directly connected to the first interconnect layer 1310 The conductive layer.
  • signal transmission pins are provided on the third chip 1410, and all signal transmission pins on the third chip 1410 are provided at the bottom of the fourth part of the third chip 1410, that is, the third chip 1410 All the signal transmission pins of the third chip 1410 are arranged on the active surface of the fourth part of the third chip 1410, which can shorten the signal transmission path between the first chip 1320 and the third chip 1410, thereby increasing the bandwidth of the integrated chip 1300.
  • the third chip 1410 may also be provided with power supply pins, and all signal power supply pins or part of the power supply pins on the third chip 1410 are provided at the bottom of the fourth part of the third chip 1410, that is, all the power supply pins of the third chip 1410
  • the power supply pins or part of the power supply pins are arranged on the active surface of the fourth part of the third chip 1410.
  • the pins of the first chip 1320 for connecting with the pins of the third chip 1410 can also be arranged on the side of the first chip 1320 close to the fourth part of the third chip 1410, so as to minimize the first chip.
  • the interconnection path between the chip 1320 and the third chip 1410 increases the bandwidth of the integrated chip 1300.
  • the signal transmission pins and power supply pins on the third chip 1410 may be arranged in an array to form an entire column of second pins.
  • all the pins in any column of the second pin array are of the same type, and the types of pins in any two adjacent columns of the second pin array are different, that is, the second pin In any two adjacent columns of the array, one column is a signal transmission pin, and the other column is a power supply pin.
  • pins in any row in the second pin array are of the same type, and the pins in any two adjacent rows in the first pin array are of different types, that is, the second pin In any two adjacent rows of the array, one row is a signal transmission pin, and the other row is a power supply pin.
  • the pins of the first chip 1320 for connecting with the pins of the third chip 1410 may also be arranged in an array corresponding to the pins of the third chip 1410.
  • the signal transmission pins of the chip have a larger area. Therefore, the signal transmission pins and power supply pins of the third chip 1410 are distributed in rows or columns at intervals, which can reduce the The area occupied by the pins of the three chips 1410 can increase the number of pins per unit area of the third chip 1410 to meet the requirements of high chip integration. At the same time, the signal transmission pins and power supply pins of the third chip 1410 follow the same line Or the column spacing distribution can separate the signal transmission pins of different columns to reduce the mutual influence between the signal transmission pins and improve the signal transmission quality.
  • the bottom of the fourth part (active surface) of the third chip 1410 is provided with high-speed signal pins
  • the bottom of the third part (active surface) of the third chip 1410 is provided with non-high-speed signal tubes.
  • the high-speed signal pins of the third chip 1410 are directly electrically connected to the first interconnection layer 1310 through the second vertical interconnection structure 1420, which can shorten the distance between the high-speed signal pins of the third chip 1410 and the first chip 1310.
  • the high-speed signal transmitted in the high-speed signal pins is the main factor affecting the bandwidth of the integrated chip 1300. Therefore, the high-speed signal pins are arranged at the bottom of the second part of the second chip 1350 In this way, the bandwidth of the integrated chip 1300 can be increased.
  • the pins of the first chip 1320 for connecting with the high-speed signal pins of the third chip 1410 are arranged on the side of the first chip 1320 close to the fourth part of the third chip 1410, so as to minimize the first chip.
  • the interconnection path between the chip 1320 and the third chip 1410 increases the bandwidth of the integrated chip 1300.
  • a fourth chip may be provided on the top of the third chip 1410 in the same manner as the third chip 1410 on the second chip 1350, wherein a part of the fourth chip is connected to the fourth chip.
  • the projections on the interconnection layer disposed on the top surface of the third chip 1410 coincide, and another part of the fourth chip protrudes from the third chip 1410 along the interconnection layer disposed on the top surface of the third chip 1410 from a part of the fourth chip
  • the bottom of the other part of the fourth chip is connected to the first interconnection layer 1310 through the third vertical interconnection structure.
  • a fifth chip and so on can be provided on top of the fourth chip.
  • the number of the first chip 1320, the second chip 1350, and the number of the third chip 1410 in the integrated chip 1300 are not limited in the embodiment of the present application.
  • the number of the first chip 1320, the number of the second chip 1350, and the number of the third chip 1410 in the integrated chip 1300 are determined according to the specific performance (such as bandwidth, area, processing speed, etc.) requirements of the integrated chip 1300.
  • the second part of the second chip 1350 in the integrated chip 1300 is electrically connected to the first chip 1320 arranged on the first interconnection layer 1310 through the first vertical interconnection structure 1330, which can shorten the second chip as much as possible.
  • the connecting structure 1340 is electrically connected to the first interconnect layer 1310, so that no TSV is required in the first chip 1320 and the second chip 1350, which can reduce the design and processing complexity of the integrated chip 1300, as well as stress and warpage. The risk of music.
  • the structure of the integrated chip 1300 is a common stacked packaging structure, which has low technical risk and high technical feasibility, and has good packaging integration performance, and is easy to package other chips together.
  • the integrated chip 1300 may be packaged with other chips through stack packaging technology.
  • the integrated chip 1300 may be packaged with other chips through FOPOP, or the integrated chip 1300 may also be packaged with other chips through other POP methods, as shown in FIG. 20b.
  • an embodiment of the present application also provides a chip 2100.
  • the chip 2100 includes a first part and a second part.
  • the first part of the chip 2100 is provided with a first type of pin for transmitting a first type of signal. 2110.
  • the second part of the chip 2100 is provided with a second type pin 2120 for transmitting the second type signal, and the transmission rate of the first type signal is greater than the transmission rate of the second type signal.
  • the chip 2100 may be a memory (including SRAM and DRAM), flip-chip packaging, passive devices, adapter boards, MEMS or other chips or packages.
  • the first type of signal includes at least one of high-speed signals such as differential signals, interrupt signals, clock signals, and reset signals. It should be noted that the above description of the first type of signal is only an example, and does not limit this application embodiment.
  • the pins 2110 of the first type are distributed in an array, and the pins of the first type include signal transmission pins and power supply pins (wherein, the power supply pins are used to supply power to the signal transmission pins).
  • the pins in any column of the array are of the same type, and the types of pins in any two adjacent columns of the array are different, as shown in Figure 7a; or, the types of all pins in any row of the array Same, the types of pins in any two adjacent rows in the array are different, as shown in Figure 7b.
  • different types are distributed at intervals of rows or columns.
  • the signal transmission pins of the chip have a larger area. Therefore, the first type of pins 2110 are distributed in an array, and the signal transmission pins of the first type of pins 2110 and the power supply The pins are distributed according to the row or column spacing, which can reduce the area occupied by the pins in the chip 2100, thereby increasing the number of pins per unit area in the chip 2100 to meet the demand for high integration of the chip.
  • the first type of pins The signal transmission pins and power supply pins in the 2110 are arranged at intervals of rows or columns. The signal transmission pins of different columns can be separated to reduce the mutual influence between the signal transmission pins and improve the signal transmission quality.
  • the second type of pins 2120 may also be distributed in an array, and the second type of pins 2120 includes signal transmission pins and power supply pins.
  • all the pins in any column of the array are of the same type, and the types of pins in any two adjacent columns of the array are different, as shown in Figure 7a; or, the types of all the pins in any row of the array Same, the types of pins in any two adjacent rows in the array are different, as shown in Figure 7b.
  • different types of pins 2120 of the second type of the chip 2100 are arranged at intervals of rows or columns in an array.
  • the pins of the chip 2100 are divided into the first type of pins 2110 and the second type of pins 2120 according to the different transmission rates of the signals transmitted by the pins, and the first type of pins 2110 and the second type of pins 2120
  • the pins 2120 are respectively provided in the first part and the second part of the chip 2100, so that when the chip 2100 is packaged with other chips, the first-type pins 2110 of the chip 2100 can be connected to other chips through the shortest interconnection path. Improve the bandwidth of the packaged chip.
  • an embodiment of the present application also provides a chip packaging method, which mainly includes the following steps:
  • S2201 Fabricate a vertical interconnection structure on the active surface of the first part of the first chip.
  • the vertical interconnection structure may be any one of copper pillars, TMV, TDV, TIV, or solder balls.
  • S2202 Paste the active surface of the second part of the first chip on the passive surface of the second chip.
  • the active surface of the second part of the first chip can be adhered to the passive surface of the second chip through an adhesive material.
  • the sticking material can be DAF or silver paste.
  • S2203 Fabricate an interconnection layer on the vertical interconnection structure and the active surface of the second chip.
  • the interconnection layer may be a substrate or a wiring layer.
  • fabricating a vertical interconnection structure on the active surface of the first part of the first chip specifically includes the following steps: i. Bonding the active surface of the first chip to a carrier; ii , Prepare a first insulating material to form a first package, wherein the first insulating material wraps the first chip; iii. remove the carrier sheet, and prepare the first part of the active surface in the first package Vertical interconnect structure.
  • the carrier sheet includes but is not limited to any one of a silicon wafer and a glass sheet, and a temporary bonding layer is arranged between the carrier sheet and the first chip for subsequent debonding.
  • step S2202 the passive surface of the second chip is pasted on the surface of the first package from the position where the second part of the active surface is located.
  • the method further includes: thinning the first package body.
  • the first package body can be thinned to a set thickness through processes including but not limited to grinding, polishing, or a combination of the two, and the set thickness is determined according to the actual processing technology and processing cost. For example, when the thickness of the first chip is large, the first package can be thinned to the same thickness as the first chip.
  • an interconnection layer can be fabricated on the vertical interconnection structure and the active surface of the second chip by the following methods: 1. A second insulating material is prepared to form a second package body, wherein Two insulating materials wrap the vertical interconnect structure and the second chip; 2. prepare the interconnect layer on the surface where the vertical interconnect structure and the active surface of the second chip in the second package body are located. Wherein, the second insulating material and the first insulating material may be the same or different.
  • the method further includes: Grinding is performed to expose the vertical interconnect structure and the small copper pillars on the active surface of the second chip.
  • the small copper pillars on the active surface of the second chip can be pre-processed on the active surface of the second chip. Surface.
  • solder balls may be prepared on the interconnection layer, so that the chip obtained after the first chip and the second chip are packaged can be connected to the outside through the solder balls.
  • the integrated chip 200 shown in FIG. 5a is packaged as an example to describe the chip packaging method provided in the present application in detail.
  • the first chip 220 is a processor chip
  • the second chip 240 is an HBM—DRAM chip separated from a memory package purchased by a memory manufacturer.
  • the bandwidth of the separated DRAM chip can reach 256Gbps.
  • the bit width of the separated DRAM chip is also higher than that of the DRAM package in the traditional stacked package structure, which can reach 1024 bits.
  • Packaging and forming the integrated chip 200 shown in FIG. 5a mainly includes the following steps:
  • S2301 Bond the active face of the second chip 240 to the carrier. Wherein, a temporary bonding layer is provided between the carrier sheet and the second chip 240.
  • S2302 Plastic-encapsulate the second chip 240 bonded on the carrier with a plastic molding compound to obtain a first package.
  • S2304 Separate the carrier sheet from the first package body after the thinning process, and remove the carrier sheet (ie, debonding).
  • S2305 Fabricate copper pillars on the active surface of the second part of the second chip 240 in the first package after the thinning process.
  • S2306 Adhere the passive surface of the first chip 220 to the active surface of the first part of the second chip 240 in the first package body through the adhesive material. Wherein, a plurality of small copper pillars are provided on the active surface of the first chip 220.
  • S2308 Grind the second package body to expose the copper pillars prepared on the first part of the second chip 240 and the small copper pillars on the active surface of the first chip 220.
  • the preparation of the integrated chip 1300 can also adopt a method similar to the above method.
  • the subtle difference is that after the second chip 1350 is plasticized to obtain the first package, the first package needs to be grown on the surface of the first package.
  • the dielectric material and metal wiring of the second interconnection layer 1340 are then fabricated or grown on the second interconnection layer 1340 such as vertical interconnection structures such as copper pillars, and the first chip 1320 is pasted.

Abstract

一种芯片以及集成芯片，以解决现有技术中封装芯片中上下层芯片需要通过TSV方式互连，导致下层芯片结构中的翘曲风险高、设计复杂度以及制作工艺难度大的问题。该集成芯片包括互连层，设置在互连层上的第一芯片，第二芯片以及第一垂直互连结构。其中，第二芯片包括第一部分和第二部分，第一部分被设置在第一芯片的顶部表面上，第二部分突出于第一芯片的侧方；第一垂直互连结构设置在第一芯片的侧方，第二芯片的第二部分通过第一垂直互连结构与互连层电性连接，即第一芯片与第二芯片相错设置，第一垂直互连结构与第二芯片的第二部分设置在第一芯片的同侧，第二芯片的第二部分绕过第一芯片，通过第一垂直互连结构与互连层电性连接。

Description

一种芯片以及集成芯片 技术领域
本申请涉及芯片封装技术领域，尤其涉及一种芯片以及集成芯片。
背景技术
随着半导体技术的发展，芯片封装技术在电子设备产业链中的地位也变得更加重要。其中，在芯片封装技术中堆叠型封装(package on package,POP)技术工艺较为成熟，可行性较高，可以大幅度提高芯片封装的集成度，具有较高的收益。
目前，采用堆叠型封装技术封装的集成芯片中上层芯片和下层芯片通过焊球(solder ball)、布线层、垂直互连结构以及基板(substrate)等实现互连，互连走线较长，导致堆叠封装后形成的芯片的带宽较小。
采用堆叠型封装技术的集成芯片的常见结构如图1所示，上层芯片位于下层芯片的上方，上层芯片通过焊球、互连层(布线层或基板)、垂直互连结构、扇出型布线层(fan out redistribution layer,FO-RDL)、小铜柱(copper stud)与下层芯片实现电性互连。其中，上层芯片可以是动态随机存取存储器(dynamic random access memory，DRAM)芯片，下层芯片可以是系统芯片(system on chip，简称SOC)，DRAM芯片通常是直接从存储器制造商购买的封装好的DRAM封装体，封装好的存储器中的多颗存储器裸芯片(bare die)通过引线键合(wire bonding，WB)或者硅通孔(through silicon via,TSV)等技术进行不同层裸芯片之间的互连，通过塑封形成封装体。
由图1可知，上层芯片和下层芯片通过焊球、互连层、垂直互连结构、扇出型布线层以及小铜柱实现电性互连，互连路径较长，导致封装后的集成芯片带宽较小。随着半导体技术的快速发展，考虑到散热和电力分配的需求，下层芯片开始也有了多芯片集成的需求。为了提高该SOC的工作效率，会在下层芯片中再为所述SOC封装一个存储芯片。这样，对于SOC需要用到的传输速率要求高的数据，可以存放在下层芯片内的存储芯片中，而不需要通过访问上层的DRAM芯片。下层芯片中的SOC和存储芯片的封装通常也会采用叠加的方式，比如将SOC设置在存储芯片的顶部，所述SOC的有源面贴在存储芯片的硅层上，然后通过在存储芯片的硅层中打上TSV的方式实现SOC和存储芯片的有源面的互联。
在这种场景下，由于下层芯片中的存储芯片中要形成TSV，这就需要增大下层芯片中的存储芯片的体积，尤其是横向面积，从而导致下层芯片结构中的翘曲风险提高。同时，这也提高了下层芯片的设计复杂度，加大了制作工艺难度。
发明内容
本申请提供一种芯片以及集成芯片，以解决现有技术中封装芯片中上下层芯片需要通过TSV方式互连，导致下层芯片结构中的翘曲风险高、设计复杂度以及制作工艺难度大的问题。
第一方面，本申请提供了一种集成芯片，该集成芯片包括互连层，设置在互连层上的第一芯片，第二芯片以及第一垂直互连结构。其中，第二芯片包括第一部分和第二部分，第一部分被设置在第一芯片的顶部表面上，第二部分突出于第一芯片的侧方；第一垂直互 连结构设置在第一芯片的侧方，第二芯片的第二部分通过第一垂直互连结构与互连层电性连接。即第一芯片与第二芯片相错设置，第一垂直互连结构与第二芯片的第二部分设置在第一芯片的同侧，第二芯片的第二部分绕过第一芯片，通过第一垂直互连结构与互连层电性连接。
通过上述方案，集成芯片中的第二芯片通过第一垂直互连结构与设置在互连层上的第一芯片电性连接，能够尽量缩短第二芯片与第一芯片之间的互连路径，以提高集成芯片数据传输速率，即提高集成芯片的带宽。并且，第二芯片的第二部分绕过了第一芯，通过第一垂直互连结构与互连层电性连接，使得第一芯片以及第二芯片中均不需要制作TSV，能够降低集成芯片的设计以及加工的复杂度，以及应力和翘曲的风险。
在本发明实施例中，第一芯片和第二芯片可以为处理器芯片和存储器芯片的任意组合，比如第一芯片为处理器芯片，第二芯片为存储器芯片，亦或者，第一芯片为存储器芯片，第二芯片为处理器芯片。在可选择的实施例中，所述第一芯片和第二芯片也可以是其它类型芯片的任意组合。
另外，集成芯片的结构为常见的堆叠型封装结构，技术风险较低，技术可行性较高，并且具有较好的封装集成性能，易于其他的芯片封装在一起。
一个可能的实施方式中，第一垂直互连结构为多个焊球，或者为多个铜柱，或者为多个模封通孔TMV，或者为多个介质层通孔TDV，或者为多个绝缘层通孔TIV。第一垂直互连结构的一端被直接连接至第二芯片的第二部分的底部，第一垂直互连结构的另一端被直接连接至互连层中的导电层。
一个可能的实施方式中，第二芯片上设置有数据传输管脚，第二芯片上的所有信号传输管脚均设置于第二芯片的第二部分的底部，能够缩短第一芯片与第二芯片之间的数据传输路径，进而可以提高集成芯片的带宽。
进一步地，第一芯片中用于与第二芯片的管脚连接的管脚可以设置在第一芯片靠近第二芯片的第二部分的一侧，以最大程度地缩短第一芯片与第二芯片的互连路径，提高集成芯片的带宽。
一个可能的实施方式中，第二芯片上还设置有供电管脚，第二芯片上的供电管脚均设置在第二芯片的第二部分的底部。
一个可能的实施方式中，第二芯片的数据传输管脚以及供电管脚呈阵列分布，构成第一管脚阵列。其中，第一管脚阵列的任意一列中所有管脚的类型相同，该第一管脚阵列的任意相邻两列中管脚的类型不同即该第一管脚阵列的任意相邻两列中，一列均为信号传输管脚，另一列均为供电管脚；或者，该第一管脚阵列中任意一行中所有管脚的类型相同，该第一管脚阵列中任意相邻两行中管脚的类型不同，即该第一管脚阵列的任意相邻两行中，一行均为信号传输管脚，另一行均为供电管脚。
相较于芯片的供电管脚，芯片的信号传输管脚的面积较大，因此，第二芯片的信号传输管脚与供电管脚按照行或者列间隔分布，能够减小第二芯片中管脚所占的面积，进而能够增加第二芯片单位面积内的管脚数目，满足芯片高度集成的需求。同时，第二芯片的信号传输管脚与电源管脚按照行或者列间隔分布，可以将不同列的信号传输管脚分割开来，降低信号传输管脚之间的互相影响，提高信号传输质量。
一个可能的实施方式中，第一芯片可以为处理器芯片，第二芯片可以为存储器芯片。
一个可能的实施方式中，第二芯片的第一部分通过黏贴材料被固定在第一芯片的顶部 表面上。其中，黏贴材料可以为芯片粘合剂或银浆等材料。
一个可能的实施方式中，集成芯片包括至少两个第一芯片；或者，集成芯片包括至少两个第二芯片；或者，集成芯片包括至少两个第一芯片以及至少两个第二芯片。
一个可能的实施方式中，集成芯片还包括第三芯片和第二垂直互连结构。其中，第三芯片包括第三部分和第四部分，该第三部分被固定在第二芯片的顶部表面上，该第四部分突出于第二芯片的侧方；第二垂直互连结构设置在第二芯片的侧方，第三芯片的第四部分通过第二垂直互连结构与互连层电性连接。
一个可能的实施方式中，第二垂直互连结构为多个焊球，或者为多个铜柱，或者为多个模封通孔TMV，或者为多个介质层通孔TDV，或者为多个绝缘层通孔TIV。第二垂直互连结构的一端被直接连接至第三芯片的第四部分的底部，第二垂直互连结构的另一端被直接连接至互连层中的导电层。
一个可能的实施方式中，第三芯片上设置有数据传输管脚，第三芯片上的所有信号传输管脚均设置于第三芯片的第四部分的底部，能够缩短第一芯片与第三芯片之间的数据传输路径，进而可以提高集成芯片的带宽。
进一步地，第一芯片中用于与第三芯片的管脚连接的管脚可以设置在第一芯片靠近第三芯片的第四部分的一侧，以最大程度地缩短第一芯片与第三芯片的互连路径，提高集成芯片的带宽。
一个可能的实施方式中，第三芯片上还设置有供电管脚，第三芯片上的供电管脚均设置在第二芯片的第四部分的底部。
一个可能的实施方式中，第三芯片的数据传输管脚以及供电管脚呈阵列分布，构成第二管脚阵列。其中，第二管脚阵列的任意一列中所有管脚的类型相同，该第二管脚阵列的任意相邻两列中管脚的类型不同，即该第二管脚阵列的任意相邻两列中，一列均为信号传输管脚，另一列均为供电管脚；或者，该第二管脚阵列中任意一行中所有管脚的类型相同，该第二管脚阵列中任意相邻两行中管脚的类型不同，即该第二管脚阵列的任意相邻两行中，一行均为信号传输管脚，另一行均为供电管脚。
相较于芯片的供电管脚，芯片的信号传输管脚的面积较大，因此，第三芯片的信号传输管脚与供电管脚按照行或者列间隔分布，能够减小第三芯片中管脚所占的面积，进而能够增加第三芯片单位面积内的管脚数目，满足芯片高度集成的需求。同时，第三芯片的信号传输管脚与电源管脚按照行或者列间隔分布，可以将不同列的信号传输管脚分割开来，降低信号传输管脚之间的互相影响，提高信号传输质量。
一个可能的实施方式中，为了提供稳定的结构和电学性能，集成芯片还包绝缘材料，该绝缘材料包裹第一芯片、垂直互连结构以及第二芯片。其中，以第一芯片的顶部为水平分界面，绝缘材料可以划分为上下布置的第一绝缘材料和第二绝缘材料，此时，第一绝缘材料包裹第一芯片以及垂直互连结构，第二绝缘材料包裹第二芯片。
第二方面，本申请提供了另一种集成芯片，该集成芯片包括：第一互连层，设置在第一互连层上的第一芯片，设置在第一芯片顶部表面上的第二互连层，设置在第二互连层顶部表面上的第二芯片以及第一垂直互连结构。其中，第二芯片包括第一部分和第二部分，第一部分与第一芯片在第二互连层上的投影重合，第二部分自第一部分沿着第二互连层突出于第一芯片的侧方；第一垂直互连结构设置在第一芯片的侧方，第一芯片和第二芯片通过第二互连层和第一垂直互连结构，绕过第一芯片，与第一互连层相连。
通过上述方案，集成芯片中的第二芯片的第二部通过垂直互连结构与设置在第一互连层上的第一芯片电性连接，能够尽量缩短第二芯片的第二部分与第一芯片之间的互连路径，以提高集成芯片数据传输速率，即提高集成芯片的带宽，并使得第二芯片的第二部分绕过了第一芯片，通过第一垂直互连结构与第一互连层电性连接，进而使得第一芯片以及第二芯片中均不需要制作TSV，能够降低集成芯片的的设计以及加工的复杂度，以及应力和翘曲的风险。并且，第二互连层不仅可以将第二芯片的第一部分底部的管脚从第二芯片的其他边扇出，增大管脚的间距，以方便第二芯片与第一芯片的管脚互连，还可以作为应力缓冲层，降低第二芯片与垂直互连结构互连时产生的应力。
另外，集成芯片的结构为常见的堆叠型封装结构，技术风险较低，技术可行性较高，并且具有较好的封装集成性能，易于其他的芯片封装在一起。
一个可能的实施方式中，第一垂直互连结构为多个焊球，或者为多个铜柱，或者为多个模封通孔TMV，或者为多个介质层通孔TDV，或者为多个绝缘层通孔TIV。第一垂直互连结构的一端通过第二互连层连接至第二芯片的第二部分的底部，第一垂直互连结构的另一端被直接连接至第一互连层中的导电层。
一个可能的实施方式中，第二芯片上设置有信号传输管脚，第二芯片上的所有第二信号传输管脚均设置在第二芯片的第二部分的底部(有源面)，能够缩短第一芯片与第二芯片之间的数据传输路径，进而可以提高集成芯片的带宽。
进一步地，第一芯片中用于与第二芯片的管脚连接的管脚可以设置在第一芯片靠近第二芯片的第二部分的一侧，以最大程度地缩短第一芯片与第二芯片的互连路径，提高集成芯片的带宽。
一个可能的实施方式中，第二芯片上还设置有供电管脚，第二芯片上的供电管脚中的部分或者全部设置在第二芯片的第二部分的底部。
一个可能的实施方式中，第二芯片上的信号传输管脚以及供电管脚呈阵列分布，构成第一管脚阵列。该第一管脚阵列的任意一列中所有管脚的类型相同，该第一管脚阵列的任意相邻两列中管脚的类型不同；或者，该第一管脚阵列中任意一行中所有管脚的类型相同，该第一管脚阵列中任意相邻两行中管脚的类型不同。
相较于芯片的供电管脚，芯片的信号传输管脚的面积较大，因此，上述方案中第二芯片的信号传输管脚与电源管脚按照行或者列间隔分布，能够减小第二芯片中管脚所占的面积，进而能够增加第二芯片单位面积内的管脚数目，满足芯片高度集成的需求，同时，第二芯片的信号传输管脚与电源管脚按照行或者列间隔分布，可以将不同列的信号传输管脚分割开来，降低信号传输管脚之间的互相影响，提高信号传输质量。
一个可能的实施方式中，第二芯片的第二部分底部设置有高速信号管脚，该高速信号管脚用于传输高速信号(高敏感性信号)，使得第二芯片的高速信号管脚直接通过第一垂直互连结构与第一互连层电性连接，能够缩短第二芯片中高速信号管脚与第一芯片之间的互连路径，而高速信号管脚中所传输的高速信号对集成芯片的为影响集成芯片带宽的主要因素，因此采用将高速信号管脚设置在第二芯片的第二部分的底部的方式，能够有效提高集成芯片的带宽。
一个可能的实施方式中，集成芯片包括至少两个第一芯片；或者，集成芯片包括至少两个所述第二芯片；或者，集成芯片包括至少两个第一芯片以及至少两个所述第二芯片。
一个可能的实施方式中，第一芯片为处理器芯片，第二芯片为存储器芯片。
一个可能的实施方式中，集成芯片还包括设置在第二芯片顶部表面上的第三互连层和设置在第三互连层顶部表面上的第三芯片。其中，第三芯片包括第三部分和第四部分，该第三部分与第二芯片在第三互连层上的投影重合，该第四部分自该第三部分沿着第三互连层突出于第二芯片的侧方；第二垂直互连结构设置于第二芯片的侧方，第三芯片通过第三互连层和第二垂直互连结构，绕过第一芯片，与第一互连层相连。
一个可能的实施方式中，第二垂直互连结构为多个焊球，或者为多个铜柱，或者为多个模封通孔TMV，或者为多个介质层通孔TDV，或者为多个绝缘层通孔TIV。第二垂直互连结构的一端通过第三互连层连接至第三芯片的第四部分的底部，第二垂直互连结构的另一端被直接连接至第一互连层中的导电层。
一个可能的实施方式中，第三芯片上设置有信号传输管脚，第三芯片上的所有第二信号传输管脚均设置在第二芯片的第四部分的底部(有源面)，能够缩短第一芯片与第三芯片之间的数据传输路径，进而可以提高集成芯片的带宽。
进一步地，第一芯片中用于与第三芯片的管脚连接的管脚可以设置在第一芯片靠近第三芯片的第四部分的一侧，以最大程度地缩短第一芯片与第三芯片的互连路径，提高集成芯片的带宽。
一个可能的实施方式中，第三芯片上设置有数据传输管脚，第三芯片上的所有信号传输管脚均设置于第三芯片的第四部分的底部，能够缩短第一芯片与第三芯片之间的数据传输路径，进而可以提高集成芯片的带宽。
进一步地，第一芯片中用于与第三芯片的管脚连接的管脚可以设置在第一芯片靠近第三芯片的第四部分的一侧，以最大程度地缩短第一芯片与第三芯片的互连路径，提高集成芯片的带宽。
一个可能的实施方式中，第三芯片上还设置有供电管脚，第三芯片上的供电管脚中的部分或全部设置在第三芯片的第四部分的底部。
一个可能的实施方式中，第三芯片的数据传输管脚以及供电管脚呈阵列分布，构成第二管脚阵列。其中，第二管脚阵列的任意一列中所有管脚的类型相同，该第二管脚阵列的任意相邻两列中管脚的类型不同，即该第二管脚阵列的任意相邻两列中，一列均为信号传输管脚，另一列均为供电管脚；或者，该第二管脚阵列中任意一行中所有管脚的类型相同，该第二管脚阵列中任意相邻两行中管脚的类型不同，即该第二管脚阵列的任意相邻两行中，一行均为信号传输管脚，另一行均为供电管脚。
相较于芯片的供电管脚，芯片的信号传输管脚的面积较大，因此，第三芯片的信号传输管脚与供电管脚按照行或者列间隔分布，能够减小第三芯片中管脚所占的面积，进而能够增加第三芯片单位面积内的管脚数目，满足芯片高度集成的需求。同时，第三芯片的信号传输管脚与电源管脚按照行或者列间隔分布，可以将不同列的信号传输管脚分割开来，降低信号传输管脚之间的互相影响，提高信号传输质量。
一个可能的实施方式中，第三芯片的第四部分底部设置有高速信号管脚，该高速信号管脚用于传输高速信号(高敏感性信号)，使得第三芯片的高速信号管脚直接通过第二垂直互连结构与第一互连层电性连接，能够缩短第三芯片中高速信号管脚与第一芯片之间的互连路径，而高速信号管脚中所传输的高速信号对集成芯片的为影响集成芯片带宽的主要因素，因此采用将高速信号管脚设置在第三芯片的第四部分的底部的方式，能够有效提高集成芯片的带宽。
一个可能的实施方式中，为了提供稳定的结构和电学性能，集成芯片还包绝缘材料，该绝缘材料包裹第一芯片、垂直互连结构以及第二芯片。其中，以第二互连层为水平分界面，绝缘材料进一步可以分成上下布置的第一绝缘材料和第二绝缘材料，此时，第一绝缘材料包裹第一芯片以及垂直互连结构，第二绝缘材料包裹第二芯片。
第三方面，本申请还提供了一种芯片，该芯片包括第一部分和第二部分，第一部分上设置有用于传输第一类信号的第一类管脚，第二部分上设置有用于传输第二类信号的第二类管脚，其中，第一类信号的传输速率大于第二类信号的传输速率。
通过上述方案，芯片管脚根据管脚所传输的信号的传输速率的不同，划分为第一类管脚和第二类管脚，并将第一类管脚和第二类管脚分别设置在芯片的第一部分和第二部分，使得芯片与其他芯片封装时，可以将芯片的第一类管脚通过尽可能短的互连路径与其他芯片连接，以提高封装后的芯片的带宽。
一个可能的实施方式中，第一类信号包括差分信号、中断信号、时钟信号以及复位信号中的至少一种。
附图说明
图1为现有技术中堆叠型封装集成的结构示意图；
图2为本申请提供的一种集成芯片的结构示意图之一；
图3为本申请提供的芯片的结构示意图；
图4为本申请提供的一种集成芯片的结构示意图之二；
图5a为本申请提供的一种集成芯片的结构示意图之三；
图5b为本申请提供的一种集成芯片的结构示意图之四；
图6为本申请提供的一种集成芯片中第一芯片以及第二芯片的管脚分布示意图；
图7a为本申请提供的第二芯片的管脚分布示意图之一；
图7b为本申请提供的第二芯片的管脚分布示意图之二；
图8a为本申请提供的第一芯片与第二芯片的管脚连接示意图之一；
图8b为本申请提供的第一芯片与第二芯片的管脚连接示意图之二；
图9为本申请提供的一种集成芯片的结构示意图之五；
图10为本申请提供的一种集成芯片的结构示意图之六；
图11a为本申请提供的一种集成芯片的结构示意图之七；
图11b为本申请提供的一种集成芯片的结构示意图之八；
图12a为本申请提供的一种集成芯片与其他芯片封装后的结构示意图之一；
图12b为本申请提供的一种集成芯片与其他芯片封装后的结构示意图之二；
图13为本申请提供的另一种集成芯片的结构示意图之一；
图14为本申请提供的另一种集成芯片的结构示意图之二；
图15a为本申请提供的另一种集成芯片的结构示意图之三；
图15b为本申请提供的另一种集成芯片的结构示意图之四；
图16为本申请提供的另一种集成芯片中第一芯片以及第二芯片的管脚分布示意图；
图17为本申请提供的另一种集成芯片的结构示意图之五；
图18为本申请提供的另一种集成芯片的结构示意图之六；
图19a为本申请提供的另一种集成芯片的结构示意图之七；
图19b为本申请提供的另一种集成芯片的结构示意图之八；
图20a为本申请提供的另一种集成芯片与其他芯片封装后的结构示意图之一；
图20b为本申请提供的另一种集成芯片与其他芯片封装后的结构示意图之二；
图21为本申请提供的一种芯片的结构示意图；
图22为本申请提供的一种芯片封装方法的流程示意图；
图23为本申请具体实施例提供的一种芯片封装方法的流程示意图。
具体实施方式
为了解决现有技术中的问题，本申请提出了一种芯片以及集成芯片。
需要说明的是，本申请实施例中所涉及的多个，是指两个或两个以上。另外，需要理解的是，在本申请实施例的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
如图2所示，本申请实施例提供了一种集成芯片200，集成芯片200包括：互连层210，设置在互连层210上的第一芯片220，第一垂直互连结构230，以及第二芯片240。由图2中可以看到，第二芯片240的一部分设置在所述第一芯片220的顶部表面，另一部分从所述第一芯片220的顶部向第一芯片220的侧方外延伸。因此，在本申请实施例中，第二芯片240可以被视为包括两部分：第一部分和第二部分。该第一部分贴附于第一芯片220的顶部表面。该第二部分自第一芯片220的顶部靠近第二芯片240的一端，向所述第一芯片220靠近第一垂直互连结构230的一侧延伸。第一垂直互连结构230与该第二部分设置在所述第一芯片220的同侧。该第二部分通过第一垂直互连结构230与互连层210电性连接，进而使得第二芯片240能够通过第一垂直互连结构230以及互连层210，与第一芯片220电性连接。
也就是说，第一芯片220与第二芯片240相错设置，第二芯片240的第一部分被第一芯片220支撑。第二芯片240的第二部分突出于第一芯片220的侧方，与同处于第一芯片220侧方的第一垂直互连结构230连接。也就是说，第二芯片240通过第一垂直互连结构230绕过第一芯片220，与互连层210电性连接。第一芯片220和第二240通过互连层210实现彼此之间的信号传输。当然，互连层210的底部还设置有对外的接口，第一芯片220和第二芯片240也通过互连层210与集成芯片200的外部收发信号。
如图3所示，芯片通常由半导体材料和布设于半导体材料上的电路层组成，半导体材料形成有晶体管等半导体器件，电路层中设置有多层的电路，通常设置有各种功能电路，这些电路与半导体材料上的半导体器件耦合，从而构成完整的芯片电路结构。其中，芯片中的电路层所处的一侧的表面称为有源面，芯片中的半导体材料所处的一侧的表面(与有源面相对应的另一面)称为无源面。在集成芯片200中，第一芯片220的底部，即第一芯片220的有源面221朝向互连层210，第二芯片240的底部，即第二芯片240的有源面241朝向互连层210，第二芯片240的第二部分的有源面241贴附于第一芯片220的无源面(即第一芯片220的顶部)。由于第一芯片220的有源面221以及第二芯片240的有源面241均朝向互连层210，第二芯片240的第二部分绕过了第一芯片220，通过第一垂直互连结 构230与互连层210电性连接，因此，第一芯片220中不需要通过TSV的方式给第二芯片240提供信号传输通道，降低了集成芯片200的应力和翘曲的风险，加工工艺的难度以及成本。
在本申请实施例中，第二芯片240的第一部分被设置在第一芯片220的顶部表面，是指该第一部分不经过其他诸如焊球，铜柱等支撑结构的支撑，直接贴装在第一芯片220的顶部。在具体实现的时候，为了保证第二芯片240贴在第一芯片220的顶部表面上的可靠性，可以在第二芯片240的第一部分和第一芯片220的顶部表面之间涂上黏贴材料。具体的，如图4所示，第二芯片240的第一部分通过黏贴材料250被固定在第一芯片220的顶部，即第二芯片240的第一部分的有源面241通过黏贴材料250被固定在第一芯片220的无源面上。其中，黏贴材料250可以为芯片粘合剂(die attach epoxy,DAF)或银浆(silver plating)等材料。此外，考虑到第一芯片220和第二芯片240在工作中会产生热量，为了提高或者避免第一芯片220和第二芯片240之间的热传导，也可以在第二芯片240的第一部分和第一芯片220之间填充导热或隔热材料。上述的黏贴材料250，导热材料或隔热材料都可以被视为将第二芯片240的第一部分固定在第一芯片220的顶部表面上时所需要进行的辅助手段。
从广义上来说，互连层210可以是通常所说的基板。在具体实现中，互连层210也可以是重布线层(redistribution layer,RDL)或者硅基板(英文又称为interposer)。互连层210内部包括多层介质层211，以及夹在介质层211之间的导电层212。导电层212上设置有电路布线，介质层211中则会设置有介质穿孔用于连通不同层上的电路布线。进一步的，互连层210可以通过如图5a所示的小铜柱260，亦或者如图5b所示的焊球270与第一芯片220电性连接。焊球270和小铜柱260通过介质穿孔与导电层212上的电路布线相连。
相较于硅基板的厚度，RDL的厚度较小，因此互连层210采用RDL能够降低集成芯片200的厚度，并且第一芯片220向下散热，采用较薄的RDL作为互连层210有利于第一芯片220的散热。
总结来说，第一垂直互连结构230是形成于第一芯片220周围的介质层，或者说塑封材料中的连通第二芯片220和互连层210的信号通道。第一垂直互连结构230可以有多种实现方式，比如，可以是竖立于第一芯片220的侧方的铜柱(copper pillar)；也可以是形成于第一芯片220侧方的介质材料中的模封通孔(through mold via，TMV)、介质层通孔(through dielectric via，TDV)，或者说、绝缘层通孔(through insulator via,TIV)，通过在上述孔中镀金属或者填充金属来形成信号通路；亦或者，第一垂直互连结构230也可以是形成于第二芯片220和互连层210之间的焊球(参照图5b中的焊球230)。
其中，第一垂直互连结构230的一端被直接连接至第二芯片240的第二部分的底部，第一垂直互连结构230的另一端被直接连接至互连层210中的导电层。
在具体实施中，第二芯片240上设置有信号传输管脚(即输入/输出管脚(input/output pad,I/O pad))，第二芯片240上所有的信号传输管脚均设置在第二芯片240的第二部分的底部，即第二芯片240的所有信号传输管脚均设置在第二芯片240的第二部分的有源面241，能够缩短第一芯片220与第二芯片240之间的信号传输路径，进而可以提高集成芯片200的带宽。
另外，第二芯片240还可以设置有供电管脚，第二芯片240上的所有信号供电管脚均设置于第二芯片240的第二部分的底部，即第二芯片240的所有供电管脚均设置在第二芯 片240的第二部分的有源面241。
相应地，第一芯片220中用于与第二芯片240的管脚连接的管脚也可以设置在第一芯片220靠近第二芯片240的第二部分的一侧，如图6所示(图6为从第二芯片240的顶部向下看的方向上集成芯片200的俯视图)，以最大程度地缩短第一芯片220与第二芯片240之间的互连路径，提高集成芯片200的带宽。
在具体实施中，第二芯片240上的信号传输管脚和供电管脚可以呈阵列分布，构成第一管脚整列。其中，如图7a所示(图7a为图6中所示的第二芯片240的管脚的分布示意图)，该第一管脚阵列的任意一列中所有管脚的类型相同，该第一管脚阵列的任意相邻两列中管脚的类型不同，即该第一管脚阵列的任意相邻两列中，一列均为信号传输管脚，另一列均为供电管脚。或者，如图7b(图7b为图6中所示的第二芯片240的管脚的分布示意图)所示，该第一管脚阵列中任意一行中所有管脚的类型相同，该第一管脚阵列中任意相邻两行中管脚的类型不同，即该第一管脚阵列的任意相邻两行中，一行均为信号传输管脚，另一行均为供电管脚。
通常情况下，相较于芯片的供电管脚，芯片的信号传输管脚的面积较大，因此，第二芯片240的信号传输管脚与供电管脚按照行或者列间隔分布，能够减小第二芯片240中管脚所占的面积，进而能够增加第二芯片240单位面积内的管脚数目，满足芯片高度集成的需求，同时，第二芯片240的信号传输管脚与供电管脚按照行或者列间隔分布，可以将不同列的信号传输管脚分割开来，降低信号传输管脚之间的互相影响，提高信号传输质量。
相应地，第一芯片220中用于与第二芯片240的管脚连接的管脚也可以按照与第二芯片240的管脚相对应的阵列排布，如图8a或图8b所示，图8a以及图8b为图6中所示的第一芯片220的管脚与第二芯片240的分布示意图。
需要说明的是，本申请实施例并不对第二芯片240的管脚构成的阵列的形状、阵列中每行包含的管脚数目、以及阵列中每列包含的管脚数目进行限定。其中，阵列中每行包含的管脚数目可以相同，也可以不同，阵列中每列包含的管脚数目可以相同，也可以不同。
在一个具体的实施方式中，第一芯片220可以为逻辑芯片(logic die)，如处理器芯片(如AP芯片)或知识产权(intellectual property，IP)核(cores)，第二芯片240可以为存储器(memory)(包括随机存储器(static random-access memory，SRAM)和DRAM)，倒装芯片封装(flip chip package)，无源器件(passive device)，转接板(interposer)，微机电系统(micro-electro-mechanical system，MEMS)等芯片或封装体。
为了提供稳定的结构和电学性能，集成芯片中通常会在芯片周围充满绝缘材料。在本申请实施例中，如图9所示，绝缘材料280包裹第一芯片220、第一垂直互连结构230以及第二芯片240。其中，以第一芯片220的顶部表面作为水平划分界面，绝缘材料280中可以进一步划分成上下布置的第一绝缘材料281和第二绝缘材料282。在这种情况下，第一绝缘材料281包裹第一芯片220以及第一垂直互连结构230，第二绝缘材料282包裹第二芯片240。
通常来说，为了保护第二芯片240，第二绝缘材料282的厚度需要大于或等于第二芯片240的厚度。从散热的角度来考虑，第二绝缘材料282高出第二芯片240的顶部的部分越薄，第二芯片240的散热就越好。
第一绝缘材料281与第二绝缘材料282可以相同，也可以不同。其中，第一绝缘材料281与第二绝缘材料282可以为氧化硅(Silicon Oxide)或者氮化硅(Nitride Oxide)或者 其他环氧树脂(epoxy)。
进一步地，如图10所示，互连层210的底部还设置有多个焊球270，用于实现第一芯片220以及第二芯片240与外部(如印刷电路板(printed circuit board，PCB)、其它芯片等)的互连，使得集成芯片200可以直接通过焊球270与外部互连。
具体实施中，集成芯片200可以包括至少两个第一芯片220，或者，包括至少两个第二芯片240，或者包括至少两个第一芯片220以及至少两个第二芯片240。例如，集成芯片200中包括两个第一芯片220以及一个第二芯片240，这两个第一芯片220均设置在第一互连层210上，第二芯片240设置在这两个第一芯片220的顶部，且位于这两个第一芯片220之间，即第二芯片240包括两个第一部分和位于这两个第一部分之间的第二部分，第二芯片240的两个第一部分分别设置在这两个第一芯片220的顶部表面上，第一垂直互连结构230位于这两个第一芯片220之间，一端直接连接在第二芯片240的第二部分的底部，另一端直接连接在互连层210中的导电层212。又如，如图11a所示，集成芯片200中包括一个第一芯片220和两个第二芯片240，这两个第二芯片240分别设置在第一芯片220的两端。
另外，如图11b所示，集成芯片200还可以包括第三芯片290和第二垂直互连结构300。其中，第三芯片290与第二芯片240类似，包括两部分：第三部分和第四部分，该第三部分被固定在第二芯片240的顶部表面上(该第三部分与第二芯片240的第一部分类似)，该第四部分突出于第二芯片240的侧方(该第四部分与第二芯片240的第二部分类似)。第二垂直互连结构300与该第四部分设置在第二芯片240的同侧，该第四部分通过第二垂直互连结构300与互连层210电性连接，进而使得第三芯片290能够通过第二垂直互连结构300以及互连层210，与第一芯片220电性连接。
与第二芯片240类似，第三芯片290的第三部分被设置在第二芯片220的顶部表面，是指该第三部分不经过其他诸如焊球，铜柱等支撑结构的支撑，直接贴装在第二芯片240的顶部。在具体实现的时候，为了保证第三芯片290贴在第二芯片240的顶部表面上的可靠性，可以在第三芯片290的第一部分和第二芯片240的顶部表面之间涂上黏贴材料。具体的，如图11b所示，第三芯片290的第三部分通过黏贴材料250被固定在第二芯片240的顶部表面上，即第三芯片290的第三部分的有源面通过黏贴材料250被固定在第二芯片240的无源面上。此外，考虑到第三芯片290和第二芯片240在工作中会产生热量，为了提高或者避免第三芯片290和第二芯片240之间的热传导，也可以在第三芯片290的第三部分和第二芯片240之间填充导热或隔热材料。上述的黏贴材料250，导热材料或隔热材料都可以被视为将第三芯片290的第三部分固定在第二芯片240的顶部表面上时所需要进行的辅助手段。
第二垂直互连结构300是形成于第一芯片220以及第二芯片240周围的介质层，或者说塑封材料中的连通第三芯片290和互连层210的信号通道。第二垂直互连结构300可以有多种实现方式，比如，可以是竖立于第一芯片220的侧方的铜柱；也可以是形成于第一芯片220侧方的介质材料中的TMV、TDV，或者说TIV，通过在上述孔中镀金属或者填充金属来形成信号通路；亦或者，第二垂直互连结构300也可以是形成于第三芯片290和互连层210之间的焊球。第二垂直互连结构300的一端被直接连接至第三芯片290的第四部分的底部，第二垂直互连结构300的另一端被直接连接至互连层210中的导电层。
在具体实施中，第三芯片290上设置有信号传输管脚，第三芯片290上所有的信号传 输管脚均设置在第三芯片290的第四部分的底部，即第三芯片290的所有信号传输管脚均设置在第三芯片290的第四部分的有源面，能够缩短第一芯片220与第三芯片290之间的信号传输路径，进而可以提高集成芯片200的带宽。
另外，第三芯片290还可以设置有供电管脚，第三芯片290上的所有信号供电管脚均设置于第三芯片290的第四部分的底部，即第三芯片290的所有供电管脚均设置在第三芯片290的第四部分的有源面。
相应地，第一芯片220中用于与第三芯片290的管脚连接的管脚也可以设置在第一芯片220靠近第三芯片290的第四部分的一侧，以最大程度地缩短第一芯片220与第三芯片290之间的互连路径，提高集成芯片200的带宽。
在具体实施中，第三芯片290上的信号传输管脚和供电管脚可以呈阵列分布，构成第二管脚阵列。其中，该第二管脚阵列的任意一列中所有管脚的类型相同，该第二管脚阵列的任意相邻两列中管脚的类型不同，即该第二管脚阵列的任意相邻两列中，一列均为信号传输管脚，另一列均为供电管脚。或者，该第二管脚阵列中任意一行中所有管脚的类型相同，该第二管脚阵列中任意相邻两行中管脚的类型不同，即该第二管脚阵列的任意相邻两行中，一行均为信号传输管脚，另一行均为供电管脚。
通常情况下，相较于芯片的供电管脚，芯片的信号传输管脚的面积较大，因此，第三芯片290的信号传输管脚与供电管脚按照行或者列间隔分布，能够减小第三芯片290中管脚所占的面积，进而能够增加第三芯片290单位面积内的管脚数目，满足芯片高度集成的需求，同时，第三芯片290的信号传输管脚与供电管脚按照行或者列间隔分布，可以将不同列的信号传输管脚分割开来，降低信号传输管脚之间的互相影响，提高信号传输质量。
相应地，第一芯片220中用于与第三芯片290的管脚连接的管脚也可以按照与第三芯片290的管脚相对应的阵列排布。
在具体实施的过程中，在第三芯片290的顶部还可以按照与第三芯片290在第二芯片240上的设置方式设置有第四芯片，其中，第四芯片的一部分被固定在第三芯片290的顶部表面上，该第四芯片的另一部分突出于第三芯片290的侧方，第四芯片的另一部分的底部通过第三垂直互连结构与互连层210连接。以此类推，第四芯片的顶部还可以设置第五芯片等等。
需要说明的是，本申请实施例中并不对集成芯片200中的第一芯片220、第二芯片240的个数以及第三芯片290的个数进行限定。集成芯片200中的第一芯片220、第二芯片240以及第三芯片290的个数根据集成芯片200的具体性能(如带宽、面积、处理速度等)要求确定。第三芯片290的芯片类型可以与第二芯片240相同，也可以不同。
通过上述方案，集成芯片200中的第二芯片240通过第一垂直互连结构230与设置在互连层210上的第一芯片220电性连接，能够尽量缩短第二芯片240与第一芯片220之间的互连路径，以提高集成芯片200数据传输速率，即提高集成芯片200的带宽。并且，集成芯片200中第一芯片220的有源面以及第二芯片240的有源面均朝向互连层210，第二芯片240的第二部分绕过了第一芯片220，通过第一垂直互连结构230与互连层210电性连接，进而使得第一芯片220以及第二芯片240中均不需要制作TSV，能够降低集成芯片200的的设计以及加工的复杂度，以及应力和翘曲的风险。
另外，集成芯片200的结构为常见的堆叠型封装结构，技术风险较低，技术可行性较高，并且具有较好的封装集成性能，易于其他的芯片封装在一起。具体地，集成芯片200 可以通过堆叠封装技术与其他芯片封装在一起。例如，如图12a所示，集成芯片200可以通过FOPOP方式与其他芯片封装在一起，或者，集成芯片200也可以通过其它的POP方式与其他芯片封装在一起，如图12b所示。
如图13所示，本申请实施例还提供了另一种集成芯片1300，集成芯片1300包括：第一互连层1310，设置在第一互连层1310上的第一芯片1320，第一垂直互连结构1330，设置在第一芯片的顶部表面上的第二互连层1340，以及设置在第二互连层1340的顶部表面上的第二芯片1350。由图13可知，第二芯片1350的一部分位于第二互连层1340上与第一芯片1320耦合的部分，第二芯片1350的另一部分位于第二互连层1340上向第一芯片1320的侧方延伸的部分，即第二芯片1350包括第一部分和第二部分这两部分，该第一部分与第一芯片1320在第二互连层1340上的投影重合，该第二部分从该第一部分沿着第二互连层1340突出于第一芯片1320的侧方。第一垂直互连结构1330设置在第一芯片1320的侧方，第一芯片1320和第二芯片1350通过第二互连层1340和第一垂直互连结构1330，绕过第一芯片1320，与第一互连层1310电性连接。当然，如前文所述，第二芯片1350和第二互连层1340的顶部表面之间也可以填充有粘结材料，导热材料或者绝热材料。
其中，第二芯片1350的第二部分的底部可以设置第二互连层1340，也可以不设置第二互连层1340，即第二互连层1340可以延伸到第二芯片1350的第二部分的底部，也可以只延伸到第二芯片1350的第一部分的底部。当第二芯片1350的第二部分的底部设置有第二互连层1340时，第二互连层1340中用于连接第二芯片1350的第二部分与第一垂直互连结构1330的部分也是通过垂直互连的方式实现二者的电性连接，即当第二芯片1350的第二部分的底部设置有第二互连层1340时，第二互连层1340中用于连接第二芯片1350的第二部分与第一垂直互连结构1330的部分也是第一垂直互连结构1330的一部分。第二互连层1340不仅可以将第二芯片1350的第一部分底部的管脚从第二芯片1350的其他边扇出，增大管脚的间距，以方便第二芯片1350与第一芯片1320的管脚互连，还可以作为应力缓冲层，降低第二芯片1350与第一垂直互连结构1330互连时产生的应力。当然，第一互连层1310的底部还设置有对外的接口，第一芯片1320和第二芯片1350也通过第一互连层1310与集成芯片1300的外部进行信号收发。
第一芯片1320的有源面1321朝向第一互连层1310，第二芯片1350的有源面1351朝向第二互连层1340，且第二芯片1350的第一部分通过第二互连层1340以及第一垂直互连结构1330，绕过第一芯片1320，与第一互连层1310电性连接，第二芯片1350的第二部分通过第一垂直互连结构1330直接与第一互连层1310电性连接，因此，第二芯片1350中不需要通过加工TSV的方式为第二芯片1350提供信号传输通道，降低了集成芯片1300的应力和翘曲的风险，加工工艺的难度以及成本。
在具体实施中，第一芯片1320可以为逻辑芯片，如处理器或知识产权核，第二芯片1350可以为存储器(包括SRAM和DRAM)，倒装芯片封装，无源器件，转接板，MEMS等芯片或封装体。
进一步地，如图14所示，第一芯片1320可以通过黏贴材料1360固定在第二互连层1340的底部。其中，黏贴材料1360可以为DAF或银浆等材料。
在一个具体的实施方式中，第一互连层1310可以是RDL或者硅基板，第二互连层1340也可以是RDL或者硅基板。以第一互连层1310为例，第一互连层1310可以通过如图15a所示的多个小铜柱1370(设置在第一互连层1310的顶部(即朝向第一芯片1320的有源面 1321的表面))，或者如图15b所示的多个焊球1380，与第一芯片1320电性连接，其中，小铜柱1370和焊球1380通过介质穿孔与第一互连层1310中的导电层上的电路布线相连。第二互连层1340与第二芯片1350实现电性连接的方式，与第一互连层1310与第一芯片1320实现电性连接的方式类似，此处不再赘述。
相较于硅基板，RDL的厚度较小，因此第一互连层1310以及第二互连层1340采用RDL能够降低集成芯片1300的厚度，并且第一芯片1320向下散热，采用较薄的RDL作为第一互连层1310有利于第一芯片220的散热。
总的来说，第一垂直互连结构1330是形成于第一芯片1320周围的介质层，或者说塑封材料中的连通第二芯片1350和第一互连层1310的信号通道。第一垂直互连结构1330可以有多种实现方式，比如，可以是竖立于第一芯片1320的侧方的铜柱；也可以是形成于第一芯片1320侧方的介质材料中的TMV、TDV，或者说TIV，通过在上述孔中镀金属或者填充金属来形成信号通路；亦或者，第一垂直互连结构1330也可以是形成于第二芯片1350和第一互连层1310之间的焊球。第一垂直互连结构1330的一端通过第二互连层1340连接至第二芯片1350的第二部分的底部，第二垂直互连结构1330的另一端被直接连接至第一互连层1310中的导电层。
在一个可能的实施例中，第二芯片1350上设置有信号传输管脚，第二芯片1350上所有的信号传输管脚均设置在第二芯片1350的第二部分的底部，即第二芯片1350的所有信号传输管脚均设置在第二芯片1350的第二部分的有源面，能够缩短第一芯片1320与第二芯片1350之间的信号传输路径，进而可以提高集成芯片1300的带宽。
另外，第二芯片1350还可以设置有供电管脚，第二芯片1350上的所有信号供电管脚或者部分供电管脚设置于第二芯片1350的第二部分的底部，即第二芯片1350的所有供电管脚或者部分供电管脚设置在第二芯片1350的第二部分的有源面。
相应地，第一芯片1320中用于与第二芯片1350的管脚连接的管脚也可以设置在第一芯片1320靠近第二芯片1350的第二部分的一侧，以最大程度地缩短第一芯片1320与第二芯片1350之间的互连路径，提高集成芯片1300的带宽。
在另一个可能的实施方式中，第二芯片1350的第二部分底部(有源面)设置有高速信号管脚，第二芯片1350的第一部分底部(有源面)设置有非高速信号管脚，该高速信号管脚用于传输高速信号(高敏感性信号)，使得第二芯片1350的高速信号管脚直接通过第一垂直互连结构1330与第一互连层1310电性连接，能够缩短第二芯片1350中高速信号管脚与第一芯片1310之间的互连路径，而高速信号管脚中所传输的高速信号对集成芯片1300的为影响集成芯片1300带宽的主要因素，因此采用将高速信号管脚设置在第二芯片1350的第二部分的底部的方式，能够提高集成芯片1300的带宽。其中，当信号满足以下任意一个条件时则认为该信号为高速信号：a、信号沿着传输路径传输时发生了严重的趋肤效应和电离损耗；b、信号的上升沿或者下降沿小于50ps；c、信号的传输路径的长大于1/6λ，λ为该信号的波长；d、信号的频率大于50MHz，非高速信号为除上述高速信号外的其他信号。
相应地，第一芯片1320中用于与第二芯片1350的高速信号管脚连接的管脚设置在第一芯片1320靠近第二芯片1350的第二部分的一侧，如图16所示，以最大程度地缩短第一芯片1320与第二芯片1350之间的互连路径，提高集成芯片1300的带宽。
在具体实施中，第二芯片1350上的信号传输管脚和供电管脚可以呈阵列分布，构成 第一管脚整列。其中，如图7a所示，该第一管脚阵列的任意一列中所有管脚的类型相同，该第一管脚阵列的任意相邻两列中管脚的类型不同，即该第一管脚阵列的任意相邻两列中，一列均为信号传输管脚，另一列均为供电管脚。或者，如图7b所示，该第一管脚阵列中任意一行中所有管脚的类型相同，该第一管脚阵列中任意相邻两行中管脚的类型不同，即该第一管脚阵列的任意相邻两行中，一行均为信号传输管脚，另一行均为供电管脚。也就是说，第二芯片1350的管脚构成的阵列中不同类型的按照行或列间隔分布。相应地，第一芯片1320中用于与第二芯片1350的管脚连接的管脚也可以按照与第二芯片1350的管脚相对应的阵列排布。
通常情况下，相较于芯片的供电管脚，芯片的信号传输管脚的面积较大，因此，第二芯片1350的信号传输管脚与供电管脚按照行或者列间隔分布，能够减小第二芯片1350中管脚所占的面积，进而能够增加第二芯片1350单位面积内的管脚数目，满足芯片高度集成的需求，同时，第二芯片1350的信号传输管脚与供电管脚按照行或者列间隔分布，可以将不同列的信号传输管脚分割开来，降低信号传输管脚之间的互相影响，提高信号传输质量。
为了提供稳定的结构和电学性能，集成芯片中通常会在芯片周围充满绝缘材料。在本申请实施例中，如图17所示，绝缘材料1390包裹第一芯片1320、第一垂直互连结构1330以及第二芯片1350。其中，以第二互连层1340为水平分界面，绝缘材料1390进一步可以分成上下布置的第一绝缘材料1391和第二绝缘材料1392，此时，第一绝缘材料1391包裹第一芯片1320以及第一垂直互连结构1330，第二绝缘材料1392包裹第二芯片1350。
通常情况下，为了保护第二芯片1350，第二绝缘材料1392的厚度需要大于或等于第二芯片1350的厚度，但是从芯片散热的角度考虑，第二绝缘材料1392的厚度越接近第二芯片1350的厚度，越有利于第二芯片1350的散热。另外，第一绝缘材料1391与第二绝缘材料1392可以相同，也可以不同。其中，第一绝缘材料1391与第二绝缘材料1392可以为氧化硅或者氮化硅或者其他环氧树脂。
进一步地，如图18所示，第一互连层1310的底部还设置有多个焊球1380，用于实现第一芯片1320以及第二芯片1350与外部(如PCB、其它芯片等)的互连。
在具体实施中，集成芯片1300包括至少两个第一芯片1320，或者，包括至少两个第二芯片1350(例如，如图19a所示)，或者包括至少两个第一芯片1320以及至少两个第二芯片1350。
如图19b所示，集成芯片1300还可以包括设置在所述第二芯片顶部表面上的第三互连层1400，设置在第三互连层1400顶部表面上的第三芯片1410以及第二垂直互连结构1420。其中，第三芯片1410与第二芯片1350类似，包括第三部分和第四部分，该第三部分与第二芯片1350在第三互连层1400上的投影重合，该第四部分自第三部分沿着第三互连层1400突出于第二芯片1350的侧方；第二垂直互连结构1420设置于第二芯片1350的侧方，第三芯片1410通过第三互连层1400和第二垂直互连结构1420，绕过第一芯片1320，与第一互连层1310相连。
其中，第三芯片1410的第四部分的底部可以设置第三互连层1400，也可以不设置第三互连层1400，即第三互连层1400可以延伸到第三芯片1410的第四部分的底部，也可以只延伸到第三芯片1410的第四部分的底部。当第三芯片1410的第四部分的底部设置有第三互连层1400时，第三互连层1400中用于连接第三芯片1410的第四部分与第二垂直互 连结构1420的部分也是通过垂直互连的方式实现二者的电性连接，即当第三芯片1410的第四部分的底部设置有第三互连层1400时，第三互连层1400中用于连接第三芯片1410的第四部分与第二垂直互连结构1420的部分也是第二垂直互连结构1420的一部分。第三互连层1400不仅可以将第三芯片1410的第三部分底部的管脚从第三芯片1410的其他边扇出，增大管脚的间距，以方便第三芯片1410与第一芯片1320的管脚互连，还可以作为应力缓冲层，降低第三芯片1410与第二垂直互连结构1420互连时产生的应力。另外，第三互连层1400靠近第二芯片1350的第一部分的一端，也可以设置有垂直互连结构，以使第二芯片1350的第一部分可以通过第三互连层1400以及该垂直互连结构与第二互连层1340实现电性连接。
总的来说，第二垂直互连结构1420是形成于第二芯片1350周围的介质层，或者说塑封材料中的连通第三芯片1410和第一互连层1310的信号通道。第二垂直互连结构1420可以有多种实现方式，比如，可以是竖立于第二芯片1350的侧方的铜柱；也可以是形成于第二芯片1350侧方的介质材料中的TMV、TDV，或者说TIV，通过在上述孔中镀金属或者填充金属来形成信号通路；亦或者，第二垂直互连结构1420也可以是形成于第三芯片1410和第一互连层1310之间的焊球。第二垂直互连结构1420的一端通过第三互连层1400连接至第三芯片1410的第四部分的底部，第二垂直互连结构1420的另一端被直接连接至第一互连层1310中的导电层。
在一个可能的实施例中，第三芯片1410上设置有信号传输管脚，第三芯片1410上所有的信号传输管脚均设置在第三芯片1410的第四部分的底部，即第三芯片1410的所有信号传输管脚均设置在第三芯片1410的第四部分的有源面，能够缩短第一芯片1320与第三芯片1410之间的信号传输路径，进而可以提高集成芯片1300的带宽。
另外，第三芯片1410还可以设置有供电管脚，第三芯片1410上的所有信号供电管脚或者部分供电管脚设置于第三芯片1410的第四部分的底部，即第三芯片1410的所有供电管脚或者部分供电管脚设置在第三芯片1410的第四部分的有源面。
相应地，第一芯片1320中用于与第三芯片1410的管脚连接的管脚也可以设置在第一芯片1320靠近第三芯片1410的第四部分的一侧，以最大程度地缩短第一芯片1320与第三芯片1410之间的互连路径，提高集成芯片1300的带宽。
在具体实施中，第三芯片1410上的信号传输管脚和供电管脚可以呈阵列分布，构成第二管脚整列。其中，如图7a所示，该第二管脚阵列的任意一列中所有管脚的类型相同，该第二管脚阵列的任意相邻两列中管脚的类型不同，即该第二管脚阵列的任意相邻两列中，一列均为信号传输管脚，另一列均为供电管脚。或者，如图7b所示，该第二管脚阵列中任意一行中所有管脚的类型相同，该第一管脚阵列中任意相邻两行中管脚的类型不同，即该第二管脚阵列的任意相邻两行中，一行均为信号传输管脚，另一行均为供电管脚。相应地，第一芯片1320中用于与第三芯片1410的管脚连接的管脚也可以按照与第三芯片1410的管脚相对应的阵列排布。
通常情况下，相较于芯片的供电管脚，芯片的信号传输管脚的面积较大，因此，第三芯片1410的信号传输管脚与供电管脚按照行或者列间隔分布，能够减小第三芯片1410中管脚所占的面积，进而能够增加第三芯片1410单位面积内的管脚数目，满足芯片高度集成的需求，同时，第三芯片1410的信号传输管脚与供电管脚按照行或者列间隔分布，可以将不同列的信号传输管脚分割开来，降低信号传输管脚之间的互相影响，提高信号传输 质量。
在另一个可能的实施方式中，第三芯片1410的第四部分底部(有源面)设置有高速信号管脚，第三芯片1410的第三部分底部(有源面)设置有非高速信号管脚，使得第三芯片1410的高速信号管脚直接通过第二垂直互连结构1420与第一互连层1310电性连接，能够缩短第三芯片1410中高速信号管脚与第一芯片1310之间的互连路径，而高速信号管脚中所传输的高速信号对集成芯片1300的为影响集成芯片1300带宽的主要因素，因此采用将高速信号管脚设置在第二芯片1350的第二部分的底部的方式，能够提高集成芯片1300的带宽。
相应地，第一芯片1320中用于与第三芯片1410的高速信号管脚连接的管脚设置在第一芯片1320靠近第三芯片1410的第四部分的一侧，以最大程度地缩短第一芯片1320与第三芯片1410之间的互连路径，提高集成芯片1300的带宽。
在具体实施的过程中，在第三芯片1410的顶部还可以按照与第三芯片1410在第二芯片1350上的设置方式设置有第四芯片，其中，第四芯片的一部分与该第四芯片在设置于第三芯片1410顶部表面的互连层上的投影重合，第四芯片的另一部分自该第四芯片的一部分沿着设置于第三芯片1410顶部表面的互连层突出于第三芯片1410的侧方，第四芯片的另一部分的底部通过第三垂直互连结构与第一互连层1310连接。以此类推，第四芯片的顶部还可以设置第五芯片等等。
需要说明的是，本申请实施例中并不对集成芯片1300中的第一芯片1320、第二芯片1350的个数以及第三芯片1410的个数进行限定。集成芯片1300中的第一芯片1320、第二芯片1350的个数以及第三芯片1410的个数根据集成芯片1300的具体性能(如带宽、面积、处理速度等)要求确定。
通过上述方案，集成芯片1300中的第二芯片1350的第二部通过第一垂直互连结构1330与设置在第一互连层1310上的第一芯片1320电性连接，能够尽量缩短第二芯片1350的第二部分与第一芯片1320之间的互连路径，以提高集成芯片1300数据传输速率，并且，使得第二芯片1350的第二部分绕过了第一芯片1320，通过第一垂直互连结构1340与第一互连层1310电性连接，进而使得第一芯片1320以及第二芯片1350中均不需要制作TSV，能够降低集成芯片1300的的设计以及加工的复杂度，以及应力和翘曲的风险。
另外，集成芯片1300的结构为常见的堆叠型封装结构，技术风险较低，技术可行性较高，并且具有较好的封装集成性能，易于其他的芯片封装在一起。具体地，集成芯片1300可以通过堆叠封装技术与其他芯片封装在一起。例如，如图20a所示，集成芯片1300可以通过FOPOP方式与其他芯片封装在一起，或者，集成芯片1300也可以通过其它的POP方式与其他芯片封装在一起，如图20b所示。
如图21所示，本申请实施例还提供了一种芯片2100，芯片2100包括第一部分和第二部分，其中，芯片2100的第一部分上设置有用于传输第一类信号的第一类管脚2110，芯片2100的第二部分上设置有用于传输第二类信号的第二类管脚2120，该第一类信号的传输速率大于该第二类信号的传输速率。
具体实施中，芯片2100可以为存储器(包括SRAM和DRAM)，倒装芯片封装，无源器件，转接板，MEMS等芯片或封装体。
进一步地，该第一类信号包括差分信号、中断信号、时钟信号以及复位信号等高速信号中的至少一种。需要说明的是，上述关于第一类信号的描述仅为举例说明，并不对本申 请实施例构成限定。
进一步地，第一类管脚2110呈阵列分布，第一类管脚中包括信号传输管脚和供电管脚(其中，供电管脚用于为信号传输管脚供电)。其中，该阵列的任意一列中所有管脚的类型相同，且该阵列的任意相邻两列中管脚的类型不同，如图7a所示；或者，该阵列中任意一行中所有管脚的类型相同，该阵列中任意相邻两行中管脚的类型不同，如图7b所示。也就是说，芯片2100的第一类管脚2110构成的阵列中不同类型的按照行或列间隔分布。
通常情况下，相较于芯片的供电管脚，芯片的信号传输管脚的面积较大，因此，第一类管脚2110阵列分布，且第一类管脚2110中的信号传输管脚与电源管脚按照行或者列间隔分布，能够减小芯片2100中管脚所占的面积，进而可以增加芯片2100中单位面积内的管脚数目，满足芯片高度集成的需求，同时，第一类管脚2110中的信号传输管脚与电源管脚按照行或者列间隔分布，可以将不同列的信号传输管脚分割开来，降低信号传输管脚之间的互相影响，提高信号传输质量。
进一步地，第二类管脚2120也可以呈阵列分布，第二类管脚2120中包括信号传输管脚和供电管脚。其中，该阵列的任意一列中所有管脚的类型相同，且该阵列的任意相邻两列中管脚的类型不同，如图7a所示；或者，该阵列中任意一行中所有管脚的类型相同，该阵列中任意相邻两行中管脚的类型不同，如图7b所示。也就是说，芯片2100的第二类管脚2120构成的阵列中不同类型的按照行或列间隔分布。
通过上述方案，芯片2100的管脚根据管脚所传输的信号的传输速率的不同，划分为第一类管脚2110和第二类管脚2120，并将第一类管脚2110和第二类管脚2120分别设置在芯片2100的第一部分和第二部分，使得芯片2100与其他芯片封装时，可以将芯片2100的第一类管脚2110通过尽可能短的互连路径与其他芯片连接，以提高封装后的芯片的带宽。
如图22所示，本申请实施例还提供了一种芯片封装方法，该方法主要包括以下步骤：
S2201：在第一芯片的第一部分的有源面上制作垂直互连结构。
其中，该垂直互连结构可以为可以是铜柱、TMV、TDV、TIV或者焊球中的任意一种。
S2202：将该第一芯片的第二部分的有源面黏贴在第二芯片的无源面上。
具体地，可以通过黏贴材料将该第一芯片的第二部分的有源面黏贴在第二芯片的无源面上。其中，该黏贴材料可以为DAF或银浆等材料。
S2203：在该垂直互连结构以及该第二芯片的有源面上制作互连层。其中，该互连层可以为基板或者布线层。
在步骤S2201中，在第一芯片的第一部分的有源面上制作垂直互连结构，具体包括以下步骤：i、将该第一芯片的有源面键合在载片(carrier)上；ii、制备第一绝缘材料，以形成第一封装体，其中，该第一绝缘材料包裹该第一芯片；iii、去掉该载片，在该第一封装体中该第一部分有源面上制备该垂直互连结构。其中，该载片包括但不限于硅片以及玻璃片等中的任意一种，该载片和第一芯片中间设置有临时键合层，以便后续解键合。
此时，在步骤S2202中，将该第二芯片的无源面黏贴在该第一封装体中从该第二部分有源面所在的位置开始的表面。
在制备第一绝缘材料之后，去掉该载片之前，还包括：对该第一封装体进行减薄处理。具体地，可以通过包括但不限于研磨、抛光或者两者结合等工艺，将该第一封装体减薄到设定厚度，该设定厚度根据实际的加工工艺以及加工成本确定。例如，当第一芯片的厚度较大时，可以将该第一封装体减薄到与第一芯片的厚度相同。
在步骤2203中，具体可以通过以下方法在该垂直互连结构以及该第二芯片的有源面上制作互连层：1、制备第二绝缘材料，以形成第二封装体，其中，该第二绝缘材料包裹该垂直互连结构以及该第二芯片；2、在该第二封装体中该垂直互连结构以及该第二芯片的有源面所在的表面上制备该互连层。其中，该第二绝缘材料与该第一绝缘材料可以相同，也可以不同。
其中，制备第二绝缘材料之后，在该第二封装体中该垂直互连结构以及该第二芯片的有源面所在的表面上制备该互连层之前，还包括：对该第二封装体进行研磨，露出该垂直互连结构以及该第二芯片的有源面上的小铜柱，其中，该第二芯片的有源面上的小铜柱可以预先加工在该第二芯片的有源面上。
进一步地，执行步骤S2203之后，还可以在该互连层上制备焊球，以使该第一芯片与该第二芯片封装后的得到的芯片可以通过焊球与外部连接。
下面以封装形成如图5a所示的集成芯片200为例，对本申请提供的芯片封装方法进行详细说明。其中，第一芯片220为处理器芯片，第二芯片240为从存储器制造商购买的存储器封装体中分离出来的HBM——DRAM芯片，其中，分离出来的DRAM芯片的带宽可以达到256Gbps，此外，分离出来的DRAM芯片位宽也比传统堆叠型封装结构中DRAM封装体位宽更高，可以达到1024位。
封装形成如图5a所示的集成芯片200主要包括以下步骤：
S2301：将第二芯片240的有源面临时键合到载片上。其中，该载片与第二芯片240之间设置有临时键合层。
S2302：利用塑封料对键合在载片上的第二芯片240进行塑封，以得到第一封装体。
S2303：对该第一封装体进行减薄处理。
S2304：将载片与减薄处理后的第一封装体分离，去掉该载片(即解键合)。
S2305：在减薄处理后的第一封装体中第二芯片240的第二部分的有源面上制作铜柱。
S2306：通过黏贴材料，将第一芯片220的无源面黏贴在第一封装体中第二芯片240的第一部分的有源面上。其中，第一芯片220的有源面上设置有多个小铜柱。
S2307：利用塑封料对铜柱以及第一芯片220进行塑封，以得到第二封装体。
S2308：对第二封装体进行研磨处理，露出在第二芯片240的第一部分上制备的铜柱以及第一芯片220的有源面上的小铜柱。
S2309：在第二封装体上露出铜柱以及小铜柱的而表面上制作RDL以及焊球。
制备集成芯片1300也可以采用与上述方法类似的方法，细微差别在于，在对第二芯片1350进行塑封，得到第一封装体后，需要先在第一封装体的表面上通过生长的方式生成第二互连层1340的介质材料和金属布线，然后再在第二互连层1340上制作或生长铜柱等垂直互连结构、黏贴第一芯片1320等。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (27)

  1. 一种集成芯片，其特征在于，包括：
    互连层；
    设置在所述互连层上的第一芯片；
    第二芯片，其中，所述第二芯片包括第一部分和第二部分，所述第一部分被固定在所述第一芯片的顶部表面上，所述第二部分突出于所述第一芯片的侧方；
    第一垂直互连结构，设置在所述第一芯片的侧方，所述第二部分通过所述第一垂直互连结构与所述互连层电性连接。
  2. 如权利要求1所述的集成芯片，其特征在于，所述第二芯片上设置有信号传输管脚，所述第二芯片上的所有信号传输管脚均设置于所述第二部分的底部。
  3. 如权利要求1或2所述的集成芯片，其特征在于，所述第一垂直互连结构为多个焊球，或者为多个铜柱，或者为多个模封通孔TMV，或者为多个介质层通孔TDV，或者为多个绝缘层通孔TIV；
    所述第一垂直互连结构的一端被直接连接至所述第二芯片的第二部分的底部，所述第一垂直互连结构的另一端被直接连接至所述互连层中的导电层。
  4. 如权利要求2所述的集成芯片，其特征在于，所述第二芯片还设置有供电管脚，所述第二芯片上的所有信号供电管脚均设置于所述第二部分的底部。
  5. 如权利要求4所述的集成芯片，其特征在于，所述第二芯片上的信号传输管脚以及供电管脚构成第一管脚阵列；
    其中，所述第一管脚阵列的任意一列中所有管脚的类型相同，所述第一管脚阵列的任意相邻两列中管脚的类型不同；或者，所述第一管脚阵列中任意一行中所有管脚的类型相同，所述第一管脚阵列中任意相邻两行中管脚的类型不同。
  6. 如权利要求1-5任意一项所述的集成芯片，其特征在于，所述第一芯片为处理器芯片，所述第二芯片为存储器芯片。
  7. 如权利要求1-6任意一项所述的集成芯片，其特征在于，所述第一部分通过黏贴材料被固定在所述第一芯片的顶部表面上。
  8. 如权利要求1-7任意一项所述的集成芯片，其特征在于，所述集成芯片包括至少两个所述第一芯片；和/或，所述集成芯片包括至少两个所述第二芯片。
  9. 如权利要求1-8任意一项所述的集成芯片，其特征在于，所述集成芯片还包括：
    第三芯片，其中，所述第三芯片包括第三部分和第四部分，所述第三部分被固定在所述第二芯片的顶部表面上，所述第四部分突出于所述第二芯片的侧方；
    第二垂直互连结构，设置在所述第二芯片的侧方，所述第四部分通过所述第二垂直互连结构与所述互连层电性连接。
  10. 如权利要求9所述的集成芯片，其特征在于，所述第三芯片上设置有信号传输管脚，所述第三芯片上的所有信号传输管脚均设置于所述第四部分的底部。
  11. 如权利要求9或10所述的集成芯片，其特征在于，所述第二垂直互连结构为多个焊球，或者为多个铜柱，或者为多个模封通孔TMV，或者为多个介质层通孔TDV，或者为多个绝缘层通孔TIV；
    所述第二垂直互连结构的一端被直接连接至所述第四部分的底部，所述第二垂直互连 结构的另一端被直接连接至所述互连层中的导电层。
  12. 如权利要求10所述的集成芯片，其特征在于，所述第三芯片还设置有供电管脚，所述第三芯片上的所有信号供电管脚均设置于所述第四部分的底部。
  13. 如权利要求12所述的集成芯片，其特征在于，所述第三芯片上的信号传输管脚以及供电管脚构成第二管脚阵列；
    其中，所述第二管脚阵列的任意一列中所有管脚的类型相同，所述第二管脚阵列的任意相邻两列中管脚的类型不同；或者，所述第二管脚阵列中任意一行中所有管脚的类型相同，所述第二管脚阵列中任意相邻两行中管脚的类型不同。
  14. 一种集成芯片，其特征在于，包括：
    第一互连层；
    设置在所述第一互连层上的第一芯片；
    设置在所述第一芯片顶部表面上的第二互连层；
    设置在所述第二互连层顶部表面上的第二芯片；
    其中，所述第二芯片包括第一部分和第二部分，所述第一部分与所述第一芯片在所述第二互连层上的投影重合，所述第二部分自所述第一部分沿着所述第二互连层突出于第一芯片的侧方；
    第一垂直互连结构，设置于所述第一芯片的侧方，所述第一芯片和第二芯片通过所述第二互连层和所述第一垂直互连结构，绕过所述第一芯片，与所述第一互连层相连。
  15. 如权利要求14所述的集成芯片，其特征在于，所述第二芯片上至少设置有信号传输管脚，所述第二芯片上的所有信号传输管脚均设置于所述第二部分的底部。
  16. 如权利要求14或15所述的集成芯片，其特征在于，所述第一垂直互连结构为多个焊球，或者为多个铜柱，或者为多个模封通孔TMV，或者为多个介质层通孔TDV，或者为多个绝缘层通孔TIV；
    所述第一垂直互连结构的一端通过所述第二互连层连接至所述第二芯片的第二部分的底部，所述第一垂直互连结构的另一端被直接连接至所述第一互连层中的导电层。
  17. 如权利要求14所述的集成芯片，其特征在于，所述第二芯片上还设置有供电管脚，所述第二芯片上的供电管脚中的部分或全部设置在所述第二部分的底部。
  18. 如权利要求17所述的集成芯片，其特征在于，所述第二芯片上的信号传输管脚和供电管脚构成第一管脚阵列；
    其中，所述第一管脚阵列的任意一列中所有管脚的类型相同，所述第一管脚阵列的任意相邻两列中管脚的类型不同；或者，所述第一管脚阵列中任意一行中所有管脚的类型相同，所述第一管脚阵列中任意相邻两行中管脚的类型不同。
  19. 如权利要求14-18任意一项所述的集成芯片，其特征在于，所述集成芯片包括至少两个所述第一芯片；和/或，所述集成芯片包括至少两个所述第二芯片。
  20. 如权利要求14-19任意一项所述的集成芯片，其特征在于，所述集成芯片还包括：
    设置在所述第二芯片顶部表面上的第三互连层；
    设置在所述第三互连层顶部表面上的第三芯片；
    其中，所述第三芯片包括第三部分和第四部分，所述第三部分与所述第二芯片在所述第三互连层上的投影重合，所述第四部分自所述第三部分沿着所述第三互连层突出于所述第二芯片的侧方；
    第二垂直互连结构，设置于所述第二芯片的侧方，所述第三芯片通过所述第三互连层和所述第二垂直互连结构，绕过所述第一芯片，与所述第一互连层相连。
  21. 如权利要求20所述的集成芯片，其特征在于，所述第三芯片上设置有信号传输管脚，所述第三芯片上的所有信号传输管脚均设置于所述第四部分的底部。
  22. 如权利要求20或21所述的集成芯片，其特征在于，所述第二垂直互连结构为多个焊球，或者为多个铜柱，或者为多个模封通孔TMV，或者为多个介质层通孔TDV，或者为多个绝缘层通孔TIV；
    所述第二垂直互连结构的一端通过所述第三互连层连接至所述第四部分的底部，所述第二垂直互连结构的另一端被连接至所述第一互连层中的导电层。
  23. 如权利要求21所述的集成芯片，其特征在于，所述第三芯片上还设置有供电管脚，所述第三芯片上的供电管脚中的部分或全部设置在所述第四部分的底部。
  24. 如权利要求23所述的集成芯片，其特征在于，所述第三芯片上的信号传输管脚和供电管脚构成第二管脚阵列；
    其中，所述第二管脚阵列的任意一列中所有管脚的类型相同，所述第二管脚阵列的任意相邻两列中管脚的类型不同；或者，所述第二管脚阵列中任意一行中所有管脚的类型相同，所述第二管脚阵列中任意相邻两行中管脚的类型不同。
  25. 如权利要求14-24任意一项所述的集成芯片，其特征在于，所述第一芯片为处理器芯片，所述第二芯片为存储器芯片。
  26. 一种芯片，其特征在于，所述芯片包括第一部分和第二部分，所述第一部分上设置有用于传输第一类信号的第一类管脚，所述第二部分上设置有用于传输第二类信号的第二类管脚；
    其中，所述第一类信号的传输速率大于所述第二类信号的传输速率。
  27. 如权利要求26所述的芯片，其特征在于，所述第一类信号包括差分信号、中断信号、时钟信号以及复位信号中的至少一种。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102630118A (zh) * 2011-02-07 2012-08-08 索尼公司 层叠的布线板
KR20130033808A (ko) * 2011-09-27 2013-04-04 삼성전기주식회사 반도체 패키지 및 그 제조방법
CN103311207A (zh) * 2013-05-29 2013-09-18 华为技术有限公司 堆叠式封装结构
CN105118823A (zh) * 2015-09-24 2015-12-02 中芯长电半导体（江阴）有限公司 一种堆叠型芯片封装结构及封装方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102630118A (zh) * 2011-02-07 2012-08-08 索尼公司 层叠的布线板
KR20130033808A (ko) * 2011-09-27 2013-04-04 삼성전기주식회사 반도체 패키지 및 그 제조방법
CN103311207A (zh) * 2013-05-29 2013-09-18 华为技术有限公司 堆叠式封装结构
CN105118823A (zh) * 2015-09-24 2015-12-02 中芯长电半导体（江阴）有限公司 一种堆叠型芯片封装结构及封装方法

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