TW201618281A - 半導體記憶裝置 - Google Patents

半導體記憶裝置 Download PDF

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Publication number
TW201618281A
TW201618281A TW104129669A TW104129669A TW201618281A TW 201618281 A TW201618281 A TW 201618281A TW 104129669 A TW104129669 A TW 104129669A TW 104129669 A TW104129669 A TW 104129669A TW 201618281 A TW201618281 A TW 201618281A
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Taiwan
Prior art keywords
insulating layer
input unit
memory chip
power supply
power
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TW104129669A
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English (en)
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TWI548061B (zh
Inventor
Seisei Oyamada
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Noda Screen Co Ltd
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Publication of TW201618281A publication Critical patent/TW201618281A/zh
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Publication of TWI548061B publication Critical patent/TWI548061B/zh

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Abstract

半導體記憶裝置(1)，係除中心墊區域(14)，具備設在對向於記憶體晶片(10)的電路面(11)的位置的薄膜電容(30)。薄膜電容(30)，係包含第1面電極(31)、順電體或鐵電體的薄膜介電體層(33)、及第2面電極(32)。第1面電極，係包含供應對於記憶體晶片的其中一個極性的電源電壓的第1電源輸入部(31Gin)、為了將其中一個極性的電源電壓輸出至中心墊(13)而設在中心墊區域的附近的第1電源輸出部(31Gout)。第2面電極，係形成於薄膜介電體層上，包含供應對於記憶體晶片的另一個極性的電源電壓的第2電源輸入部(32Vin)、為了將另一個極性的電源電壓施加至中心墊而設在中心墊區域的附近的第2電源輸出部(32Vout)。

Description

半導體記憶裝置
本發明，係關於半導記憶裝置，詳細而言，關於具有薄膜旁通電容的半導體記憶裝置。
歷來，在具備膜旁通電容的半導體記憶裝置方面，已知例如揭露於專利文獻1的技術。在專利文獻1，係記憶體晶片具有中心墊(center pad)，將中心墊、形成於基板的安裝面的相反側的面的基板配線，通過形成於安裝基板上的開口部而以焊線方式連接。此記憶體晶片的連接構成方面，於記憶體晶片的鄰接區域形成薄膜去耦電容(薄膜旁通電容)。如此，在專利文獻1，係揭露欲於記憶體晶片的鄰接區域形成薄膜旁通電容，從而將電極構造上的寄生電感進行最小化的技術。
[先前技術文獻] [專利文獻]
[專利文獻1]日本發明專利公開2009-55040號公報
然而，近年來，半導體記憶裝置的時鐘頻率高達400MHz以上，此外隨著資料位元寬的增加，在半導體記憶裝置方面，對於電源電壓的穩定性、多位元I/O的介面時的雜訊減低的要求已成為嚴峻者。
此外，關於具有中心墊的記憶體晶片，將中心墊與外部電路進行連接的構成方面，經由搭載基板的開口部而以焊線進行連接。並且，將非晶質系金屬氧化膜的薄膜層形成於構成封裝體的有機基板的一面的開口部周邊的旁通電容(亦即電極間的寄生電容程度)方面，係可形成於有機基板的容量密度極低，記憶體以高速進行寫入、以多位元進行讀取時，具有無法以最近距離充分供應必要的電荷如此的不妥。
所以，在本說明書，係可在具備具有中心墊的記憶體晶片的半導體記憶裝置方面，提供使在高頻介面的電源雜訊的減低效果提升，同時在記憶體晶片的搭載基板不需要外部連接用的開口部的半導體記憶裝置。
由本說明書所揭露的半導體記憶裝置，係具備具有包含形成複數個中心墊的中心墊區域的電路面、是前述電路面的相反側的面的背面的記憶體晶片，該半導體記憶裝置，具備：除前述中心墊區域，設在對向於前述電 路面的位置的薄膜電容；以及相對於前述薄膜電容，形成於前述記憶體晶片的相反側之第1絕緣層，亦即於其上形成傳送線路的第1絕緣層；前述薄膜電容，係包含：包含供應對於前述記憶體晶片的其中一個極性的電源電壓的第1電源輸入部、為了將被供應的前述其中一個極性的電源電壓輸出至前述中心墊而設於前述中心墊區域的附近的第1電源輸出部的第1面電極；形成於除前述第1電源輸入部及第1電源輸出部的前述第1面電極上的順電體或鐵電體的薄膜介電體層；以及形成於前述薄膜介電體層上的第2面電極，亦即包含供應對於前述記憶體晶片的另一個極性的電源電壓的第2電源輸入部、為了將被供應的前述另一個極性的電源電壓施加至前述中心墊而設於前述中心墊區域的附近的第2電源輸出部的第2面電極；前述傳送路，係包含供應對於前述記憶體晶片的信號的信號輸入部、為了將被供應的前述信號供應至前述中心墊而設於前述中心墊區域的附近的信號輸出部。
依本構成時，薄膜電容，係除中心墊區域，設在對向於記憶體晶片的電路面的位置。此外，於薄膜電容的第1面電極及第2面電極，係設置供於將電源電壓施加至中心墊用的電源輸出部，另外於傳送線路，係設置供於將位址信號等的信號施加至中心墊用的信號輸出部。
為此，在具備具有中心墊的記憶體晶片的半導體記憶裝置方面，能提供以最接近中心墊的距離，形成採用順電體或高介電體的容量密度高的絕緣層並提供對於電源系統 以數GHz以上的高頻區域供予充分的電荷的環境，降低高頻下的電源阻抗，使電源雜訊的減低效果提升，同時在搭載記憶體晶片的基板不需要外部連接用的開口部的半導體記憶裝置。
在上述半導體記憶裝置方面，亦可作成具備：以面朝上搭載前述記憶體晶片的基板；以及形成於前述記憶體晶片的前述電路面上的第2絕緣層；前述薄膜電容的前述第1面電極係形成於前述第2絕緣層上，前述第1絕緣層係形成於除前述第2電源輸入部及第2電源輸出部的前述第2面電極上，前述基板係包含與前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部連接的複數個連接墊，前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部、前述複數個連接墊係藉焊線方式而連接，前述第1電源輸出部、前述第2電源輸出部、及前述信號輸出部、前述複數個中心墊係藉焊線方式而連接。
依本構成時，可藉周知的焊線方式，將薄膜電容及傳送線路與基板，此外將薄膜電容及傳送線路與記憶體晶片的中心墊進行連接。此情況下，於搭載記憶體晶片的基板係不需要外部連接用的開口部。
此外，在上述半導體記憶裝置方面，亦可作成具備形成於前述記憶體晶片的前述電路面上的第2絕緣層，前述薄膜電容的前述第1面電極係形成於前述第2絕緣層上，前述第1絕緣層係形成於除前述第2電源輸入部 及第2電源輸出部的前述第2面電極上，於前述第1電源輸入部及前述第2電源輸入部係形成第1連接凸塊，於前述信號輸入部係形成高度比前述第1連接凸塊低前述第1絕緣層的厚度份的第2連接凸塊，前述第1電源輸出部、前述第2電源輸出部、及前述信號輸出部、前述複數個中心墊係藉焊線方式而連接。
依本構成時，可使在高頻介面的電源雜訊的減低效果提升，同時將在搭載記憶體晶片的基板不需要外部連接用的開口部的半導體記憶裝置構成為具有BGA(Ball Grid Array)的CSP(Chip Scale Package)。
此外，在上述半導體記憶裝置方面，亦可作成具備：以面朝上載置前述記憶體晶片的金屬板；配置前述金屬板的基板；形成於前述記憶體晶片的前述電路面上的第2絕緣層；以及形成於前述第1絕緣層上的保護層；前述薄膜電容的前述第1面電極係形成於前述第2絕緣層上，前述第1絕緣層係形成於除前述第2電源輸入部及第2電源輸出部的前述第2面電極上，前述基板係包含與前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部連接的複數個連接墊，前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部、前述複數個連接墊係藉焊線方式而連接，前述第1電源輸出部、前述第2電源輸出部、及前述信號輸出部、前述複數個中心墊係藉焊線方式而連接，前述基板、前述記憶體晶片、前述第2絕緣層、前述薄膜電容、前述第1絕緣層、及前述保護層，係 形成依此順序而積層的記憶單元，該半導體記憶裝置係具備被積層的至少二階的前述記憶單元，於最上階的記憶單元的保護層之上，配置與各金屬板熱性連接的散熱構材。
依本構成時，在重疊複數個包含記憶體晶片的記憶單元而構成的半導體記憶裝置方面，可提供使在高頻介面的電源雜訊的減低效果提升，同時在搭載記憶體晶片的基板不需要外部連接用的開口部的半導體記憶裝置以外，可進一步將由於各記憶體晶片而產生的熱適當地散熱。藉此可使半導體記憶裝置的動作的可靠性提升。
此情況下，亦可作成前述金屬板係俯視下，具備於沿著前述焊線的電線的鋪設方向的方向上具有比前述記憶體晶片的長度短的長度，於與前述電線的鋪設方向正交的方向上，具有比前述記憶體晶片的長度長的長度的矩形的形狀，配置於最下階的基板的金屬板，係具有配置於其長邊方向的端部，與配置於比最下階還上階的基板的金屬板、前述散熱構材熱性連接的熱傳達部。
依本構成時，可將來自各階的記憶單元的發熱，經由熱傳達部傳達至散熱構材，從散熱構材放掉。
再者該情況下，亦可作成於前述基板係形成供於配置前述金屬板用的開口或薄部。
依本構成時，可將金屬板簡易地配置於基板。
此外，在上述半導體記憶裝置方面，亦可作成具備：以面朝下的態樣搭載前述記憶體晶片的基板；形成於前述傳送路上的保護層；以及設於前述記憶體晶片的 前述電路面上的第2絕緣層；前述薄膜電容的前述第1面電極係形成於前述第2絕緣層上，前述第1絕緣層係於中心墊側使第1電源輸出部及第2電源輸出部曝露而形成於前述薄膜電容上，在中心墊側的相反側以前述信號輸入部於前述保護層上曝露的方式而回蝕，前述第2絕緣層係在中心墊側的相反側以前述第1電源輸入部及前述第2電源輸入部在前述第1絕緣層上曝露的方式而回蝕，前述保護層係形成為於中心墊側在前述第2絕緣層上使前述信號輸出部曝露，在中心墊側的相反側使前述信號輸入部在其上曝露，前述第1電源輸出部、前述第2電源輸出部、及前述信號輸出部、前述複數個中心墊係藉焊線方式而連接，形成於前述記憶體晶片的前述電路面上的前述第2絕緣層、前述薄膜電容、前述第1絕緣層、前述傳送路、及前述保護層，係以前述記憶體晶片成為最上階且前述保護層成為最下階的方式將上下反轉而搭載於前述基板上，前述基板係包含與前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部連接的複數個連接墊，前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部、前述複數個連接墊係藉焊線方式而連接。
依本構成時，在記憶體晶片被以面朝下的態樣而搭載於基板的構成的半導體記憶裝置方面，可提供使在高頻介面的電源雜訊的減低效果提升，同時在基板不需要外部連接用的開口部的半導體記憶裝置。此外，在此構成下，係可使記憶體晶片的背面曝露，故可於記憶體晶片的背面， 設置散熱器等的散熱構材。
此外，在上述半導體記憶裝置方面，亦可作成具備：基板；形成於前述基板上的前述第1絕緣層；形成於前述第1絕緣層上的第2絕緣層；以及形成於前述薄膜電容上的保護膜；前述記憶體晶片係以面朝下搭載於前述保護膜上，前述第2絕緣層係形成於除前述傳送路的前述信號輸入部的前述第1絕緣層上，前述薄膜電容的前述第1面電極係形成於前述第2絕緣層上，前述第1電源輸出部係包含形成於第2絕緣層上的第1電源輸出配線，前述第2電源輸出部係包含形成於第2絕緣層上的第2電源輸出配線，前述傳送路的信號輸出部係包含形成於前述第2絕緣層內的導孔、與前述導孔連接並形成於第2絕緣層上的信號輸出配線，前述基板係包含與前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部連接的複數個連接墊，前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部、前述複數個連接墊係藉焊線方式而連接，前述第1電源輸出配線、前述第2電源輸出配線、及前述信號輸出配線、前述複數個中心墊係藉凸塊而連接。
依本構成時，在記憶體晶片被以面朝下的態樣而搭載於基板的構成的半導體記憶裝置方面，可提供使電源雜訊的減低效果提升，同時在搭載記憶體晶片的基板不需要外部連接用的開口部的半導體記憶裝置。在此構成下，係可使記憶體晶片的背面曝露，故可於記憶體晶片的背面，設置散熱器等的散熱構材。
此情況下，亦可作成具備配置於前述記憶體晶片的前述背面上的散熱構材， 依本構成時，可藉散熱構材抑制記憶體晶片的發熱，藉此可使半導體記憶裝置的動作的可靠性提升。
此外，在上述半導體記憶裝置方面，亦可作成具備形成於前述中心墊區域的兩側的至少一對的前述薄膜電容。
依本構成時，可於由於中心墊區域使得記憶體區域被分離的構造的半導體記憶裝置，對應於各記憶體區域而設置薄膜電容。
此外，在上述半導體記憶裝置方面，亦可作成前述第2面電極係俯視下，於對應於前述第1面電極的區域內分割成複數個。
依本構成時，可相對於1個共通的第1面電極構成複數個的薄膜電容。藉此，亦可應對具備複數個不同電源電壓的記憶體晶片。
依本發明的半導體記憶裝置時，可在具備具有中心墊的記憶體晶片的半導體記憶裝置方面，提供使在高頻介面的電源雜訊的減低效果提升，同時在記憶體晶片的搭載基板不需要外部連接用的開口部的半導體記憶裝置。
1‧‧‧半導體記憶裝置
10‧‧‧記憶體晶片
11‧‧‧電路面
13‧‧‧中心墊
14‧‧‧中心墊區域
20‧‧‧中間基板
21‧‧‧第1絕緣層
22‧‧‧第2絕緣層
23‧‧‧傳送線路
24、25‧‧‧Au線
26‧‧‧焊料凸塊
27‧‧‧保護層
30‧‧‧薄膜電容
31‧‧‧第1面電極
31Gin‧‧‧第1電源輸入部
31Gout‧‧‧第1電源輸出部
32‧‧‧第2面電極
32Vin‧‧‧第2電源輸入部
32Vout‧‧‧第2電源輸出部
33‧‧‧薄膜介電體層
40‧‧‧中間基板
45‧‧‧散熱器
46‧‧‧散熱金屬板
47‧‧‧熱傳達部
48‧‧‧薄部
[圖1]實施形態1的半導體記憶裝置的示意性的剖面圖
[圖2]實施形態1的半導體記憶裝置的示意性的部分平面圖
[圖3]示出薄膜電容的構成的示意性的剖面圖
[圖4]示出基板側相關之連接的示意性的部分放大圖
[圖5]示出中心墊側相關之連接的示意性的部分放大圖
[圖6]示出薄膜電容的別的構成例的示意性的平面圖
[圖7]示出薄膜電容的別的構成例的示意性的平面圖
[圖8]實施形態2的半導體記憶裝置的示意性的剖面圖
[圖9]實施形態2的半導體記憶裝置的示意性的部分平面圖
[圖10]實施形態3的半導體記憶裝置的示意性的剖面圖
[圖11]實施形態3的半導體記憶裝置的別的示意性的剖面圖
[圖12]實施形態3的半導體記憶裝置的示意性的部分平面圖
[圖13]實施形態4的半導體記憶裝置的示意性的剖面圖
[圖14]針對實施形態4的基板側相關之連接進行繪示的示意性的部分放大圖
[圖15]說明在實施形態4的回蝕的部分剖面圖
[圖16]說明在實施形態4的回蝕的部分剖面圖
[圖17]實施形態5的半導體記憶裝置的示意性的剖面圖
[圖18]實施形態5的半導體記憶裝置的示意性的平面圖
[圖19]針對實施形態5的基板側相關之連接進行繪示的示意性的部分放大圖
<實施形態1>
針對本發明相關之實施形態1，參照圖1至圖7進行說明。
1.半導體記憶裝置的構成
本實施形態1的半導體記憶裝置1，係如示於圖1，主要具備記憶體晶片10、薄膜電容30、及中間基板(「基板」的一例)40。
記憶體晶片10，係具有包含形成複數個中心墊13的中心墊區域14的電路面11(圖2參照)、是電路面11的相反側的面的背面12。記憶體晶片10，係如示於圖1 ，在中間基板40上，以與中間基板40相反側而面朝上而搭載電路面11。記憶體晶片10，係例如DDR3-SDRAM。另外，記憶體晶片10，係不限於DDR3-SDRAM，具有包含中心墊區域14的電路面11的記憶體晶片即可。
薄膜電容30，係如示於圖2等，除中心墊區域14，設在對向於記憶體晶片10的電路面11的位置。在實施形態1，如示於圖2，薄膜電容30係在中心墊區域14的兩側形成一對。為此，可於由於中心墊區域14使得記憶體區域被分離的構造的半導體記憶裝置，對應於各記憶體區域而設置薄膜電容30。
各薄膜電容30，係形成於從設於中心墊區域14的中心墊13分離例如100μm(微米)程度的位置。薄膜電容30，係如示於圖3，包含第1面電極31、薄膜介電體層33、及第2面電極32。
第1面電極31，係包含提供對於記憶體晶片10的接地電壓(零電位)Gnd的第1電源輸入部31Gin、供於將接地電壓Gnd施加於中心墊13G用的第1電源輸出部31Gout。第1面電極31，係例如，藉濺鍍而形成，由具有2μm以上的膜厚的銅薄膜而構成。
薄膜介電體層33，係由例如具有1μm以下的膜厚的順電體(例如，SrTiO)或鐵電體(例如，BST)而構成。
第2面電極32，係形成於薄膜介電體層33上，如同第1面電極31，例如，藉濺鍍而形成，由具有 2μm以上的膜厚的銅薄膜而構成。第2面電極32，係包含被供應對於記憶體晶片10的既定的正電壓Vdd的第2電源輸入部32Vin、供於將既定的正電壓Vdd施加於中心墊13V用的第2電源輸出部32Vout。
於此，接地電壓Gnd係相當於施加於記憶體晶片10的其中一個極性的電源電壓，正電壓係相當於施加於記憶體晶片10的另一個極性的電源電壓。另外，不限於此，亦可為其相反。亦即，使其中一個極性的電源電壓為正電壓Vdd，使另一個極性的電源電壓為接地電壓Gnd亦可。另外，在本實施形態，係對於正電壓Vdd相關之構材的符號附上「V」的文字，對於接地電壓Gnd相關之構材的符號附上「G」的文字。此外，對於電源以外的信號相關之構材附上「S」的文字。此外，無須特別區別的情況下，對於符號不附上「V」、「G」及「S」。
中間基板40，係具有記憶體晶片10被面朝上而搭載的搭載面41、是搭載面41的相反側的面的外部連接面42。於搭載面41，係形成與記憶體晶片10連接的複數個連接墊43(圖4參照)、及配線(未圖示)。於外部連接面42，係設有供於將半導體記憶裝置1連接於主機板等用的複數個焊球44、及配線(未圖示)。亦即，於外部連接面42，係設有BGA。此外，於中間基板40的內部，係設有將搭載面41與外部連接面42連接的導孔等(未圖示)。於此，中間基板40，係例如有機基板。另外，於外部連接面42，係不限於BGA，設置LGA亦可。
再者，半導體記憶裝置1，係具備第1絕緣層21與第2絕緣層22。第1絕緣層21，係如示於圖1，相對於薄膜電容30形成在記憶體晶片10的相反側。詳細而言，如示於圖3，第1絕緣層21，係形成於第2電源輸入部32Vin及第2電源輸出部32Vout以外的第2面電極32上。於第1絕緣層21上，係形成傳送線路23。第1絕緣層21，係由供於將傳送線路23平行保持而黏合用的BT樹脂等的熱硬化樹脂所成。第1絕緣層21的層厚，係50μm以上為優選。
傳送線路23，係包含被供應對於記憶體晶片10的信號的信號輸入部23Sin、供於將信號供應至中心墊13G用的信號輸出部23Sout。於此，存在於第1絕緣層21上的傳送線路23，係成為對應於記憶體晶片10具有的全部的墊的信號之中，電源系統(Vdd及Gnd)以外的全部的信號的傳送線路。傳送線路23的特性阻抗，係設定成記憶體晶片10建議之值。
傳送線路23的特性阻抗，係取決於第1絕緣層21的材料具有的相對電容率、傳送線路23的寬、及傳送線路23與薄膜電容30的第2面電極32的距離(第1絕緣層21的層厚)等。例如，第1絕緣層21為相對電容率εo=4.4的BT樹脂，傳送線路23的寬度為25μm，其厚度為10μm，在特性阻抗方面建議100Ω的情況下，第1絕緣層(BT樹脂)21的層厚係約120μm，傳送線路23的配線間距係約100μm為優選。
此外，第2絕緣層22係形成於記憶體晶片10的電路面11上，於第2絕緣層22上，形成薄膜電容30的第1面電極31。第2絕緣層22，係如同第1絕緣層21，由BT樹脂等的熱硬化樹脂所成。此外，第2絕緣層22的層厚，係50μm以上為優選。
如示於圖4，第1電源輸入部31Gin、第2電源輸入部32Vin、及信號輸入部23Sin、複數個連接墊43，係藉依電線24的焊線方式而連接。此外，如示於圖5，第1電源輸出部31Gout、前述第2電源輸出部32Vout、及信號輸出部23Sout、複數個中心墊13，係同樣藉依電線25的焊線方式而連接。
電線25，係Au(金)線、Al(鋁)線、Cu(銅)線等。焊線方面，進行使用焊線機的超音波接合。在本實施形態，電線25係Au線。
另外，一般而言，記憶體晶片10係接地GND共通，具有不同電源(正電壓)Vdd系統(內部電路用、DQ(資料)用等)。為此，亦可作成將薄膜電容30的第1面電極31當作接地電壓Gnd用的情況下，為了將對應於其的正電壓(Vdd1、Vdd2等)分離，如示於圖6，依正電壓將第2面電極32及薄膜介電體層33分離。於圖6，係示出分離成3個薄膜電容30的薄膜電容群30G。此情況下，可相對於1個共通的第1面電極31構成複數個的薄膜電容。藉此，亦可應對具備複數個不同電源電壓的記憶體晶片。
再者，記憶體晶片10方面存在複數個接地GND的情況下，如示於圖7，亦可將第1面電極31分割而構成。亦即，於圖7，係示出具備4個示於圖6的薄膜電容群30G，第1面電極31分割成4個的薄膜電容的構成例。
2.半導體記憶裝置的作成方法的概要
如示於圖3，於第2絕緣層22上形成薄膜電容30的第1面電極31，於第1面電極31上形成薄膜介電體層33，於薄膜介電體層33上形成第2面電極32。接著，於第2面電極32上形成第1絕緣層21，於第1絕緣層21上形成傳送線路23。
接著，將示於圖3的中間生成物，配置於記憶體晶片10的電路面11的中心墊區域14的兩側。接著，藉周知的方法，將記憶體晶片10以面朝上晶粒接合於形成有焊球44等的中間基板40上。
接著，將第1電源輸入部31Gin、第2電源輸入部32Vin、及信號輸入部23Sin、複數個連接墊43，藉依Au線24的焊線方式而連接。此外，將第1電源輸出部31Gout、第2電源輸出部32Vout、及信號輸出部23Sout、複數個中心墊13，藉依Au線25的焊線方式而連接。
並且，運用周知的模具技術，而將記憶體晶片10等藉模具樹脂(未圖示)模製成既定的大小，從而 完成如示於圖1的半導體記憶裝置1。
3.實施形態1的效果
在實施形態1，薄膜電容30，係除中心墊區域14，設在對向於記憶體晶片10的電路面11的位置。在實施形態1，係在形成於記憶體晶片10的電路面11上的第2絕緣層22上形成薄膜電容30，藉此可將薄膜電容30與中間基板40及記憶體晶片10的中心墊13的連接距離最短化。亦即，可最短化Au線24、25的長度。為此，在具備具有中心墊13的記憶體晶片10的半導體記憶裝置1方面，可藉薄膜電容30等使電源雜訊的減低效果提升。
換言之，能以最接近中心墊13的距離，形成採用順電體或高介電體下的容量密度高的薄膜介電體層33，提供可對於電源系統以數GHz以上的高頻區域供予充分的電荷的環境，降低高頻下的電源阻抗。藉此，可使在高頻介面的電源雜訊的減低效果提升，同時可提供在記憶體晶片的搭載基板不需要外部連接用的開口部的半導體記憶裝置1。
此外，於薄膜電容30的第1面電極31及第2面電極32，係設置供於將電源電壓(Gnd、Vdd)施加至中心墊13用的電源輸出部(31Gout、32Vout)。另外於傳送線路23，係設置供於將位址信號等的信號施加至中心墊13用的信號輸出部23Sout。藉此構成，可不須在搭載記憶體晶片10的中間基板40形成外部連接用的開口 部，將薄膜電容30、中間基板40及記憶體晶片10的中心墊13，藉焊線方式而連接。
<實施形態2>
接著，參照圖8、圖9，而說明實施形態2。另外，對於與實施形態1相同的構材，係附上相同的符號而省略其說明。為此，僅說明與實施形態1的差異。
實施形態2的半導體記憶裝置1A，係如示於圖8，實施形態1的半導體記憶裝置1，係主要不具有中間基板40之點不同。亦即，實施形態2的半導體記憶裝置1A，係形成為CSP。
為此，薄膜電容30及傳送線路23與外部的連接係藉焊球26而進行，薄膜電容30及傳送線路23與中心墊13的連接係藉依Au線25的焊線方式而進行。
詳細而言，如示於圖9，於第1面電極31，係薄膜介電體層33及第2面電極32未重疊的區域被設於4方向，在除與中心墊13的連接部分外的3方向，設置可搭載焊球26G的區域。同樣，於第2面電極32，亦於3方向，設置可搭載焊球26V的區域。
此外，於第1面電極31的第1電源輸入部31Gin係形成焊球(「第1連接凸塊」的一例)26G，於第2面電極32的第2電源輸入部32Vin係形成焊球(「第1連接凸塊」的一例)26V。焊球26G與焊球26V的高度(直徑)，係存在將薄膜介電體層33與第2面電 極32的膜厚進行加算的值(3μm程度)的差，惟幾乎相等。
此外，於傳送線路23的信號輸入部23Sin，係形成高度(直徑)比焊球26G、26V低第1絕緣層21的厚度程度(50μm程度)的焊球26S(「第2連接凸塊」的一例)。
於此，焊球26G、26V的直徑係200μm程度，焊球26S的直徑係150μm程度。此外，第1電源輸入部31Gin及第2電源輸入部32Vin係直徑從150μm至200μm的被鍍金的焊墊，信號輸入部23Sin係直徑從100μm至150μm的被鍍金的焊墊。另外，第2連接凸塊係不限於焊球26S，亦可為例如金柱狀凸塊。
如此，在實施形態2，係可將藉薄膜電容30等使在高頻介面的電源雜訊的減低效果提升，同時在搭載記憶體晶片10的中間基板40不需要外部連接用的開口部的半導體記憶裝置1A，構成為CSP。
<實施形態3>
接著，參照圖10至圖12，而說明實施形態3。另外，對於與實施形態1相同的構材，係附上相同的符號而省略其說明。為此，僅說明與實施形態1的差異。
在實施形態3，係如示於圖10，由中間基板40、記憶體晶片10、第2絕緣層22、薄膜電容30、第1絕緣層21、及保護層27，形成依此順序而積層的記憶單 元50。並且，半導體記憶裝置1B，係具備被積層的至少2級(實施形態3係2級)的記憶單元50A、50B。
各中間基板40，係包含以面朝上搭載記憶體晶片10的散熱金屬板(「金屬板」的一例)46。此外，於各中間基板40，係形成供於配置散熱金屬板46用的薄部48。可藉薄部48簡易地將散熱金屬板46配置於基板。另外，將散熱金屬板46配置於中間基板40的方法，係不限於藉薄部48的方法。亦可作成例如將開口設於中間基板40而配置散熱金屬板46。
散熱金屬板46，係如示於圖12，俯視下，具備於沿著焊線的電線24、25的鋪設方向的方向(圖12的箭頭X方向)，具有比記憶體晶片10的長度短的長度，於與電線的鋪設方向正交的方向(箭頭Y方向)，具有比記憶體晶片10的長度長的長度的矩形的形狀。散熱金屬板46，係例如1mm×2mm的平面形狀，厚度係具有2-3mm的厚度的銅板。
此外，如示於圖10，於最上階的記憶單元50B的保護層27上，配置與各散熱金屬板46、46A熱性連接的散熱器(「散熱構材」的一例)45。另外，於圖12，係示出除散熱器45外的平面圖。
此外，如示於圖11，配置於最下階的中間基板40的散熱金屬板46A，係具有配置於其長邊方向(圖12的箭頭Y方向)的端部，與配置於比最下階還上階的中間基板40的散熱金屬板46、散熱器45熱性連接的熱 傳達部47。在本實施形態下熱傳達部47，係與散熱金屬板46A一體形成。另外，不限於此，熱傳達部47，係亦可與散熱金屬板46A個別地形成。
藉此熱傳達部47，使得各散熱金屬板46、46A的熱被傳達至散熱器45。亦即，可將來自各階的記憶單元50的發熱，經由熱傳達部47傳達至散熱器45，從散熱器45放掉。另外，散熱金屬板46與熱傳達部47，係為了獲得適合的熱導，而藉Ag(銀)膏體或矽脂等而黏合。
如此，在實施形態3，係在將包含記憶體晶片10的記憶單元50重疊複數階(此處係2級)而構成的半導體記憶裝置1B方面，可提供藉薄膜電容30等使電源雜訊的減低效果提升，同時在搭載記憶體晶片10的中間基板40不需要外部連接用的開口部的半導體記憶裝置。再者，可將由於記憶單元50的各記憶體晶片10而產生的適當散熱。藉此可使半導體記憶裝置1B的動作的可靠性提升。
<實施形態4>
接著，參照圖13至圖16，而說明實施形態4。另外，對於與實施形態1相同的構材，係附上相同的符號而省略其說明。為此，僅說明與實施形態1的差異。
在實施形態4的半導體記憶裝置1C，係與實施形態1至3不同，記憶體晶片10被以面朝下的態樣而 搭載於中間基板40。亦即，在半導體記憶裝置1C，係如示於圖13，設於記憶體晶片10的電路面11上的第2絕緣層22、薄膜電容30、第1絕緣層21、傳送線路23、及保護層27，係以記憶體晶片10成為最上階且保護層27成為最下階的方式將上下反轉而搭載於中間基板40上。
為此，關於薄膜電容30及傳送線路23與記憶體晶片10的連接，藉焊線方式而連接之點儘管與實施形態1相等，惟各輸入部的配置處與實施形態1不同。
亦即，如示於圖14，第1電源輸入部31Gin及第2電源輸入部32Vin，係配置於第1絕緣層21上，信號輸入部23Sin，係配置於保護層27上。並且，第1電源輸入部31Gin、第2電源輸入部32Vin、及信號輸入部23Sin、中間基板40上的複數個連接墊43，係如同實施形態1，藉依電線24的焊線方式而連接。
針對構成如示於圖14的各輸入部的配置處的例子，參照圖15及圖16進行說明。首先，使用例如金屬基材等，而形成依包含以雙點劃線而示的被回蝕的部分(圖15參照)的第2絕緣層22、薄膜電容30、第1絕緣層21、傳送線路23、及保護層27的順序而積層的多層薄膜體。
並且，如示於圖15，將多層薄膜體上下反轉的狀態下，對於第2絕緣層22將碳酸氣體(CO2)雷射光L1照射於形成第1電源輸出部31Gout等的端部的相反側的端部，而將以雙點劃線而示的第2絕緣層22的端部 進行回蝕而除去。
此情況下，使用僅分解是有機材的第2絕緣層22，並將是銅等的金屬製的薄膜電容30的第1面電極31反射的波長長的碳酸氣體雷射光L1。藉此，可於第1絕緣層21上使第1面電極31曝露。
接著，如示於圖16，對於曝露的第1面電極31，除成為第1電源輸入部31Gin的部分，將波長短的紫外線(UV)雷射光L2既定時間進行照射而蝕刻第1面電極31，使由SrTiO等的順電體等所成之薄膜介電體層33曝露。再者，對於被曝露的薄膜介電體層33，除第1面電極31的附近，將紫外線雷射光L2既定時間進行照射而蝕刻薄膜介電體層33，使第2面電極32曝露。接著，對於曝露的第2面電極32，除成為第2電源輸入部32Vin的部分，進一步將紫外線雷射光L2既定時間進行照射而將第2面電極32蝕刻除去。藉此第1絕緣層21的端部曝露。
接著，對於是有機材的被曝露的第1絕緣層21的端部，照射碳酸氣體雷射光L1而第1絕緣層21的端部進行回蝕而除去。藉此，在保護層27上成為傳送線路23的信號輸入部23Sin的部分曝露於保護層27上。如此進行針對輸入部的回蝕處理的多層薄膜體，係黏貼於記憶體晶片10的電路面11上。並且，進行多層薄膜體與記憶體晶片10的焊線處理，在使記憶體晶片10為面朝下的狀態下，進行多層薄膜體與中間基板40的焊線處理。
此情況下，薄膜電容30與記憶體晶片10的連接方法及各輸出部的配置，係皆與實施形態1相等。亦即，第1電源輸出部31Gout、第2電源輸出部32Vout、及信號輸出部23Sout、複數個中心墊13，係依與示於圖5的實施形態1同樣的態樣，藉依Au線25的焊線方式而連接。
亦即，在實施形態4，第1絕緣層21係於中心墊側，使第1電源輸出部31Gout及第2電源輸出部32Vout曝露而形成於薄膜電容30上，在中心墊側的相反側亦即中間基板40側，係以信號輸入部23Sin在保護層27上曝露的方式而回蝕。
此外，第2絕緣層22，係在中心墊側的相反側亦即中間基板40側，以第1電源輸入部31Gin及第2電源輸入部32Vin在第1絕緣層21上曝露的方式而回蝕。
此外，保護層27係形成為：於中心墊側，在第2絕緣層22上使信號輸出部23Sout曝露，在中心墊側的相反側使信號輸入部23Sin於其上曝露。藉此構成，在記憶體晶片10被以面朝下的態樣而搭載於中間基板40的構成中，於多層薄膜體的中心墊側及中間基板40側，藉焊線方式的連接成為可能。
此外，如此，記憶體晶片10在最上階以面朝下的態樣搭載於中間基板40的構成中，係記憶體晶片10的背面12曝露，故如示於圖13，可將散熱器45配置於 記憶體晶片10的背面12上。
在實施形態4，係在記憶體晶片10被以面朝下的態樣而搭載於中間基板40的構成的半導體記憶裝置1C方面，可提供藉薄膜電容30等使在高頻介面的電源雜訊的減低效果提升，同時在中間基板40不需要外部連接用的開口部的半導體記憶裝置。此外，在此構成下，係可使記憶體晶片10的背面12曝露，故可於記憶體晶片的背面12，設置散熱器45等的散熱構材。
亦即，在高速存取的記憶體介面，係如何使在記憶體晶片的接面產生的發熱以低的熱阻從而予以連接於散熱器、散熱片而予以散熱成為重要的課題。為此，在實施形態4，係藉使在高頻介面的電源雜訊的減低效果提升，同時將散熱器45配置於記憶體晶片10的背面12上的構成，而可簡易地解決該課題。另外，回蝕的方法係不限於使用雷射光者。例如，可為一般的使用抗蝕層的藉蝕刻溶液的方法、或使用氣體的方法。
<實施形態5>
接著，參照圖17至圖19，而說明實施形態5。在實施形態5的半導體記憶裝置1D，係如同實施形態4，記憶體晶片10被以面朝下的態樣而搭載於中間基板40。另外，對於與實施形態1相同的構材，係附上相同的符號而省略其說明。為此，僅說明與實施形態1的差異。
實施形態5與實施形態4，係第1電源輸出部 31Gout、第2電源輸出部32Vout、及信號輸出部23Sout、複數個中心墊13藉形成於中心墊13的凸塊15而連接之點不同。
亦即，如示於圖18，第1電源輸出部31Gout，係包含形成於第2絕緣層22上的第1電源輸出配線31W。第2電源輸出部32Vout，係包含形成於第2絕緣層22上的第2電源輸出配線32W。此外，傳送線路23的信號輸出部23Sout，係包含形成於第2絕緣層22內的導孔22H、與導孔22H連接並形成於第2絕緣層22上的信號輸出配線23W。
於各輸出配線23W、31W、32W上，係形成與形成於記憶體晶片10的中心墊13上的凸塊15連接的焊墊23L、31L、32L。凸塊15，係例如Au柱狀凸塊(stud bump)或微焊料凸塊。
此外，如示於圖17，第1絕緣層21，係與實施形態1不同，形成於中間基板40上，第2絕緣層22，係形成於第1絕緣層21上。此外，薄膜電容30係形成於第2絕緣層22上，於薄膜電容30上形成保護層27。並且，記憶體晶片10，係以面朝下而搭載於保護層27上。
另外，如示於圖17及圖19，第1電源輸入部31Gin、第2電源輸入部32Vin、及信號輸入部23Sin、複數個連接墊43，係如同實施形態1，藉依Au線24的焊線方式而連接。
如此，在實施形態5，係如同實施形態4，在 記憶體晶片10被以面朝下的態樣而搭載於基板的構成的半導體記憶裝置方面，可提供藉薄膜電容30等使電源雜訊的減低效果提升，同時在搭載記憶體晶片10的中間基板40不需要外部連接用的開口部的半導體記憶裝置1D。在此構成下，係可使記憶體晶片的背面曝露，故可於記憶體晶片的背面，設置散熱器等的散熱構材。
<其他實施形態>
本發明係非限定於藉上述記述及圖式而說明的實施形態者，例如以下的各種的態樣亦含於本發明的技術範圍。
(1)於實施形態1，係雖示出薄膜電容30對向於中心墊區域14的兩側而形成1對之例，惟不限於此。例如，薄膜電容30，係可僅對向於中心墊區域14的其中一側而形成。或者，亦可對向於中心墊區域14的兩側而形成2對。此外，薄膜電容群30G的形成態樣(分割態樣)，係非限於示於圖6及圖7者，依薄膜電容的必要形態，而酌情分割即可。
(2)於實施形態4，亦可省略散熱器45。反之，在實施形態5，在記憶體晶片10的背面12上設置散熱器45等的散熱構材亦可。
1‧‧‧半導體記憶裝置
10‧‧‧記憶體晶片
11‧‧‧電路面
13‧‧‧中心墊
14‧‧‧中心墊區域
21‧‧‧第1絕緣層
22‧‧‧第2絕緣層
23‧‧‧傳送線路
24、25‧‧‧Au線
30‧‧‧薄膜電容
31‧‧‧第1面電極
31Gin‧‧‧第1電源輸入部
31Gout‧‧‧第1電源輸出部
32‧‧‧第2面電極
32Vin‧‧‧第2電源輸入部
32Vout‧‧‧第2電源輸出部
33‧‧‧薄膜介電體層
40‧‧‧中間基板
41‧‧‧搭載面
42‧‧‧外部連接面
43‧‧‧連接墊
44‧‧‧焊球

Claims (11)

  1. 一種半導體記憶裝置，具備具有包含形成複數個中心墊的中心墊區域的電路面、是前述電路面的相反側的面的背面的記憶體晶片，該半導體記憶裝置具備：除前述中心墊區域，設在對向於前述電路面的位置的薄膜電容；以及相對於前述薄膜電容，形成於前述記憶體晶片的相反側之第1絕緣層，亦即於其上形成傳送線路的第1絕緣層；前述薄膜電容，係包含：包含供應對於前述記憶體晶片的其中一個極性的電源電壓的第1電源輸入部、為了將被供應的前述其中一個極性的電源電壓輸出至前述中心墊而設於前述中心墊區域的附近的第1電源輸出部的第1面電極；形成於除前述第1電源輸入部及第1電源輸出部的前述第1面電極上的順電體或鐵電體的薄膜介電體層；以及形成於前述薄膜介電體層上的第2面電極，亦即包含供應對於前述記憶體晶片的另一個極性的電源電壓的第2電源輸入部、為了將被供應的前述另一個極性的電源電壓施加至前述中心墊而設於前述中心墊區域的附近的第2電源輸出部的第2面電極；前述傳送路，係包含供應對於前述記憶體晶片的信號的信號輸入部、為了將被供應的前述信號供應至前述中心 墊而設於前述中心墊區域的附近的信號輸出部。
  2. 如申請專利範圍第1項的半導體記憶裝置，其具備：以面朝上搭載前述記憶體晶片的基板；以及形成於前述記憶體晶片的前述電路面上的第2絕緣層；前述薄膜電容的前述第1面電極，係形成於前述第2絕緣層上，前述第1絕緣層，係形成於除前述第2電源輸入部及第2電源輸出部的前述第2面電極上，前述基板，係包含與前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部連接的複數個連接墊，前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部、前述複數個連接墊係藉焊線方式而連接，前述第1電源輸出部、前述第2電源輸出部、及前述信號輸出部、前述複數個中心墊係藉焊線方式而連接。
  3. 如申請專利範圍第1項的半導體記憶裝置，其具備形成於前述記憶體晶片的前述電路面上的第2絕緣層，前述薄膜電容的前述第1面電極，係形成於前述第2絕緣層上，前述第1絕緣層，係形成於除前述第2電源輸入部及第2電源輸出部的前述第2面電極上，於前述第1電源輸入部及前述第2電源輸入部，係形成第1連接凸塊， 於前述信號輸入部，係形成高度比前述第1連接凸塊低前述第1絕緣層的厚度份的第2連接凸塊，前述第1電源輸出部、前述第2電源輸出部、及前述信號輸出部、前述複數個中心墊係藉焊線方式而連接。
  4. 如申請專利範圍第1項的半導體記憶裝置，其具備：以面朝上載置前述記憶體晶片的金屬板；配置前述金屬板的基板；形成於前述記憶體晶片的前述電路面上的第2絕緣層；以及形成於前述第1絕緣層上的保護層；前述薄膜電容的前述第1面電極，係形成於前述第2絕緣層上，前述第1絕緣層，係形成於除前述第2電源輸入部及第2電源輸出部的前述第2面電極上，前述基板，係包含與前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部連接的複數個連接墊，前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部、前述複數個連接墊係藉焊線方式而連接，前述第1電源輸出部、前述第2電源輸出部、及前述信號輸出部、前述複數個中心墊係藉焊線方式而連接，前述基板、前述記憶體晶片、前述第2絕緣層、前述薄膜電容、前述第1絕緣層、及前述保護層，係形成依此順序而積層的記憶單元， 該半導體記憶裝置，係具備被積層的至少二階的前述記憶單元，於最上階的記憶單元的保護層之上，配置與各金屬板熱性連接的散熱構材。
  5. 如申請專利範圍第4項的半導體記憶裝置，其中，前述金屬板，係俯視下，具備於沿著前述焊線的電線的鋪設方向的方向上具有比前述記憶體晶片的長度短的長度，於與前述電線的鋪設方向正交的方向上，具有比前述記憶體晶片的長度長的長度的矩形的形狀，配置於最下階的基板的金屬板，係具有配置於其長邊方向的端部，與配置於比最下階還上階的基板的金屬板、前述散熱構材熱性連接的熱傳達部。
  6. 如申請專利範圍第5項的半導體記憶裝置，其中，於前述基板，係形成供於配置前述金屬板用的開口或薄部。
  7. 如申請專利範圍第1項的半導體記憶裝置，其具備：以面朝下的態樣搭載前述記憶體晶片的基板；形成於前述傳送路上的保護層；以及設於前述記憶體晶片的前述電路面上的第2絕緣層；前述薄膜電容的前述第1面電極，係形成於前述第2絕緣層上，前述第1絕緣層，係於中心墊側，使第1電源輸出部及第2電源輸出部曝 露而形成於前述薄膜電容上，於中心墊側的相反側，以前述信號輸入部於前述保護層上曝露的方式而回蝕，前述第2絕緣層，係於中心墊側的相反側，以前述第1電源輸入部及前述第2電源輸入部在前述第1絕緣層上曝露的方式而回蝕，前述保護層，係形成為於中心墊側，在前述第2絕緣層上使前述信號輸出部曝露，於中心墊側的相反側，使前述信號輸入部在其上曝露，前述第1電源輸出部、前述第2電源輸出部、及前述信號輸出部、前述複數個中心墊係藉焊線方式而連接，形成於前述記憶體晶片的前述電路面上的前述第2絕緣層、前述薄膜電容、前述第1絕緣層、前述傳送路、及前述保護層，係以前述記憶體晶片成為最上階且前述保護層成為最下階的方式將上下反轉而搭載於前述基板上，前述基板，係包含與前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部連接的複數個連接墊，前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部、前述複數個連接墊係藉焊線方式而連接。
  8. 如申請專利範圍第1項的半導體記憶裝置，其具備：基板；形成於前述基板上的前述第1絕緣層； 形成於前述第1絕緣層上的第2絕緣層；以及形成於前述薄膜電容上的保護膜；前述記憶體晶片，係以面朝下搭載於前述保護膜上，前述第2絕緣層，係形成於除前述傳送路的前述信號輸入部的前述第1絕緣層上，前述薄膜電容的前述第1面電極，係形成於前述第2絕緣層上，前述第1電源輸出部，係包含形成於第2絕緣層上的第1電源輸出配線，前述第2電源輸出部，係包含形成於第2絕緣層上的第2電源輸出配線，前述傳送路的信號輸出部，係包含形成於前述第2絕緣層內的導孔、與前述導孔連接並形成於第2絕緣層上的信號輸出配線，前述基板，係包含與前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部連接的複數個連接墊，前述第1電源輸入部、前述第2電源輸入部、及前述信號輸入部、前述複數個連接墊係藉焊線方式而連接，前述第1電源輸出配線、前述第2電源輸出配線、及前述信號輸出配線、前述複數個中心墊係藉凸塊而連接。
  9. 如申請專利範圍第7或8項的半導體記憶裝置，其中，具備配置於前述記憶體晶片的前述背面上的散熱構材。
  10. 如申請專利範圍第1項的半導體記憶裝置，其中，具備形成於前述中心墊區域的兩側的至少一對的前述薄膜電容。
  11. 如申請專利範圍第1項的半導體記憶裝置，其中，前述第2面電極，係俯視下，於對應於前述第1面電極的區域內，分割成複數個。
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US20170092615A1 (en) 2017-03-30
CN107408402A (zh) 2017-11-28
WO2016194132A1 (ja) 2016-12-08
CN107408402B (zh) 2019-03-08
JPWO2016194132A1 (ja) 2017-06-15
US9627354B1 (en) 2017-04-18
JP5874072B1 (ja) 2016-03-01
TWI548061B (zh) 2016-09-01
KR20170002373A (ko) 2017-01-06

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