CN113939911A - 一种芯片以及集成芯片 - Google Patents

一种芯片以及集成芯片 Download PDF

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Publication number
CN113939911A
CN113939911A CN201980097019.3A CN201980097019A CN113939911A CN 113939911 A CN113939911 A CN 113939911A CN 201980097019 A CN201980097019 A CN 201980097019A CN 113939911 A CN113939911 A CN 113939911A
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China
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chip
pins
layer
integrated
disposed
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Pending
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CN201980097019.3A
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Inventor
张晓东
张童龙
官勇
李珩
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication of CN113939911A publication Critical patent/CN113939911A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种芯片以及集成芯片，以解决现有技术中封装芯片中上下层芯片需要通过TSV方式互连，导致下层芯片结构中的翘曲风险高、设计复杂度以及制作工艺难度大的问题。该集成芯片包括互连层，设置在互连层上的第一芯片，第二芯片以及第一垂直互连结构。其中，第二芯片包括第一部分和第二部分，第一部分被设置在第一芯片的顶部表面上，第二部分突出于第一芯片的侧方；第一垂直互连结构设置在第一芯片的侧方，第二芯片的第二部分通过第一垂直互连结构与互连层电性连接，即第一芯片与第二芯片相错设置，第一垂直互连结构与第二芯片的第二部分设置在第一芯片的同侧，第二芯片的第二部分绕过第一芯片，通过第一垂直互连结构与互连层电性连接。

Description

PCT国内申请，说明书已公开。

Claims (27)

  1. PCT国内申请，权利要求书已公开。
CN201980097019.3A 2019-05-31 2019-05-31 一种芯片以及集成芯片 Pending CN113939911A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/089691 WO2020237685A1 (zh) 2019-05-31 2019-05-31 一种芯片以及集成芯片

Publications (1)

Publication Number Publication Date
CN113939911A true CN113939911A (zh) 2022-01-14

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CN201980097019.3A Pending CN113939911A (zh) 2019-05-31 2019-05-31 一种芯片以及集成芯片

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CN (1) CN113939911A (zh)
WO (1) WO2020237685A1 (zh)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012164794A (ja) * 2011-02-07 2012-08-30 Sony Corp 積層配線基板
KR101847162B1 (ko) * 2011-09-27 2018-05-29 삼성전기주식회사 반도체 패키지 및 그 제조방법
CN103311207A (zh) * 2013-05-29 2013-09-18 华为技术有限公司 堆叠式封装结构
CN105118823A (zh) * 2015-09-24 2015-12-02 中芯长电半导体（江阴）有限公司 一种堆叠型芯片封装结构及封装方法

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