CN113498549A - 封装面积减小的高带宽管芯到管芯互连件 - Google Patents

封装面积减小的高带宽管芯到管芯互连件 Download PDF

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CN113498549A
CN113498549A CN202080016057.4A CN202080016057A CN113498549A CN 113498549 A CN113498549 A CN 113498549A CN 202080016057 A CN202080016057 A CN 202080016057A CN 113498549 A CN113498549 A CN 113498549A
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die
interposer
package structure
local
vertical
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仲崇华
翟军
胡坤忠
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Apple Inc
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Apple Inc
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Abstract

描述了具有折叠管芯布置的封装结构及制造方法。在一个实施方案中，封装结构包括并排的第一管芯和竖直中介层。第二管芯面朝下位于竖直中介层上并与其电连接，并且局部中介层将第一管芯与竖直中介层电连接。

Description

封装面积减小的高带宽管芯到管芯互连件
背景技术
技术领域
本文所述的实施方案涉及半导体封装，并且更具体地讲，涉及折叠管芯封装结构。
背景技术
对便携式和移动电子设备诸如移动电话、个人数字助理(PDA)、数字相机、便携式播放器、游戏设备和其他移动设备的当前市场需求要求将更多性能和特征集成到越来越小的空间中。虽然半导体管芯封装的形状因数(例如，厚度)和占位面积(例如，面积)正在减小，但片上系统(SoC)设计正变得更加复杂。
缩放特征以减少单片管芯中的技术节点通常是满足较高SoC需求和减小面积两者的方法。这继而对设计验证提出了显著更高的要求，这导致对芯片(也称为管芯)内的某些SoC核(也称为IP块)的硬件和/或软件(诸如中央处理单元(CPU)、GPU(图形处理单元)、存储器应用处理器(MEM/AP)、电压调节、无源集成等)的划分。
最近，行业已开始研究将SoC核管芯分裂成单独的管芯。若干先进的封装解决方案已成为适应SoC管芯分裂的潜在候选方案，诸如具有重新分布层(RDL)的扇出型封装、具有并排安装在中介层上的管芯的2.5D封装、或具有堆叠管芯的3D封装。
发明内容
实施方案描述了包括折叠管芯布置的封装结构。具体地讲，此类折叠管芯布置可用于将SoC核分裂成单独的管芯。在一个实施方案中，折叠管芯布置利用竖直中介层和局部中介层的组合来实现，以电连接分裂的管芯。竖直中介层提供竖直互连，而局部中介层提供横向互连。
附图说明
图1是根据一个实施方案的堆叠封装结构的横截面侧视图图示。
图2是根据一个实施方案的各种封装部件的示意性顶视图布局图示。
图3是示出了根据一个实施方案的形成封装结构的序列的流程图。
图4A至图4F是根据一个实施方案的形成封装结构的序列的横截面侧视图图示。
图5是根据一个实施方案的堆叠封装结构的横截面侧视图图示。
图6是根据一个实施方案的倒装芯片球珊阵列封装结构的横截面侧视图图示。
具体实施方式
实施方案描述了包括折叠管芯布置的封装结构。具体地讲，此类折叠管芯布置可用于将SoC核分裂成单独的管芯。在一个实施方案中，封装结构包括第一布线层，该第一布线层包括第一侧和与第一侧相对的第二侧。第一管芯和竖直中介层可以并排位于第一布线层的第一侧上。该竖直中介层包括从竖直中介层的与第一布线层的第一侧耦接的第一侧到竖直中介层的与竖直中介层的第一侧相对的第二侧的电互连件。第二管芯面朝下位于竖直中介层的第二侧上并与该竖直中介层电连接，并且局部中介层位于第一布线层的第二侧上并与第一管芯和竖直中介层电连接。
在一个方面，根据实施方案的折叠管芯封装结构可利用竖直堆叠和局部中介层两者来同时实现高带宽管芯到管芯互连件和封装占位面积(面积)减小。与扇出型RDL或2.5D封装解决方案相比，此类堆叠布置可减少占位面积。此外，与3D封装解决方案相比，此类堆叠布置可提供显著的成本节省。在3D封装解决方案中，使用诸如硅通孔(TSV)的技术形成的面到面管芯互连件可为昂贵的。
在各种实施方案中，参照附图来进行描述。然而，某些实施方案可在不存在这些具体细节中的一个或多个具体细节或者不与其他已知的方法和构型相结合的情况下被实施。在以下的描述中，示出许多具体细节诸如特定构型、尺寸和工艺等，以提供对实施方案的透彻理解。在其他情况下，未对熟知的半导体工艺和制造技术进行特别详细地描述，以免不必要地模糊实施方案。整个说明书中所提到的“一个实施方案”是指结合实施方案所描述的特定特征、结构、构型或特性被包括在至少一个实施方案中。因此，整个说明书中多处出现短语“在一个实施方案中”不一定是指相同的实施方案。此外，特定特征、结构、构型或特性可以任何适当的方式组合在一个或多个实施方案中。
本文所使用的术语“在…上方”、“至”、“在…之间”、“跨”和“在…上”可指一层相对于其他层的相对位置。一层相对于另一层来说为“在其上方”、“跨其”、或“在其上”或者结合“至”另一层或者与另一层“接触”可为直接与另一层接触或可具有一个或多个居间层。一层在多层“之间”可为直接与该多层接触或可具有一个或多个居间层。
现在参见图1，根据实施方案提供了堆叠封装(PoP)结构的横截面侧视图图示。如图所示，PoP结构300可包括具有根据实施方案的折叠管芯布置的下部封装结构100，以及安装在下部封装结构100上的顶部封装结构200。如图所示，下部封装结构100可包括第一封装级111和在第一封装级111下方的第二封装级171。第一封装级可包括堆叠在第一管芯110上并与第一管芯110偏置的第一管芯140。例如，这可通过将第一管芯140堆叠在第二管芯110和机械小芯片120(例如，硅)上来实现。竖直中介层130也堆叠在第二管芯110上，并且与第二管芯电连接。布线层160跨越第一管芯140的端子146和竖直中介层130的端子136。根据实施方案，布线层160可与竖直中介层130和第一管芯140扇出或扇入连接。虽然布线层160可在竖直中介层130与第一管芯140之间形成一些电连接，但根据实施方案，布线层160不形成竖直中介层130与第一管芯140之间的所有电连接。在一些实施方案中，布线层160不包括竖直中介层与第一管芯之间的任何电连接。如图1所示，位于第二封装级171内的局部中介层170可用于完成第一管芯140与竖直中介层130之间的电连接，其继而连接到第二管芯110，从而完成从第一管芯140到布线层160(任选的)、到局部中介层170、到布线层160(任选的)、到竖直中介层130、到第二管芯110的电路径。因此，该方法利用竖直堆叠(第一管芯140、第二管芯110、竖直中介层130)以及局部中介层170两者来实现高带宽管芯到管芯互连和封装面积减小两者。
根据实施方案，例如，第一管芯140可为包括较高性能核(例如CPU、GPU)或用较小节点技术制造的核的主芯片，而第二管芯110可为包括较低性能核(例如RF、存储器)或用较大节点技术制造的核的子芯片。设想了多种潜在的管芯分裂原因。
在一个实施方案中，封装结构包括第一布线层160，该第一布线层包括第一侧162和与第一侧相对的第二侧164。第一管芯140和竖直中介层130并排(并且横向相邻)位于第一布线层160的第一侧162上。该竖直中介层130包括从竖直中介层的与第一布线层160的第一侧162耦接的第一侧132到竖直中介层的与竖直中介层的第一侧相对的第二侧164的电互连件130。例如，电互连件130可为或包括穿过块状硅小芯片的柱或硅通孔(TSV)。第二管芯110面朝下位于竖直中介层130的第二侧134上并与竖直中介层的第二侧电连接。根据实施方案，局部中介层170安装在第一布线层160的第二侧164上并且与第一管芯140和竖直中介层130电连接。在一个实施方案中，局部中介层170包括位于局部中介层的与第一布线层160的第二侧164耦接的第一侧172上的多个端子176，并且局部中介层170不包括位于局部中介层的与局部中介层的第一侧172相对的第二侧174上的端子。因此，局部中介层170可用于第一管芯140与竖直中介层130之间的横向布线，而不是竖直中介层130的竖直布线。
仍然参考图1，第一模制化合物150可包封第一管芯140、竖直中介层130和第二管芯110。另外，机械小芯片120可附接到第一管芯140，且与第二管芯110横向相邻。更具体地讲，第一管芯140可例如用粘合剂层148附接到第二管芯110和机械小芯片120。第一多个导电柱104可从第一布线层160延伸并穿过第一模制化合物150。
第二模制化合物180可包封第一布线层160的第二侧164上的局部中介层170。另外，第二多个导电柱185可从第一布线层160延伸并穿过第二模制化合物180。如图所示，第二布线层190可形成在第二模制化合物180上并且连接到第二多个导电柱185。在一个实施方案中，第二布线层190位于包括第二模制化合物180、第二多个导电柱185和局部中介层170的平坦化表面上。焊料凸块199可以放置在第二布线层190的着落焊盘196上。例如，焊料凸块199可用于安装到电路板上。
在图1所示的特定堆叠封装(PoP)实施方案中，第二封装200可安装在下部封装100上。例如，第二封装200可安装在第一多个导电柱104上并且与第一多个导电柱电连接。在一个实施方案中，第二封装包括与布线衬底220连接并且包封在模制化合物230内的芯片210。在一个实施方案中，芯片210是存储器芯片，诸如动态随机存取存储器(DRAM)或NAND。芯片210可通过多种方法(包括引线接合212)与布线衬底220连接。
图2是根据一个实施方案的各种封装部件的示意性顶视图布局图示。虽然实施方案不限于所提供的特定配置，但是图2应当被理解为根据实施方案的折叠管芯结构的特别适当的实施方式。如图所示，第一管芯140可占据封装结构内的最大面积。第一管芯140也位于第二管芯110下方。该位置可有利于就近布线到封装结构内的电路板。
如图所示，第一管芯140和竖直中介层130彼此横向相邻或并列。第二管芯110或子芯片可根据需要根据其包含的核来设定尺寸。部件的相对宽度(W)在图1所示的横向重叠方向上示出。部件的相对深度(D)在与宽度正交的方向上示出。在一个实施方案中，第二管芯110与竖直中介层130重叠，并且可与竖直中介层130的区域完全重叠。第二管芯110可与第一管芯140部分地或完全地重叠。在所示的实施方案中，第二管芯110的面积比第一管芯140的面积小并且仅与第一管芯140部分地重叠。在此类实施方案中，机械小芯片120可与第一管芯140的一些剩余区域重叠。这可为封装结构提供机械稳定性和热膨胀匹配。机械小芯片120可另外有助于热性能。如图所示，局部中介层170与第一管芯140和竖直中介层130重叠。如图所示，部件的比较深度(D)可仅与横向和竖直布线所需的深度一样深。例如，局部中介层深度(D)可小于第一芯片140和任选的竖直中介层130的深度。竖直中介层130的深度比第二管芯110以及任选的局部中介层170的深度小。
在一个实施方案中，第一管芯140占据的面积比第二管芯110的面积大。第一管芯140和第二管芯110可包括分裂逻辑。例如，一个IP逻辑块(例如CPU)可在一个管芯中，而另一个IP逻辑块(GPU)在另一个管芯中。又如，一个IP逻辑块(例如，较高性能的块，具有可选的较小处理节点)在一个管芯中，而另一个IP逻辑块(例如，较低性能的块，具有可选的较大处理节点)在第二管芯中。在一个实施方案中，第一管芯140的第一晶体管形成有的处理节点比第二管芯110的第二晶体管的处理节点小。
现在参考图3和图4A至图4F，图3是示出了根据一个实施方案的形成封装结构的序列的流程图；图4A至图4F是根据一个实施方案的形成封装结构的序列的横截面侧视图图示。为了清楚简洁起见，参考图4A至图4F所示的特征来描述图3的流程图。在下面的描述中，处理序列可用于形成封装结构，并且具体地讲，形成关于图1所述的第一封装级结构和第二封装级结构，以及图5和图6中提供的结构变型。
如图4A所示，在操作3010处，将第二管芯110和机械小芯片120放置在承载衬底102上。第二管芯110可包括第一侧112和与第一侧相对的第二侧114。同样，机械小芯片120可包括与第二侧124相对的第一侧122。在所示的实施方案中，第二管芯110面朝上附接到承载衬底102。在一个实施方案中，第二管芯110的第一侧112包括暴露端子116(例如，铜焊盘)和钝化材料117。在一些实施方案中，钝化材料117可以是用于混合接合的氧化物材料(例如氧化硅)。第二管芯110和机械小芯片120可任选地分别用粘合剂层118、128固定在承载衬底102上。在一个实施方案中，机械小芯片120由硅形成以用于热膨胀匹配。
在图4A所示的实施方案中，第一多个导电柱104位于承载衬底102上。第一多个导电柱104可在放置第二管芯110和机械小芯片120之前形成。例如，第一多个导电柱104可被电镀。另选地，第一多个导电柱104可放置在衬底上。这可在放置第二管芯110和机械小芯片120之前或稍后发生。在一个实施方案中，第二管芯110和机械小芯片120被放置在第一多个导电柱104的周边内或行之间。
在操作3020处，将竖直中介层130接合到第二管芯110，如图4B所示。竖直中介层130可使用诸如混合接合的技术接合以实现高密度端子间距(例如，小于15μm)，或者使用微(焊料)凸块以实现小于40μm的端子间距密度。竖直中介层130可包括竖直中介层的第一侧132上的端子136、从端子136延伸到竖直中介层的与竖直中介层的第一侧相对的第二侧134上的端子138的电互连件135。端子138接合到第二管芯110的端子116。在所示的具体实施方案中，竖直中介层130的第二侧134上的端子138和钝化层137(例如，氧化物)与第二管芯110的端子116和钝化层117混合接合(金属-金属和氧化物-氧化物)。
仍然参见图4B，在操作3030处，将第一管芯140放置在第二管芯110上，并且任选地放置在机械小芯片120上。第一管芯140可面朝上放置并用粘合剂148固定。如图所示，第一管芯140包括具有端子146的第一侧142和与第一侧142相对的第二侧144。第二管芯110和机械小芯片120可具有大致相同的高度以有利于附接第一管芯140。
应当理解，处理序列中可存在变型。例如，可在接合竖直中介层130之前放置第一管芯140。在另一个变型中，竖直中介层130和第二管芯110在放置在承载衬底102上之前接合。此外，第一多个导电柱104可在不同时间形成或放置。
现在参见图4C，在操作3040处，将第二管芯110、任选的机械小芯片120、竖直中介层130、第一管芯140和任选的第一多个导电柱104包封在模制化合物150中。这之后可进行附加的平面化和/或蚀刻以暴露端子146、136和第一多个导电柱104，该第一多个导电柱可在模制化合物150的第一侧152和第二侧154之间延伸。在另选的处理序列中，第一多个导电柱104在模制操作之后形成于模制化合物150中。
然后任选地在模制化合物的第一侧152、第一管芯140的第一侧142、竖直中介层130的第一侧132上形成布线层160，并且该布线层160与第一管芯140的端子146和竖直中介层130的端子136电连接，如图4D所示。布线层160也可称为重新分布层(RDL)。例如，布线层160可形成有电介质层166沉积和图案，以及金属晶种沉积、图案和电镀(例如，铜)以形成重新分布线164。接触焊盘也可形成为布线层160中的重新分布线的一部分或作为重新分布线的补充。
现在参见图4E，在操作3050处，局部中介层170安装在第一管芯140和竖直中介层130上并与第一管芯和竖直中介层电连接。在一个实施方案中，局部中介层170包括单个面并且面朝下安装。例如，局部中介层170包括第一侧172、与第一侧相对的第二侧174。第一侧包括分别接合到第一管芯140的端子146和竖直中介层130的端子136的多个端子176。在一个实施方案中，使用焊料凸块179完成接合。如图所示，局部中介层170包括布线171以电连接竖直中介层130和第一管芯140。
类似地，与第一多个导电柱104一样，第二多个导电柱185可形成在布线层160上。第二多个导电柱185可在放置局部中介层170之前形成。例如，第二多个导电柱185可被电镀。另选地，第二多个导电柱185可放置在底层结构上。这可在放置局部中介层170之前或稍后发生。在一个实施方案中，局部中介层170放置在第二多个导电柱185的周边内或行之间。
现在参见图4F，在操作3060处，局部中介层170和任选地第二多个导电柱185被包封在第二模制化合物180中。这之后可进行附加的平面化和/或蚀刻以暴露局部中介层170的第二侧174和第二多个导电柱185，该第二多个导电柱185可在第二模制化合物180的第一侧182和第二侧184之间延伸。在另选的处理序列中，第二多个导电柱185在模制操作之后形成于模制化合物180中。
然后可根据要形成的最终封装结构执行各种处理序列。在图4F所示的示例性实施方案中，包括一个或多个绝缘层192和布线层194的第二布线层190形成在第二模制化合物180的第一侧182、暴露的第二多个柱185上，并且任选地直接形成在局部中介层174的第二侧174上。第二布线层190可以包括着落焊盘196，并且焊料凸块199可以放置在着落焊盘196上以进一步集成，然后移除承载衬底102。
图5是根据一个实施方案的堆叠封装结构的横截面侧视图图示。图5基本上类似于图1中提供的结构，不同的是使用微(焊料)凸块139将竖直中介层130接合到第二管芯110。
图6是根据一个实施方案的倒装芯片球珊阵列(FCBGA)封装结构的横截面侧视图图示。如前所述，包括第一封装级111和第二封装级171的封装结构可集成到包括PoP和倒装芯片FCBGA的多种封装配置中。在图6所示的实施方案中，着落焊盘196可位于螺柱197上。封装结构100可用焊料凸块199接合到封装衬底402。然后可将底部填充材料195施加在封装100和封装基底402之间。然后可将封装(焊料)凸块404施加到封装衬底402的相对侧以用于安装到电路板上等。
在利用实施方案的各个方面时，对本领域技术人员显而易见的是，对于形成折叠管芯封装结构而言，以上实施方案的组合或变型是可能的。尽管以特定于结构特征和/或方法行为的语言对实施方案进行了描述，但应当理解，所附权利要求并不一定限于所描述的特定特征或行为。所公开的特定特征和行为相反应当被理解为用于进行例示的权利要求的实施方案。

Claims (20)

1.一种封装结构，包括：
第一布线层，所述第一布线层包括第一侧和与所述第一侧相对的第二侧；
第一管芯和竖直中介层，所述第一管芯和所述竖直中介层并排位于所述第一布线层的所述第一侧上，其中所述竖直中介层包括从所述竖直中介层的与所述第一布线层的所述第一侧耦接的第一侧到所述竖直中介层的与所述竖直中介层的所述第一侧相对的第二侧的电互连件；
第二管芯，所述第二管芯面朝下位于所述竖直中介层的所述第二侧上并与所述竖直中介层的所述第二侧电连接；和
局部中介层，所述局部中介层位于所述第一布线层的所述第二侧上并且与所述第一管芯和所述竖直中介层电连接。
2.根据权利要求1所述的封装结构，其中所述局部中介层在所述局部中介层的第一侧上包括多个端子，所述局部中介层的所述第一侧与所述第一布线层的所述第二侧耦接，并且所述局部中介层在所述局部中介层的第二侧上不包括端子，所述局部中介层的所述第二侧与所述局部中介层的所述第一侧相对。
3.根据权利要求1所述的封装结构，其中所述第一管芯占据比所述第二管芯占据的面积大的面积。
4.根据权利要求3所述的封装结构，其中所述第一管芯和所述第二管芯包括分裂逻辑。
5.根据权利要求3所述的封装结构，其中所述第一管芯的第一晶体管形成有比所述第二管芯的第二晶体管的处理节点小的处理节点。
6.根据权利要求3所述的封装结构，其中所述第二管芯占据比所述竖直中介层占据的面积大并且比所述局部中介层占据的面积大的面积。
7.根据权利要求2所述的封装结构，其中所述竖直中介层与所述第二管芯混合接合。
8.根据权利要求2所述的封装结构，其中焊料凸块将所述竖直中介层与所述第二管芯电连接。
9.根据权利要求1所述的封装结构，还包括第一模制化合物，所述第一模制化合物包封所述第一管芯、所述竖直中介层和所述第二管芯。
10.根据权利要求1所述的封装结构，还包括机械小芯片，所述机械小芯片与所述第二管芯横向相邻地附接到所述第一管芯。
11.根据权利要求9所述的封装结构，还包括第一多个导电柱，所述第一多个导电柱从所述第一布线层延伸并穿过所述第一模制化合物。
12.根据权利要求9所述的封装结构，还包括第二模制化合物，所述第二模制化合物包封位于所述第一布线层的所述第二侧上的所述局部中介层。
13.根据权利要求12所述的封装结构，还包括第二多个导电柱，所述第二多个导电柱从所述第一布线层延伸并穿过所述第二模制化合物。
14.根据权利要求13所述的封装结构，还包括第二布线层，所述第二布线层位于所述第二模制化合物上并且连接到所述第二多个导电柱。
15.根据权利要求14所述的封装结构，其中所述第二布线层位于包括所述第二模制化合物、所述第二多个导电柱和所述局部中介层的平坦化表面上。
16.根据权利要求13所述的封装结构，还包括第二封装，所述第二封装位于所述第一多个导电柱上并与所述第一多个导电柱电连接。
17.根据权利要求13所述的封装结构，还包括多个焊料凸块，所述多个焊料凸块将所述第二布线层电连接到封装布线衬底。
18.一种形成封装结构的方法，包括：
将第二管芯和机械小芯片放置在承载衬底上；
将竖直中介层接合到所述第二管芯；
将第一管芯放置在所述第二管芯和所述机械小芯片上；
将所述第二管芯、所述机械小芯片、所述竖直中介层和所述第一管芯包封在第一模制化合物中；
将局部中介层安装在所述竖直中介层和所述第一管芯上并与所述竖直中介层和所述第一管芯电连接；以及
将所述局部中介层包封在第二模制化合物中。
19.根据权利要求18所述的方法，其中将所述竖直中介层接合到所述第二管芯包括混合接合。
20.根据权利要求18所述的方法，其中将所述竖直中介层接合到所述第二管芯包括形成焊料凸块。
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