WO2021159306A1 - 封装结构及其制备方法和电子设备 - Google Patents

封装结构及其制备方法和电子设备 Download PDF

Info

Publication number
WO2021159306A1
WO2021159306A1 PCT/CN2020/074879 CN2020074879W WO2021159306A1 WO 2021159306 A1 WO2021159306 A1 WO 2021159306A1 CN 2020074879 W CN2020074879 W CN 2020074879W WO 2021159306 A1 WO2021159306 A1 WO 2021159306A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
redistribution layer
layer
heat
package
Prior art date
Application number
PCT/CN2020/074879
Other languages
English (en)
French (fr)
Inventor
李珩
张晓东
王思敏
戚晓芸
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202080096220.2A priority Critical patent/CN115066746A/zh
Priority to PCT/CN2020/074879 priority patent/WO2021159306A1/zh
Publication of WO2021159306A1 publication Critical patent/WO2021159306A1/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions

Definitions

  • This application relates to the field of packaging technology, and in particular to a packaging structure, a preparation method thereof, and electronic equipment.
  • the embodiment of the present application provides a package structure to improve the heat dissipation effect of the package structure.
  • the embodiments of the present application also provide a method for manufacturing the packaging structure and electronic equipment.
  • the embodiment of the present application provides a package structure, including a first redistribution layer and a first chip, the first redistribution layer includes a first metal circuit and a first heat conducting member connected to the first metal circuit, the The first heat conducting member at least partially exposes the top surface of the first redistribution layer, the front surface of the first chip is used to transmit signals, and the back surface of the first chip is set opposite to the front surface of the first chip On the passive surface, the back side of the first chip is provided on the top surface and connected with the first heat conducting member.
  • the back side of the first chip in the package structure described in the embodiment of the application is connected to the first heat-conducting member, so as to transfer the heat of the first chip from the back to the first metal circuit via the first heat-conducting member, that is, the The heat of a chip is transferred from the passive surface to the first metal circuit via the first heat-conducting element, and finally is exported through the first metal circuit, so as to effectively export the heat of the first chip from the back side, so that the first chip is in the vertical direction. It has a good heat dissipation effect, improves the electrical performance of the first chip, and further improves the electrical performance of the packaging structure.
  • a barrier layer is provided on the back surface of the first chip, and the barrier layer is connected between the back surface and the first heat conducting member.
  • the barrier layer is used to isolate the first chip and the first heat-conducting element, so as to prevent the material in the first heat-conducting element from diffusing into the first chip, affecting the electrical performance of the first chip, and even causing the first chip to fail.
  • the material of the barrier layer is, for example, silicon nitride.
  • the material of the barrier layer can also be other materials that can prevent the material in the first heat conducting element from diffusing into the first chip.
  • an adhesive layer is provided between the barrier layer and the first heat-conducting member, and the adhesive layer adheres the first chip to the top surface.
  • the adhesive layer is used to fix the first chip on the top surface, so that when the first package body encapsulates the first chip on the first redistribution layer, the first chip will not be offset during the packaging process, which improves The finished quality of the package structure.
  • the packaging structure includes a first packaging body, the first packaging body is packaged on the first chip, and the pins on the front surface of the first chip expose the first packaging body.
  • the pins of the first chip expose the surface of the first package body to facilitate the electrical connection of the first chip with other structures.
  • the package structure includes a second redistribution layer, the second redistribution layer is disposed on the first package body, and the second redistribution layer includes a second metal circuit and the second redistribution layer.
  • the package structure includes a first connection post, and the first connection post is disposed in the first package body and connected between the first metal circuit and the second metal circuit.
  • the first connecting post is used for realizing electrical connection and at the same time realizing heat transfer between the first metal circuit and the second metal circuit and transferring the heat in the first package body, so as to further improve the heat dissipation effect of the package structure.
  • the packaging structure includes a second chip and a second packaging body.
  • the second package is packaged on the second chip, and the pins of the second chip expose the second package.
  • the heat of the second chip is transferred to the second metal circuit through the second heat-conducting member, and then conducts heat to the outside through the second metal circuit, so that the second chip has a good heat dissipation effect in the vertical direction, and improves the second chip's heat dissipation.
  • the electrical performance thereby improving the electrical performance of the package structure.
  • the first chip is a memory chip
  • the second chip is a CPU chip
  • the package structure includes a third redistribution layer and solder balls, the third redistribution layer is disposed on the second package body, and the solder balls are disposed on the third redistribution layer ,
  • the third metal circuit of the third redistribution layer is connected between the pin of the second chip and the solder ball.
  • the third rewiring layer is not only used for electrical connection, but also transfers the heat transferred from the first chip and the second chip to the third metal circuit to the outside through the solder balls, which are used for electrical connection with other electronic components.
  • the package structure includes a second connecting pillar, and the second connecting pillar is disposed in the second package body and connected between the second metal circuit and the third metal circuit.
  • the second connecting pillar is used for realizing the connection between the circuits and at the same time can conduct the heat transferred from the second chip to the second metal circuit to other parts, so as to further improve the heat dissipation effect of the package structure.
  • An embodiment of the application also provides a package structure, including a first redistribution layer, a first chip, a first heat transfer element, and a first package body.
  • the first redistribution layer includes a first metal circuit, and the first The metal circuit part exposes the top surface of the first redistribution layer, the front surface of the first chip is used to transmit signals, and the back surface of the first chip is a passive surface disposed opposite to the front surface of the first chip ,
  • the pins on the front of the first chip are arranged on the top surface and connected with the first metal circuit, the first heat transfer element is arranged on the back side of the first chip, and the first On the package body package and the first chip, the first heat transfer element is exposed on the surface of the first package body.
  • the first heat transfer element is arranged on the back side of the first chip, that is, the first heat transfer element is arranged on the passive surface side of the first chip.
  • the first heat transfer element exposes the surface of the first package body. That is, the heat of the first chip is transferred out of the first package through the first heat transfer member to dissipate heat, thereby effectively dissipating the heat of the first chip from the back surface to the outside of the package structure, so that the first chip has a very high vertical direction.
  • the good heat dissipation effect improves the electrical performance of the first chip, and further improves the electrical performance of the package structure.
  • the package structure further includes a metal body, the first heat transfer element is multiple, and the multiple first heat transfer elements are arranged at intervals, and the metal body is connected to the multiple first heat transfer elements.
  • One end of the component facing away from the first chip, and the first heat transfer component exposes the first package body through the metal body. Connecting the plurality of first heat transfer elements through the metal body on the one hand increases the heat dissipation area of the first chip, on the other hand, the plurality of first heat transfer elements can be more firmly connected to the subsequently formed heat conduction element through the metal body, so that The first chip has a good heat dissipation effect in the vertical direction, which improves the electrical performance of the first chip, thereby improving the electrical performance of the packaging structure.
  • a barrier layer is provided on the back surface of the first chip, and the barrier layer is connected between the back surface and the first heat transfer element.
  • the barrier layer is used to isolate the first chip and the first heat transfer element, so as to prevent the material in the first heat transfer element from diffusing into the first chip, affecting the electrical performance of the first chip, and even causing the first chip to fail.
  • the material of the barrier layer is, for example, silicon nitride.
  • the material of the barrier layer can also be other materials that can prevent the material in the first heat transfer element from diffusing into the first chip.
  • the package structure includes a second redistribution layer, the second redistribution layer is disposed on the first package body, and the second redistribution layer includes a second metal circuit and the second redistribution layer.
  • the second heat-conducting member is used to connect the first heat-transfer member, so that the heat of the first heat-transfer member transferred from the first chip is transferred to the second metal circuit through the second heat-conducting member and is conducted out through the second metal circuit, so that The first chip has a good heat dissipation effect in the vertical direction, which improves the electrical performance of the first chip, thereby improving the electrical performance of the packaging structure.
  • the package structure includes a first connection post, and the first connection post is disposed in the first package body and connected between the first metal circuit and the second metal circuit.
  • the first connecting post is used to connect the first metal circuit and the second metal circuit, and at the same time can transfer the heat transferred from the first chip to the first package to other parts, or transfer the heat of the second metal circuit to the first metal The circuit further improves the heat dissipation effect of the package structure.
  • the package structure includes a second chip, a second package body, and a second heat transfer element, and the pins on the front side of the second chip are provided on the second redistribution layer and are connected to the first rewiring layer.
  • Two metal lines are connected, the second heat transfer element is provided on the back side of the second chip, the second package is packaged on the second chip, and the second heat transfer element exposes the first 2.
  • the surface of the package body. The heat of the second chip is transferred from the back side through the second heat transfer member, so that the second chip has a good heat dissipation effect in the vertical direction, and the electrical performance of the second chip is improved, thereby improving the electrical performance of the package structure .
  • the first chip is a memory chip
  • the second chip is a CPU chip
  • the package structure includes a third redistribution layer and solder balls, the third redistribution layer is disposed on the second package body, and the third redistribution layer is connected to a third metal line
  • the third heat conducting element is connected to the second heat transfer element, and the solder ball is arranged on the surface of the first redistribution layer facing away from the first chip and connected to the first metal circuit.
  • the third rewiring layer is not only used to realize electrical connection, but also transfers the heat transferred from the first chip and the second chip to the third metal circuit to the outside, and the solder balls are used to electrically connect with other electronic components.
  • the package structure includes a second connecting pillar, and the second connecting pillar is disposed in the second package body and connected between the second metal circuit and the third metal circuit.
  • the second connecting pillar is used to connect the second metal circuit and the third metal circuit and realize heat transfer, and at the same time, it can conduct the heat transferred from the second chip to the second package to other parts, further improving the heat dissipation effect of the package structure.
  • An embodiment of the present application also provides an electronic device, including the above-mentioned packaging structure.
  • the heat dissipation performance and stability of the electronic device with the packaging structure provided in the present application are significantly improved.
  • the embodiments of the present application also provide a method for manufacturing a package structure, and the manufacturing method includes the following steps:
  • the surface of the package wherein the front surface of the first chip is used for transmitting signals, and the back surface of the first chip is a passive surface disposed opposite to the front surface of the first chip.
  • the preparation method described in the embodiment of the application includes two solutions.
  • One solution is: the first chip is connected to the first redistribution layer, and the back of the first chip is connected to the first redistribution layer through the first heat-conducting member.
  • the first metal circuit is used to transfer the heat of the first chip from the back side to the first metal circuit via the first heat-conducting member, and finally out through the first metal circuit, thereby effectively dissipating the heat of the first chip from the back side, so that the first The chip has a good heat dissipation effect in the vertical direction, which improves the electrical performance of the first chip, thereby improving the electrical performance of the packaging structure.
  • the first chip is packaged on the first redistribution layer facing away from the first redistribution layer, and the back of the first chip is connected to the surface of the first package body through the first heat transfer element, that is, the first The heat of the chip is transferred out of the first package through the first heat transfer member for heat dissipation, thereby effectively dissipating the heat of the first chip from the back side to the outside of the package structure, so that the first chip has a good heat dissipation effect in the vertical direction , The electrical performance of the first chip is improved, thereby improving the electrical performance of the package structure.
  • the heat conduction structure (first heat conduction element or first heat transfer element) Connect to the back of the first chip, and conduct the heat dissipated by the first chip to the outside through the heat-conducting structure (the conduction path can be one side of the first redistribution layer, or it can be conducted to the first chip away from the first redistribution layer The surface of the first package).
  • the first heat-conducting member is formed in the first red-wiring layer during the process of making the first red-wiring layer, and is connected to the first metal circuit.
  • the component is at least partially exposed on the top surface of the first redistribution layer, and during the process of connecting the first chip to the first redistribution layer, the back surface of the first chip faces the top surface.
  • the first heat-conducting element is embedded in the first redistribution layer, that is, the first heat-conducting element does not occupy additional space, and the size of the package structure will not increase due to the addition of the first heat-conducting element.
  • the first heat-conducting element is formed at the same time as the first rewiring layer is formed, which reduces the manufacturing process, while dissipating heat for the first chip, improves the production efficiency of the packaging structure, and reduces the production cost of the packaging structure.
  • the first heat-conducting member is made of a metal material.
  • a barrier layer is formed on the back of the first chip. The back surface is separated from the first heat conducting member.
  • the barrier layer is used to isolate the first chip and the first heat-conducting element, so as to prevent the material in the first heat-conducting element from diffusing into the first chip, affecting the electrical performance of the first chip, and even causing the first chip to fail.
  • the material of the barrier layer is, for example, silicon nitride.
  • the material of the barrier layer can also be other materials that can prevent the material in the first heat conducting element from diffusing into the first chip.
  • the barrier layer and the top surface of the first redistribution layer are fixedly connected by an adhesive layer.
  • the adhesive layer is used to fix the first chip on the first redistribution layer, so that when the first package body encapsulates the first chip on the first redistribution layer, the first chip will not occur during the packaging process.
  • the offset improves the quality of the finished product of the package structure.
  • the first chip is packaged to the first redistribution layer by a first package, and the front side of the first chip
  • the pins expose the surface of the first package body.
  • the pins of the first chip expose the surface of the first package body to facilitate the electrical connection of the first chip with other structures.
  • a first connection pillar is formed on the first redistribution layer, and the first connection pillar is connected to the first metal line.
  • the first package body simultaneously encapsulates the first connecting pillars, and the first connecting pillars are partially exposed to the first rewiring layer.
  • the first connecting pillar is connected to a part of the first metal line exposing the surface of the first redistribution layer.
  • the first connecting pillar is used to connect the first metal line and the second metal line of the second redistribution formed in the subsequent process, and at the same time
  • the heat transferred from the first chip to the first metal circuit can also be conducted to other parts, which further improves the heat dissipation effect of the package structure.
  • the manufacturing method further includes fabricating a second redistribution layer on the first package body, and the second redistribution layer is provided with a second metal circuit and a second metal circuit connected to the second metal circuit.
  • Two heat-conducting elements the second heat-conducting element exposes the surface of the second redistribution layer facing away from the first chip, and the second metal circuit partially exposes the surface of the second redistribution layer facing the first chip and It is connected with the pin of the first chip and the first connecting pillar.
  • the second heat-conducting member is formed at the same time as the second rewiring layer is made, which effectively simplifies the manufacturing process of the packaging structure, improves production efficiency, and reduces production costs.
  • the preparation method further includes connecting a second chip to the second redistribution layer, so that the back of the second chip faces the second redistribution layer, and is connected by a second heat conducting member The second metal circuit.
  • the heat of the second chip is transferred to the second metal circuit through the second heat-conducting member, and then conducts heat to the outside through the second metal circuit, so that the second chip has a good heat dissipation effect in the vertical direction, and improves the second chip's heat dissipation.
  • the electrical performance thereby improving the electrical performance of the package structure.
  • the first chip is a memory chip
  • the second chip is a CPU chip
  • the second chip is packaged to the second redistribution layer by a second package, and the front side of the second chip
  • the pins expose the surface of the second package body.
  • the pins of the second chip are exposed on the surface of the second package body to facilitate the electrical connection between the second chip and other structures.
  • a second connection pillar is formed on the second redistribution layer, and the second connection pillar is connected to the second metal line.
  • the second package body simultaneously encapsulates the second connecting pillars, and the second connecting pillars are partially exposed to the first 2. The surface of the package body.
  • the second connecting pillar is connected to a part of the second metal line exposing the surface of the second redistribution layer, and the second connecting pillar is used to connect the second metal line and the third metal line of the third redistribution formed in the subsequent process, and at the same time
  • the heat transferred from the second chip to the second metal circuit can also be conducted to other parts, which further improves the heat dissipation effect of the package structure.
  • the manufacturing method further includes fabricating a third redistribution layer on the second package body, forming solder balls on the third redistribution layer, and the third metal of the third redistribution layer
  • the wires are connected to the pins of the second chip and the second connecting pillars.
  • the third rewiring layer is not only used for electrical connection, but also transfers the heat transferred from the first chip and the second chip to the third metal circuit to the outside through the solder balls, which are used for electrical connection with other electronic components.
  • a plurality of spaced first transmission paths are formed on the back side of the first chip.
  • the thermal element after the first chip is packaged in the first package, the back surface of the first chip is connected to the surface of the first package through a plurality of the first heat transfer elements.
  • the heat of the first chip is transferred from the back side through a plurality of first heat transfer elements formed on the back side of the first chip, and the plurality of first heat transfer elements can ensure effective heat transfer so that the first chip is in a vertical direction It has a good heat dissipation effect, improves the electrical performance of the first chip, and further improves the electrical performance of the package structure.
  • a plurality of spaced first transmission paths are formed on the back side of the first chip.
  • a thermal element a protective layer is formed on the back side of the first chip, the protective layer covers the first heat transfer element, and the end of the first heat transfer element away from the first chip exposes the A protective layer, after the first package body encapsulates the first chip, the surface of the protective layer facing away from the first chip exposes the surface of the first package body.
  • the heat of the first chip is transferred from the back side through a plurality of first heat transfer elements formed on the back side of the first chip, and the plurality of first heat transfer elements can ensure effective heat transfer so that the first chip is in a vertical direction It has a good heat dissipation effect, improves the electrical performance of the first chip, and further improves the electrical performance of the package structure.
  • a plurality of first heat transfer elements are fixed by the protective layer so that the first heat transfer elements will not be skewed during the packaging of the first chip, thereby further ensuring the heat dissipation of the first chip Effect.
  • a plurality of spaced first transmission paths are formed on the back side of the first chip.
  • the thermal element a protective layer is formed on the back side of the first chip, the protective layer covers the first heat transfer element, and a metal body is formed in the protective layer.
  • the first heat transfer element is connected, the part of the metal body away from the first heat transfer body exposes the protective layer, and after the first package body encapsulates the first chip, the protective layer faces away from the The surface of the first chip exposes the surface of the first package.
  • the heat of the first chip is transferred from the back side through a plurality of first heat transfer elements formed on the back side of the first chip.
  • the plurality of first heat transfer elements can ensure effective heat transfer, and the plurality of first heat transfer elements are transferred through the metal body.
  • the thermal element connection increases the heat dissipation area of the first chip.
  • the multiple first heat transfer elements can be connected to the subsequently formed heat conduction element more firmly through the metal body, so that the first chip has a vertical direction. The good heat dissipation effect improves the electrical performance of the first chip, and further improves the electrical performance of the package structure.
  • a plurality of first heat transfer elements and metal bodies are fixed through the protective layer so that the first heat transfer elements and the metal body will not be skewed during the process of packaging the first chip, thereby further ensuring The heat dissipation effect of the first chip is improved.
  • a plurality of spaced openings are formed on the first package body to expose the back side of the first chip.
  • the heat of the first chip is transferred from the back side through a plurality of first heat transfer elements formed on the back side of the first chip, and the plurality of first heat transfer elements can ensure effective heat transfer so that the first chip is in a vertical direction It has a good heat dissipation effect, improves the electrical performance of the first chip, and further improves the electrical performance of the package structure.
  • a first opening is formed in the first package body, and a plurality of spaced second openings are formed on the bottom wall of the first opening, The second opening exposes the back side of the first chip, and the first heat transfer element is formed in the first opening and the second opening.
  • the heat dissipation surface of the first heat transfer element is enlarged, so that the first chip has a good heat dissipation effect in the vertical direction, and the electrical performance of the first chip is improved, thereby improving the package Electrical properties of the structure.
  • the first heat transfer element is made of a metal material, and before the first heat transfer element is formed on the back side of the first chip, a barrier layer is formed on the back of the first chip, and The barrier layer separates the back surface and the first heat transfer member.
  • the barrier layer is used to isolate the first chip and the first heat transfer element, so as to prevent the material in the first heat transfer element from diffusing into the first chip, affecting the electrical performance of the first chip, and even causing the first chip to fail.
  • the material of the barrier layer is, for example, silicon nitride.
  • the material of the barrier layer can also be other materials that can prevent the material in the first heat transfer element from diffusing into the first chip.
  • a first connection pillar is formed on the first redistribution layer, and the first connection pillar is connected to the first metal line.
  • the first package body simultaneously encapsulates the first connecting pillars, and the first connecting pillars are partially exposed to the first rewiring layer.
  • the first connecting pillar is connected to a part of the first metal line exposing the surface of the first redistribution layer.
  • the first connecting pillar is used to connect the first metal line and the second metal line of the second redistribution formed in the subsequent process, and at the same time
  • the heat transferred from the first chip to the first package body can also be conducted to other parts, which further improves the heat dissipation effect of the package structure.
  • the manufacturing method further includes fabricating a second redistribution layer on the first package body, and the second redistribution layer is provided with a second metal circuit and a second metal circuit connected to the second metal circuit.
  • Two heat-conducting parts the second heat-conducting part exposes the surface of the second redistribution layer facing the first chip and is connected to the first heat-conducting part or the metal body, and the second metal circuit part is exposed
  • the second redistribution layer faces away from the surface of the first chip.
  • the second heat-conducting member is formed at the same time as the second rewiring layer is made, which effectively simplifies the manufacturing process of the packaging structure, improves production efficiency, and reduces production costs.
  • the second heat-conducting member is used to connect the first heat-transfer member, so that the heat of the first heat-transfer member transferred from the first chip is transferred to the second metal circuit through the second heat-conducting member and is conducted out through the second metal circuit to
  • the first chip has a good heat dissipation effect in the vertical direction, and the electrical performance of the first chip is improved, thereby improving the electrical performance of the packaging structure.
  • the manufacturing method further includes packaging a second chip on the second redistribution layer through a second package body, so that the pins of the second chip are connected to the second metal lines, and the The back surface of the second chip faces the second redistribution layer and is connected to the surface of the second package body through a second heat transfer element.
  • the heat of the second chip is transferred from the back side through the second heat transfer member, so that the second chip has a good heat dissipation effect in the vertical direction, and the electrical performance of the second chip is improved, thereby improving the electrical performance of the package structure .
  • the first chip is a memory chip
  • the second chip is a CPU chip
  • a second connection pillar is formed on the second redistribution layer, and the second connection pillar is connected to the second metal line.
  • the second package body simultaneously encapsulates the second connecting pillars, and the second connecting pillars are partially exposed to the first 2. The surface of the package body.
  • the second connecting pillar is connected to a part of the second metal line exposing the surface of the second redistribution layer, and the second connecting pillar is used to connect the second metal line and the third metal line of the third redistribution formed in the subsequent process, and at the same time
  • the heat transferred from the second chip to the second package body can also be conducted to other parts, which further improves the heat dissipation effect of the package structure.
  • the manufacturing method further includes fabricating a third redistribution layer on the second package body, forming solder balls on the surface of the first redistribution layer facing away from the first chip, and The third metal line of the triple wiring layer connects the second heat transfer element and the second connection pillar.
  • the third rewiring layer is not only used to realize electrical connection, but also transfers the heat transferred from the first chip and the second chip to the third metal circuit to the outside, and the solder balls are used to electrically connect with other electronic components.
  • the package structure described in the embodiments of the present application has two solutions.
  • the back side of the first chip is connected to the first heat-conducting member, so as to transfer the heat of the first chip from the back to the first heat-conducting member through the first heat-conducting member.
  • a metal circuit that is, transfer the heat of the first chip from the passive surface to the first metal circuit via the first heat-conducting member, and finally lead out through the first metal circuit, thereby effectively dissipating the heat of the first chip from the back side, so that
  • the first chip has a good heat dissipation effect in the vertical direction, which improves the electrical performance of the first chip, thereby improving the electrical performance of the packaging structure.
  • the first heat transfer element is arranged on the back side of the first chip, that is, the first heat transfer element is arranged on the passive surface side of the first chip, And the first heat transfer element exposes the surface of the first package body. That is, the heat of the first chip is transferred out of the first package through the first heat transfer member to dissipate heat, thereby effectively dissipating the heat of the first chip from the back surface to the outside of the package structure, so that the first chip has a very high vertical direction.
  • the good heat dissipation effect improves the electrical performance of the first chip, and further improves the electrical performance of the package structure.
  • the package structure provided by this application is connected to the first heat conduction structure (first heat conduction element or first heat transfer element).
  • the back side (passive surface) of the chip and conduct the heat dissipated by the first chip to the outside through the thermal conductive structure (the conduction path can be one side of the first redistribution layer, or it can be conducted to the first chip away from the first redistribution Layer on the surface of the first package body), thereby effectively improving the heat dissipation effect of the package structure in the vertical direction, thereby improving the electrical performance of the package structure.
  • FIG. 1 is a schematic diagram of a part of the structure of an electronic device provided by an embodiment of the present application.
  • Fig. 2 is a schematic structural diagram of the packaging structure in the electronic device shown in Fig. 1.
  • FIG. 3 is a schematic diagram of another structure of the package structure shown in FIG. 2.
  • Fig. 4 is a schematic structural diagram of a second package structure provided by the present application.
  • FIG. 5 is a schematic flow chart of the manufacturing method of the packaging structure shown in FIG. 2.
  • 6 to 11 are specific process flow diagrams of the preparation method shown in FIG. 5.
  • FIG. 12 is a schematic flow chart of a method for manufacturing the packaging structure shown in FIG. 4.
  • FIG. 13-18 are specific process flow diagrams of the preparation method shown in FIG. 12.
  • FIG. 1 is a partial structural diagram of an electronic device 100 according to an embodiment of the present application.
  • the electronic device 100 includes a casing, a circuit board 10 and a packaging structure 20.
  • the circuit board 10 and the packaging structure 20 are both contained in the casing, and the packaging structure 20 is connected to the circuit board 10 through solder balls.
  • the electronic device 100 in this embodiment includes, but is not limited to, electronic devices with a packaging structure 20 such as mobile phones, tablet computers, e-book readers, notebook computers, and desktop computers. Among them, multiple chips are embedded in the packaging structure 20, and the chips can be chips with different functions, such as active chip components such as memory chips, CPU chips, radio frequency drive chips, or other processor chips, to assist the electronic device 100 to achieve A variety of functions.
  • the packaging structure 20 of the present application has good heat dissipation effect and integration, and the heat dissipation performance and stability of the electronic device 100 with the packaging structure 20 provided by the present application have been significantly improved, and also meet the needs of lightweight design.
  • FIG. 2 is a schematic structural diagram of the packaging structure 20 in the electronic device 100 shown in FIG. 1.
  • FIG. 2 shows the first embodiment of the packaging structure 20.
  • the package structure 20 includes a first rewiring layer 21, a first chip 22, a first package body 23, a second rewiring layer 24, a second chip 25, a second package body 26, a third rewiring layer 27, and solder balls 28 .
  • the first package 23 encapsulates the first chip 22 on the first redistribution layer 21, the back of the first chip 22 faces the first redistribution layer 21, and the pins 221 on the front of the first chip 22 expose the first package 23 s surface.
  • the second rewiring layer 24 is provided on the first package body 23 and electrically connected to the pins 221 of the first chip 22 and the first rewiring layer 21.
  • the second package body 26 encapsulates the second chip 25 on the second rewiring layer.
  • the back surface of the second chip 25 faces the second redistribution layer 24, and the pins 251 on the front surface of the second chip 25 expose the surface of the second package body 26.
  • the third redistribution layer 27 is provided on the second package body 26 and is electrically connected to the pins 251 of the second chip 25 and the second redistribution layer 24.
  • the solder balls 28 are connected to the third redistribution layer 27 and pass through the third redistribution layer.
  • the wiring layer 27 is electrically connected to the first chip 22 and the second chip 25.
  • the front surfaces of the first chip 22 and the second chip 25 are surfaces provided with pins for transmitting signals
  • the back surface of the first chip 22 is a passive surface disposed opposite to the front surface of the first chip 22.
  • the back surface of the second chip 25 is a passive surface arranged opposite to the front surface of the second chip 25.
  • the first redistribution layer 21 includes a first insulating medium 211, a first metal circuit 212 and a first heat conducting member 213.
  • the first metal circuit 212 and the first heat conducting member 213 are connected and both are arranged in the first insulating medium 211.
  • the first redistribution layer 21 has a top surface 214 and a bottom surface 215 opposite to each other.
  • the top surface 214 and the bottom surface 215 of the first redistribution layer 21 are the top surface and the bottom surface of the first insulating medium 211.
  • there are a plurality of first heat-conducting members 213, and the plurality of first heat-conducting members 213 are arranged at intervals and at least partially expose the top surface 214 of the first redistribution layer 21.
  • the surface of the first rewiring layer 21 exposed by the plurality of first heat conducting members 213 is flush with the top surface 214, and the back side of the first chip 22 is provided on the top surface 214 and connected to the plurality of first heat conducting members 213 ,
  • the first metal circuit 212 In order to transfer the heat of the first chip 22 from the back to the first metal circuit 212 via the first heat-conducting member 213, and finally to export it through the first metal circuit 212, thereby effectively dissipating the heat of the first chip 22 from the back, so that the first One chip 22 has a good heat dissipation effect in the vertical direction, which improves the electrical performance of the first chip 22, and further improves the electrical performance of the package structure 20.
  • the first insulating medium 211, the first metal circuit 212, and the first heat conducting member 213 in this embodiment can be formed by a patterning process.
  • the first insulating medium 211 may be an insulating resin material, such as benzocyclobutene (BCB) or polyimide (PI), etc., formed by patterning processes such as exposure, development, and curing.
  • the first metal circuit 212 and the first heat-conducting member 213 may be formed by first forming a metal thin film layer by a deposition process, a sputtering process or an electroplating process, and then patterning the metal thin film layer by a patterning process such as etching.
  • the materials of the first metal circuit 212 and the first heat conducting member 213 may include conductive materials such as metallic copper and metallic aluminum. It can be understood that the middle part and the two side parts of the first metal circuit 212 in FIG. 2 are separated. This figure is only a cross-sectional view of the position in the figure, and the first metal circuit 212 is actually connected in other positions. Of course, in other embodiments, the specific shape of the first metal circuit 212 can be designed as required.
  • a part of the first heat conducting member 213 is exposed to the top surface 214 and is connected to the first package body 23, so as to transfer the heat conducted by the first chip 22 to the first package body 23, and improve the performance of the first chip 22. heat radiation.
  • the first metal circuit 212 partially exposes the bottom surface 215 of the first redistribution layer 21, and the connection interface 29 is provided on the bottom surface 215 and is connected to a part of the first metal circuit 212 exposed on the bottom surface 215 to realize the connection between the package structure 20 and other modules.
  • the other part of the first metal circuit 212 exposed on the bottom surface 215 is used to transfer the heat of the first chip 22 to the outside, so as to improve the heat dissipation effect of the package structure 20.
  • the implementation form of the first heat conducting member 213 and the connection interface 29 is not limited to the above description.
  • the first chip 22 is a memory chip.
  • the back surface of the first chip 22 is provided with a barrier layer 31, and the barrier layer 31 is connected between the back surface of the first chip 22 and the first heat conducting member 213.
  • the barrier layer 31 is used to isolate the first chip 22 and the first heat-conducting member 213, so as to prevent the metal material in the first heat-conducting member 213 from diffusing into the semiconductor material (such as silicon) on the back of the first chip 22 and affecting the conductivity of the semiconductor, thereby The electrical performance of the first chip 22 is affected, and the first chip 22 may even fail.
  • the material of the barrier layer 31 is, for example, silicon nitride.
  • the first chip 22 may also be an active electronic device such as a CPU chip, a radio frequency drive chip, or a chip of another processor.
  • the material of the barrier layer 31 can also be other materials that can prevent the material in the first heat conducting member 213 from diffusing into the first chip 22.
  • an adhesive layer 32 is provided between the barrier layer 31 provided on the back surface of the first chip 22 and the first heat conducting member 213, and the adhesive layer 32 adheres the first chip 22 to the top surface 214.
  • the adhesive layer 32 is used to fix the first chip 22 on the top surface 214, so that when the first package body 23 encapsulates the first chip 22 on the first redistribution layer 21, the first chip 22 will not be in the packaging process. The misalignment occurs, which improves the quality of the finished product of the package structure 20.
  • the barrier layer 31 can effectively prevent the first heat-conducting member 213 from spreading in the first chip 22, which improves the manufacturing quality of the package structure 20. Rate.
  • first heat conduction member 213 protruding from the top surface 214 is embedded in the first package body 23 to increase the contact area of the first heat conduction member 213 with the adhesive layer 32 and the first package body 23, so that the first chip The heat transferred from 22 and the first chip 22 to the first package body 23 is quickly transferred to the first metal circuit 212 through the first heat-conducting member 213, and then transferred to the outside through the first metal circuit 212, effectively improving the heat dissipation effect of the package structure 20 .
  • the part of the first rewiring layer 21 exposed by the plurality of first heat-conducting members 213 can also be directly held against the isolation layer 31.
  • the second rewiring layer 24 includes a second insulating medium 241, a second metal circuit 242 and a second heat conducting member 243.
  • the second metal circuit 242 and the second heat conducting member 243 are connected and both are arranged in the second insulating medium 241.
  • the second metal circuit 242 partially exposes the surface of the second redistribution layer 24 facing the first chip 22 and is connected to the pins 221 of the first chip 22.
  • the surface of the second rewiring layer 24 exposed by the plurality of second heat conductors 243 is flush with the surface of the second rewiring layer 24 facing away from the first chip 22, and the back side of the second chip 25 is set on the second rewiring layer 24.
  • the wiring layer 24 faces away from the surface of the first chip 22 and is connected to a plurality of second heat-conducting members 243 to transfer the heat of the second chip 25 from the back to the second metal circuit 242 via the second heat-conducting member 243, and finally through The second metal circuit 242 is led out, thereby effectively dissipating the heat of the second chip 25 from the back side, so that the second chip 25 has a good heat dissipation effect in the vertical direction, and the electrical performance of the second chip 25 is improved, thereby improving The electrical performance of the package structure 20 is improved.
  • the second rewiring layer 24 is formed using the same manufacturing process as the first rewiring layer 21.
  • the second heat conducting member 243 is also a part of the second heat conducting member 243 exposed to the second redistribution layer 24 and connected to the second package body 26, so as to transfer the heat conducted by the second chip 25 into the second package body 26, and improve the heat dissipation effect of the second chip 25 .
  • the second metal circuit 242 in FIG. 2 is only a state of a cross-sectional view of the position in the figure. Of course, in other embodiments, the specific shape of the second metal line 242 can be designed as required.
  • the implementation form of the second heat conducting member 243 is not limited to the above description.
  • the second chip 25 is a CPU chip.
  • a barrier layer 33 is provided on the back surface of the second chip 25, and the barrier layer 33 is connected between the back surface of the second chip 25 and the second heat conducting member 243.
  • the barrier layer 33 is used to isolate the second chip 25 and the second heat-conducting member 243, so as to prevent the metal material in the second heat-conducting member 243 from diffusing into the semiconductor material (such as silicon) on the back of the second chip 25 to affect the conductivity of the semiconductor, thereby The electrical performance of the second chip 25 is affected, and the second chip 25 may even fail.
  • the material of the barrier layer 33 is, for example, silicon nitride.
  • the second chip 25 may also be an active electronic device such as a memory chip, a radio frequency drive chip, or a chip of another processor.
  • the material of the barrier layer 33 can also be other materials that can prevent the material in the second heat conducting member 243 from diffusing into the second chip 25.
  • an adhesive layer 34 is provided between the barrier layer 33 on the back of the second chip 25 and the second heat conducting member 243, and the adhesive layer 34 bonds the second chip 25 to the second redistribution layer 24 .
  • the adhesive layer 34 is used to fix the second chip 25 on the second redistribution layer 24, so that when the second package body 26 encapsulates the second chip 25 on the second redistribution layer 24, the second chip 25 will not The deviation occurs during the packaging process, and the quality of the finished product of the packaging structure 20 is improved.
  • the barrier layer 34 can effectively prevent the second heat-conducting member 243 from spreading in the second chip 25, which improves the manufacturing quality of the package structure 20. Rate.
  • the portion of the second rewiring layer 21 exposed by the plurality of second heat conducting members 243 protrudes from the surface of the second rewiring layer 21 facing away from the first chip 22, so as to make adhesion
  • the second heat conductive member 243 partially protruding from the surface of the second redistribution layer 21 facing away from the first chip 22 is embedded in the adhesive layer 34 in.
  • a second heat conduction member 243 partially protruding from the surface of the second rewiring layer 21 facing away from the first chip 22 and embedded in the second package body 26 to enlarge the second heat conduction member 243 and the adhesive layer 34 and the second The contact area of the package body 26, so that the heat transferred from the second chip 25 and the second chip 25 to the second package body 26 is quickly transferred to the second metal line 242 through the second heat conducting member 243, and then is transferred through the second metal line 242 To the outside, the heat dissipation effect of the package structure 20 is effectively improved.
  • the part of the second rewiring layer 24 exposed by the plurality of second heat conducting members 243 can also be directly against the isolation layer 34.
  • the package structure 20 further includes a first connecting pillar 216, the first connecting pillar 216 is provided in the first package body 23, and both ends are respectively connected to the first redistribution layer 21 and the second redistribution layer 24 And contact with the first metal line 212 and the second metal line 242 in the first redistribution layer 21 and the second redistribution layer 24.
  • the parts of the first metal circuit 212 and the second metal circuit 242 connected to the first connection pillar 216 expose the top surface 214 and the surface of the second redistribution layer 24 facing the first connection pillar 216 to facilitate electrical connection with the first connection pillar 216. connect.
  • the first connecting post 216 is used to realize the electrical connection between the first metal circuit 212 and the second metal circuit 242, and at the same time realize the heat transfer between the first metal circuit 212 and the second metal circuit 242 and the heat transfer in the first package body 23. To further improve the heat dissipation effect of the package structure 20.
  • the third redistribution layer 27 includes a third insulating medium 271 and a third metal line 272, and the third metal line 272 is provided in the third insulating medium 271.
  • Part of the third metal line 272 exposes the surface of the third redistribution layer 27 facing the second chip 25 and is connected to the pins 251 of the second chip 25, and part of the third metal line 272 exposes the third redistribution layer 27 facing away from the second chip.
  • the surface of the chip 25 is connected to the solder ball 28.
  • the solder ball 28 is connected to the third metal circuit 272 that exposes the surface of the third redistribution layer 27 facing away from the second chip 25 through the pad 35.
  • the third redistribution layer 27 is formed using the same manufacturing process as the first redistribution layer 21.
  • the third rewiring layer 27 is not only used to realize the electrical connection between the solder balls 28 and the first chip 22 and the second chip 25, but also to transfer the heat of the first chip 22 and the second chip 25 to the third metal line 272 through the soldering.
  • the ball 28 is transferred to the outside, and the solder ball 28 is used for electrical connection with other electronic components.
  • the arrangement of the third metal circuit 272 and the solder balls 28 in FIG. 2 is only one of the examples listed in this embodiment. Of course, in other embodiments, the specific shape of the third metal line 272 and the solder ball 28 can be designed as required.
  • the package structure 20 includes a second connection pillar 244, the second connection pillar 244 is provided in the second package body 26, the two ends are respectively connected to the second rewiring layer 24 and the third rewiring layer 27, and the second rewiring layer
  • the second metal line 242 and the third metal line 272 in the wiring layer 24 and the third redistribution layer 27 are in contact.
  • the parts of the second metal line 242 and the third metal line 272 connected to the second connecting pillar 244 expose the surface of the second redistribution layer 24 and the third redistribution layer 27 facing the second connecting pillar 244 to facilitate the connection with the second
  • the post 244 is electrically connected.
  • the second connecting pillar 244 is used to realize the connection between the circuits and at the same time conduct the heat transferred from the second chip 25 to the second metal circuit 242 to other parts, so as to further improve the heat dissipation effect of the package structure 20.
  • the packaging structure 20 of the embodiment of the present application is packaged with two chips.
  • the back sides of the first chip 22 and the second chip 25 are respectively connected to the first heat-conducting member 213 and the second heat-conducting member 243, so as to reduce the heat of the first chip 22.
  • the package structure 20 of the present application solves the heat dissipation problem of the chip in the vertical direction, the package structure 20 can also realize the stacking of more than two multi-layer chips, thereby realizing the multi-layer stacking of chips with higher heat dissipation chip requirements. , While ensuring the heat dissipation effect of the chip, the integration degree of the packaging structure 20 is effectively improved.
  • FIG. 4 is a schematic structural diagram of the second package structure 20 provided in the present application.
  • the package structure 20 includes a first rewiring layer 21, a first chip 22, a first package body 23, a second rewiring layer 24, a second chip 25, a second package body 26, a third rewiring layer 27, and solder balls 28 .
  • the first package body 23 encapsulates the first chip 22 on the first redistribution layer 21, and the pins 221 on the front side of the first chip 22 are provided on the first redistribution layer 21 and connected to the first redistribution layer 21.
  • the first heat transfer element 41 on the back side of the first chip 22 exposes the surface of the first package body 23.
  • the second rewiring layer 24 is provided on the first package body 23 and electrically connected to the first heat transfer member 41 and the first rewiring layer 21 provided on the back side of the first chip 22.
  • the second package body 26 connects the second
  • the chip 25 is packaged on the second redistribution layer 24, and the pins 251 on the front of the second chip 25 are arranged on the second redistribution layer 24 and connected to the second redistribution layer 24, and are arranged on the back side of the second chip 25
  • the second heat transfer member 42 is exposed on the surface of the second package body 26.
  • the third redistribution layer 27 is provided on the second package body 26 and is electrically connected to the second heat transfer element 42 and the second redistribution layer 24 provided on the back side of the second chip 25, and the solder balls 28 are connected to the first rewiring layer.
  • the wiring layer 21 is electrically connected to the first chip 22 and the second chip 25 through the first rewiring layer 21.
  • the front surfaces of the first chip 22 and the second chip 25 are surfaces provided with pins for transmitting signals
  • the back surface of the first chip 22 is a passive surface disposed opposite to the front surface of the first chip 22.
  • the back surface of the second chip 25 is a passive surface arranged opposite to the front surface of the second chip 25.
  • the package structure 20 of the embodiment of the present application is packaged with two chips.
  • the first heat transfer element 41 is arranged on the back side of the first chip 22, and the first heat transfer element 41 exposes the first package body 23 and the second weight.
  • the wiring layer 24 is connected, and the second heat transfer member 42 is provided on the back side of the second chip 25, and the second heat transfer member 42 is exposed to the second package body 26 to be connected to the third redistribution layer 27.
  • the heat of the first chip 22 and the second chip 25 is transferred to the second redistribution layer 24 and the third redistribution layer 27 through the first heat transfer member 41 and the second heat transfer member 42, respectively, for heat dissipation, thereby effectively dissipating the first
  • the heat of the first chip 22 and the second chip 25 is conducted out of the package structure 20 from the back, so that the first chip 22 and the second chip 25 have a good heat dissipation effect in the vertical direction, and the first chip 22 and the second chip are improved.
  • the electrical performance of the two chips 25 further improves the electrical performance of the package structure 20.
  • the package structure 20 of the present application solves the heat dissipation problem of the chip in the vertical direction, the package structure 20 can also realize the stacking of more than two multi-layer chips, thereby realizing the multi-layer stacking of chips with higher heat dissipation chip requirements. , While ensuring the heat dissipation effect of the chip, the integration degree of the packaging structure 20 is effectively improved.
  • the first redistribution layer 21 includes a first insulating medium 211, a first metal circuit 212 and a first heat conducting member 213.
  • the first metal circuit 212 and the first heat conducting member 213 are connected and both are arranged in the first insulating medium 211.
  • the first redistribution layer 21 has a top surface 214 and a bottom surface 215 opposite to each other.
  • the top surface 214 and the bottom surface 215 of the first redistribution layer 21 are the top surface and the bottom surface of the first insulating medium 211.
  • the first metal circuit 212 partially exposes the top surface 214 to connect to the pins 221 of the first chip 22, and the first metal circuit 212 also partially exposes the bottom surface 215 to connect to the solder balls 28.
  • the solder balls 28 are connected to the solder balls through the pads 35.
  • the first metal circuit 212 exposed on the bottom surface 215 is connected.
  • the solder balls 28 are used for electrical connection with other electronic components.
  • the first metal line 212 in FIG. 4 has a plurality of separated parts, and this figure is only a cross-sectional view of the position in the figure, and the first metal line 212 is actually connected at other positions.
  • the specific shape of the first metal circuit 212 can be designed as required.
  • first heat-conducting members 213, and the plurality of first heat-conducting members 213 are arranged at intervals and at least partially expose the top surface 214 of the first redistribution layer 21.
  • the surface of the first rewiring layer 21 is flush with the top surface 214, and the first heat conductive member 213 is exposed to the top surface 214 and is connected to the first package body 23 to conduct the first chip 22 to The heat in the first package body 23 is transferred out through the first metal circuit 212, which effectively improves the heat dissipation effect of the first chip 22.
  • the portions of the plurality of first heat conducting members 213 that expose the first redistribution layer 21 protrude from the top surface 214.
  • the implementation form of the first heat conducting member 213 and the solder ball 28 is not limited to the above description.
  • the first chip 22 is a memory chip.
  • the back surface of the first chip 22 is provided with a barrier layer 31, and the barrier layer 31 is connected between the back surface of the first chip 22 and the first heat transfer member 41.
  • the barrier layer 31 is used to isolate the first chip 22 and the first heat transfer element 41 to prevent the metal material in the first heat transfer element 41 from diffusing into the semiconductor material (such as silicon) on the back of the first chip 22 to affect the conductivity of the semiconductor This further affects the electrical performance of the first chip 22, and even causes the first chip 22 to fail.
  • the material of the barrier layer 31 is, for example, silicon nitride.
  • the first chip 22 may also be an active electronic device such as a CPU chip, a radio frequency drive chip, or a chip of another processor.
  • the material of the barrier layer 31 can also be other materials that can prevent the material in the first heat transfer member 41 from diffusing into the first chip 22.
  • the packaging structure 20 further includes a metal body 43.
  • the multiple first heat transfer elements 41 are connected between the barrier layer 31 and the metal body 43 at intervals.
  • a plurality of first heat transfer elements 41 and metal bodies 43 are encapsulated on the back surface of the first chip 22 through a protective layer 44.
  • the protective layer 44 exposes the surface of the first package body 23, and the metal body 43 exposes the protective layer 44 and faces the first chip 22. That is, the first heat transfer element 41 exposes the first package body 23 through the metal body 43 and is connected to the second redistribution layer 24.
  • the metal body 43 may be a thin metal layer or a metal mesh layer.
  • Connecting the plurality of first heat transfer elements 41 through the metal body 43 increases the heat dissipation area of the first chip 22 on the one hand, and on the other hand, the plurality of first heat transfer elements 41 can be connected to the second redistribution layer through the metal body 43.
  • the connection 24 is firmer, so that the first chip 22 has a good heat dissipation effect in the vertical direction, and the electrical performance of the first chip 22 is improved, thereby improving the electrical performance of the packaging structure 20.
  • the metal body 43 is not provided in the package structure 20, and the first heat transfer element 41 is directly connected between the barrier layer 31 and the second redistribution layer 24.
  • the second redistribution layer 24 includes a second insulating medium 241, a second metal circuit 242 and a second heat conducting member 243, and the second metal circuit 242 and the second heat conducting member 243 are connected and both are disposed in the second insulating medium 241.
  • the second metal circuit 242 partially exposes the surface of the second redistribution layer 24 facing away from the first chip 22 and is connected to the pins 251 of the second chip 25, and a part of the second heat conducting member 243 exposes the second redistribution layer 24 facing away from the first chip.
  • the surface of 22 is connected to the second package body 26 to transfer the heat conducted from the second chip 25 to the second package body 26.
  • Another part of the second heat conducting member 243 exposes the surface of the second redistribution layer 24 facing the first chip 22 Connected with the metal body 43 of the first chip 22 to conduct the heat of the first chip 22 to the second metal circuit 242 through the first heat transfer member 41, the metal body 43, and the second heat conduction member 243 and through the second metal circuit 242 Conduction out, so that the first chip 22 has a good heat dissipation effect in the vertical direction, and the electrical performance of the first chip 22 is improved, thereby improving the electrical performance of the packaging structure 20.
  • the second metal circuit 242 in FIG. 4 is only a state of a cross-sectional view of the position in the figure. Of course, in other embodiments, the specific shape of the second metal line 242 can be designed as required.
  • the other part of the second heat conducting member 243 exposes the surface of the second redistribution layer 24 facing the first chip 22 and is connected to the first heat transfer member 41 of the first chip 22 to pass the heat of the first chip 22 through the first heat transfer member 41 And the second heat conducting member 243 are conducted to the second metal circuit 242 and conducted out through the second metal circuit 242.
  • the implementation form of the second heat conducting member 243 is not limited to the above description.
  • the second chip 25 is a CPU chip.
  • a barrier layer 33 is provided on the back surface of the second chip 25, and the barrier layer 33 is connected between the back surface of the second chip 25 and the second heat transfer element 42.
  • the barrier layer 33 is used to isolate the second chip 25 and the second heat transfer element 42 to prevent the metal material in the second heat transfer element 42 from diffusing into the semiconductor material (such as silicon) on the back of the second chip 25 to affect the conductivity of the semiconductor This further affects the electrical performance of the second chip 25, and even causes the second chip 25 to fail.
  • the material of the barrier layer 33 is, for example, silicon nitride.
  • the second chip 25 may also be an active electronic device such as a memory chip, a radio frequency drive chip, or a chip of another processor.
  • the material of the barrier layer 33 can also be other materials that can prevent the material in the second heat transfer member 42 from diffusing into the second chip 25.
  • the end of the second heat transfer element 42 away from the barrier layer 33 is connected with a metal body 45.
  • the plurality of second heat transfer elements 42 and the metal body 45 are encapsulated on the back surface of the second chip 25 through a protective layer 46.
  • the protective layer 46 exposes the surface of the second package body 26, and the metal body 45 exposes the protective layer 46 and faces the second chip 25. That is, the second heat transfer element 42 exposes the second package body 26 through the metal body 45 and is connected to the third redistribution layer 27.
  • the metal body 45 may be a thin metal layer or a metal mesh layer. Connecting the plurality of second heat transfer elements 42 through the metal body 45 on the one hand increases the heat dissipation area of the second chip 25, on the other hand, the plurality of second heat transfer elements 42 can be connected to the third redistribution layer through the metal body 45. 27 is connected more firmly, so that the second chip 25 has a good heat dissipation effect in the vertical direction, and the electrical performance of the second chip 25 is improved, thereby improving the electrical performance of the packaging structure 20.
  • the metal body 45 is not provided in the package structure 20, and the second heat transfer element 42 is directly connected between the barrier layer 33 and the third redistribution layer 27.
  • the package structure 20 further includes a first connecting pillar 216, the first connecting pillar 216 is provided in the first package body 23, both ends are connected to the first redistribution layer 21 and the second redistribution layer 24, and are connected to the first redistribution layer 21 and the second redistribution layer 24 respectively.
  • the first metal line 212 and the second metal line 242 in the redistribution layer 21 and the second redistribution layer 24 are in contact.
  • the parts of the first metal circuit and the second metal circuit 242 connected to the first connection pillar 216 expose the top surface 214 and the surface of the second redistribution layer 24 facing the first connection pillar 216 to facilitate electrical connection with the first connection pillar 216 .
  • the first connecting pillar 216 is used to connect the first metal circuit 212 and the second metal circuit 242, and at the same time can conduct the heat transferred from the first chip 22 to the first package body 23 to other parts, or to connect the second metal circuit 242 to other parts.
  • the heat is transferred to the first metal circuit 212 to further improve the heat dissipation effect of the package structure 20.
  • the third redistribution layer 27 includes a third insulating medium 271, a third metal circuit 272 and a third heat conductive member 273, and the third metal circuit 272 and the third heat conductive member 273 are connected and are both disposed in the third insulating medium 271.
  • the third heat conducting member 273 exposes the surface of the third redistribution layer 27 facing the second chip 25, and a part is connected to the second package body 26 to conduct heat from the second chip 25 to the second package body 26, and a part is through metal
  • the body 45 is connected to the second heat transfer member 42 to transfer the heat of the second chip 25 from the back side through the second heat transfer member 42 so that the second chip 25 has a good heat dissipation effect in the vertical direction and improves
  • the electrical performance of the second chip 25 is improved, and the electrical performance of the package structure 20 is improved.
  • the surface of the third redistribution layer 27 facing away from the second chip 25 is provided with a connection interface 29.
  • the third metal wire partly exposes the surface of the third redistribution layer 27 facing away from the second chip 25, and a part is used to connect with the connection interface 29.
  • the other part is used to transfer the heat of the second chip 25 to the outside, so as to improve the heat dissipation effect of the packaging structure 20.
  • the arrangement of the third metal line 272 and the connection interface 29 in FIG. 3 is only one of the methods listed in this embodiment. Of course, in other embodiments, the specific shapes of the third metal line 272 and the connection interface 29 can be designed as required.
  • the package structure 20 includes a second connection pillar 244, the second connection pillar 244 is provided in the second package body 26, the two ends are respectively connected to the second rewiring layer 24 and the third rewiring layer 27, and the second rewiring layer
  • the second metal line 242 and the third metal line 272 in the wiring layer 24 and the third redistribution layer 27 are in contact.
  • the parts of the second metal line 242 and the third metal line 272 connected to the second connection pillar 244 expose the surface of the second rewiring layer 24 and the third rewiring layer 27 facing the second connection pillar 244, and the second connection pillar 244 is used for
  • the second metal circuit 242 and the third metal circuit 272 are connected to realize heat transfer, and at the same time, the heat transferred from the second chip 25 to the second package body 26 can be conducted to other parts, and the heat dissipation effect of the package structure 20 is further improved.
  • the heat transfer structure (the first heat transfer member 213 or the first heat transfer The component 41) is connected to the back surface of the first chip 22, and conducts the heat dissipated by the first chip 22 to the outside through the heat-conducting structure (the conduction path can be one side of the first redistribution layer 21, or through conduction to the first chip 22 (the surface of the first package body 23 facing away from the first rewiring layer 21).
  • the heat-conducting structure is connected to the back of the second chip 25, and the second chip 25 is distributed through the heat-conducting structure
  • the heat is conducted to the outside (the path of conduction may be one side of the second redistribution layer 24, or it may be conducted to the surface of the second package body 26 of the second chip 25 away from the second redistribution layer 24).
  • FIG. 5 is a schematic flowchart of a manufacturing method of the packaging structure 20 shown in FIG. 2.
  • the first method for preparing the package structure 20 includes the following S110-S150.
  • the first redistribution layer 21 includes a first insulating medium 211 and a first insulating medium 211 built in Metal line 212.
  • the first insulating medium 211 and the first metal circuit 212 may be formed by a patterning process, so that a part of the first metal circuit 212 of the first redistribution layer 21 is exposed and a part of the bottom surface 215 of the first redistribution layer 21 is exposed.
  • the top surface 214 of the first rewiring layer 21 may be formed by a patterning process, so that a part of the first metal circuit 212 of the first redistribution layer 21 is exposed and a part of the bottom surface 215 of the first redistribution layer 21 is exposed.
  • the first insulating medium 211 may be an insulating resin material, such as benzocyclobutene (BCB) or polyimide (PI), etc., formed by patterning processes such as exposure, development, and curing.
  • the first metal circuit 212 may be formed by first forming a metal thin film layer by a deposition process, a sputtering process or an electroplating process, and then patterning the metal thin film layer by a patterning process such as etching.
  • the material of the first metal circuit 212 may include conductive materials such as metallic copper and metallic aluminum. It can be understood that the middle part and the two side parts of the first metal circuit 212 in FIG. 6 are separated. This figure is only a cross-sectional view of the position in the figure, and the first metal circuit 212 is actually connected in other positions.
  • the specific shape of the first metal circuit 212 can be designed as required.
  • the first heat conduction member 213 is formed at the same time, so that the first heat conduction member 213 is connected to the first metal circuit 212 and is at least partially exposed on the top surface 214 of the first redistribution layer 21.
  • the manufacturing process of the first heat-conducting member 213 is the same as that of the first metal circuit 212, and the material of the first heat-conducting member 213 is also the same as that of the first metal circuit 212. It is understandable that the first heat-conducting member 213 is embedded in the first rewiring layer 21, that is, the first heat-conducting member 213 does not occupy additional space, and the size of the packaging structure 20 will not change due to the addition of the first heat-conducting member 213. Big.
  • the first heat conducting member 213 is formed at the same time as the first rewiring layer 21 is formed, which reduces the manufacturing process, improves the production efficiency of the packaging structure 20, and reduces the production cost of the packaging structure 20. Of course, in other embodiments, the portion of the first rewiring layer 21 exposed by the plurality of first heat conducting members 213 protrudes from the top surface 214 of the first rewiring layer 21.
  • a first connection pillar 216 is formed on the first redistribution layer 21. Specifically, a first connecting pillar 216 is formed on the first metal line 212 exposing the top surface 214 of the first redistribution layer 21, so that the first connecting pillar 216 and the first metal line 212 are connected.
  • the specific forming process of the first connecting pillar 216 includes glue coating, photolithography, development and electroplating.
  • the material of the first connecting pillar 216 is the same as that of the first metal circuit 212.
  • the first connecting pillar 216 is used to connect the first metal line 212 and the second metal line 242 of the second rewiring formed in the subsequent process, and at the same time, it can conduct the heat of the first metal line 212 to other parts, further improving the package.
  • the heat dissipation effect of the structure 20 is used to connect the first metal line 212 and the second metal line 242 of the second rewiring formed in the subsequent process, and at the same time, it can conduct the heat of the first metal line 212 to other parts, further improving the package. The heat dissipation effect of the structure 20.
  • a barrier layer 31 is formed on the back of the first chip 22, and then the barrier layer 31 faces away from the first chip 22.
  • the adhesive layer 32 is pasted on the surface, and then the back of the first chip 22 faces the top surface 214 and is fixed to the top surface 214 by the adhesive layer 32, and is connected to the first heat conducting member 213 exposed on the top surface 214, so that the first chip 22
  • the back side of 22 is connected to the first metal circuit 212 through the first heat-conducting member 213, so as to transfer the heat of the first chip 22 from the back side to the first metal circuit 212 via the first heat-conducting member 213, and finally out through the first metal circuit 212, Therefore, the heat of the first chip 22 is effectively discharged from the back side, so that the first chip 22 has a good heat dissipation effect in the vertical direction, and the electrical performance of the first chip 22 is improved, thereby improving the electrical performance of the package structure 20
  • the first chip 22 in this embodiment is, for example, a memory chip.
  • the barrier layer 31 is used to isolate the first chip 22 and the first heat-conducting element 213.
  • the barrier layer 31 can effectively prevent the first heat-conducting element 213 is diffused in the first chip 22 to prevent the metal material in the first heat-conducting member 213 from diffusing into the semiconductor material (such as silicon) on the back of the first chip 22 through the adhesive layer 32 to affect the conductivity of the semiconductor, thereby affecting the first
  • the electrical performance of the chip 22 even causes the first chip 22 to fail.
  • the material of the barrier layer 31 is, for example, silicon nitride.
  • the adhesive layer 32 is used to fix the first chip 22 on the first redistribution layer 21, so that when the first package 23 encapsulates the first chip 22 on the first redistribution layer 21, the first chip 22 will not The deviation occurs during the packaging process, and the quality of the finished product of the packaging structure 20 is improved.
  • the first chip 22 may also be an active electronic device such as a CPU chip, a radio frequency drive chip, or other processor chips.
  • the material of the barrier layer 31 can also be other materials that can prevent the material in the first heat conducting member 213 from diffusing into the first chip 22.
  • the part of the first rewiring layer 21 exposed by the plurality of first heat-conducting members 213 can also be directly held against the isolation layer 31.
  • the first chip 22 is packaged to the first redistribution layer 21 through the first package body 23. While the first package body 23 encapsulates the first chip 22, The first connecting pillar 216 is packaged in the first package body 23, and then the surface of the first package body 23 facing away from the first redistribution layer 21 is polished, so that the pins 221 on the front side of the first chip 22 and the first The connecting pillar 216 exposes the surface of the first package body 23. The pins 221 of the first chip 22 and the first connecting pillars 216 expose the surface of the first package body 23 so that the first chip 22 and the first connecting pillars 216 are electrically connected to other structures.
  • the material of the first package body 23 is an insulating resin material, for example, an epoxy resin material.
  • a second redistribution layer 24 is fabricated on the surface of the first package body 23 facing away from the first redistribution layer 21.
  • the second redistribution layer 24 includes a second insulating medium 241 and a The second metal line 242 of the insulating medium 241.
  • the second insulating medium 241 and the second metal circuit 242 can be formed by a patterning process, so that a part of the second metal circuit 242 of the second redistribution layer 24 is exposed to the second redistribution layer 24 facing the first chip 22.
  • the surface is connected to the pins 221 of the first chip 22 and the first connecting pillars 216, and a part of the surface of the second redistribution layer 24 facing away from the first chip 22 is exposed.
  • the manufacturing process of the second rewiring layer 24 in this embodiment is the same as the manufacturing process of the first rewiring layer 21.
  • the material of the second insulating medium 241 is the same as the material of the first insulating medium 211, and the material of the second metal line 242 and the first metal line 212 are the same.
  • the second metal circuit 242 in FIG. 9 is only a state of a cross-sectional view of the position in the figure. Of course, in other embodiments, the specific shape of the second metal line 242 can be designed as required.
  • the manufacturing process of the second redistribution layer 24 may be different from the manufacturing process of the first redistribution layer 21, and the materials may also be different.
  • a second heat conducting member 243 is formed at the same time, so that the second heat conducting member 243 is connected to the second metal circuit 242 and is at least partially exposed on the second redistribution layer 24 facing away from the first chip 22 s surface.
  • there are a plurality of second heat conducting members 243 and the plurality of second heat conducting members 243 are arranged at intervals, and the plurality of second heat conducting members 243 are exposed on the surface of the second redistribution layer 24 facing away from the second redistribution layer 24. The flush of the first chip 22.
  • the manufacturing process of the second heat conducting member 243 is the same as the manufacturing process of the second metal circuit 242, and the material of the second heat conducting member 243 is also the same as that of the second metal circuit 242. It is understandable that the second heat-conducting member 243 is embedded in the second rewiring layer 24, that is, the second heat-conducting member 243 does not occupy additional space, and the size of the packaging structure 20 will not change due to the addition of the second heat-conducting member 243. Big.
  • the second heat conducting member 243 is formed at the same time as the second rewiring layer 24 is formed, which reduces the manufacturing process, improves the production efficiency of the packaging structure 20, and reduces the production cost of the packaging structure 20.
  • the portion of the second rewiring layer 24 exposed by the plurality of second heat conducting members 243 protrudes from the surface of the second rewiring layer 24 facing away from the first chip 22.
  • a second connection pillar 244 is formed on the second redistribution layer 24.
  • a second connecting pillar 244 is formed on the second metal line 242 of the second rewiring layer 24 that faces away from the first chip 22, so that the second connecting pillar 244 is connected to the second metal line 242.
  • the specific forming process of the second connecting pillar 244 includes glue coating, photolithography, development and electroplating.
  • the material of the second connecting pillar 244 is the same as that of the second metal circuit 242.
  • the second connecting pillar 244 is used to connect the second metal line 242 to the third metal line of the third rewiring formed in the subsequent process, and at the same time, it can conduct the heat of the second metal line 242 to other parts, further improving the package structure. 20's heat dissipation effect.
  • S140 Connect the second chip 25 to the second redistribution layer 24 so that the back of the second chip 25 faces the second redistribution layer 24, and the second metal circuit 242 is connected through the second heat conducting member 243, wherein the second The front surface of the chip 25 is used to transmit signals, and the back surface of the second chip 25 is a passive surface arranged opposite to the front surface of the second chip 25.
  • a barrier layer 33 is formed on the back of the second chip 25, and then the barrier layer 33 is pasted on the surface of the barrier layer 33 facing away from the second chip 25.
  • the back side of the second chip 25 faces the surface of the second redistribution layer 24 away from the first chip 22 and is fixed to the surface of the second redistribution layer 24 away from the first chip 22 by the adhesive layer 34 And connected to the second heat conducting member 243 exposing the surface of the second rewiring layer 24 facing away from the first chip 22, so that the back of the second chip 25 is connected to the second metal circuit 242 through the second heat conducting member 243 to connect the The heat of the two chips 25 is transferred from the back to the second metal circuit 242 through the second heat conducting member 243, and finally is exported through the second metal circuit 242, thereby effectively dissipating the heat of the second chip 25 from the back, so that the second chip 25 is In the vertical direction, it has a good heat dissipation effect, improves the electrical performance of the second chip 25, and further improves the electrical performance of the package structure 20.
  • the second chip 25 in this embodiment is a CPU chip.
  • the barrier layer 33 is used to isolate the second chip 25 and the second heat-conducting element 243.
  • the barrier layer 34 can effectively prevent the second heat-conducting element 243 is diffused in the second chip 25 to prevent the metal material in the second heat-conducting member 243 from diffusing into the semiconductor material (such as silicon) on the back of the second chip 25 through the adhesive layer 34 to affect the conductivity of the semiconductor, thereby affecting the second
  • the electrical performance of the chip 25 may even cause the second chip 25 to fail.
  • the material of the barrier layer 33 is, for example, silicon nitride.
  • the adhesive layer 34 is used to fix the second chip 25 on the second redistribution layer 24, so that when the second package body 26 encapsulates the second chip 25 on the second redistribution layer 24, the second chip 25 will not The deviation occurs during the packaging process, and the quality of the finished product of the packaging structure 20 is improved.
  • the second chip 25 may also be an active electronic device such as a memory chip, a radio frequency drive chip, or other processor chips.
  • the material of the barrier layer 33 can also be other materials that can prevent the material in the second heat conducting member 243 from diffusing into the second chip 25.
  • the part of the second rewiring layer 24 exposed by the plurality of second heat conducting members 243 can also be directly against the isolation layer 34.
  • the second chip 25 is packaged to the second redistribution layer 24 through the second package body 26. While the second package body 26 encapsulates the second chip 25, it also The second connecting pillar 244 is packaged in the second package body 26, and then the surface of the second package body 26 facing away from the second redistribution layer 24 is polished, so that the pins 251 on the front side of the second chip 25 and the second The connecting pillar 244 exposes the surface of the second package body 26. The pins 251 and the second connecting pillars 244 of the second chip 25 expose the surface of the second package body 26 so that the second chip 25 and the second connecting pillars 244 are electrically connected to other structures.
  • the material of the second package body 26 is the same as the material of the first package body 23.
  • a third redistribution layer 27 is formed on the second package body 26, and solder balls 28 are formed on the third redistribution layer 27.
  • a third redistribution layer 27 is formed on the back surface of the second package body 26 facing away from the second chip 25.
  • the third redistribution layer 27 includes a third insulating medium 271 and a third insulating medium 271.
  • the third insulating medium 271 and the third metal line 272 can be formed by a patterning process, so that a part of the third metal line 272 of the third redistribution layer 27 exposes the third redistribution layer 27 facing the second chip 25.
  • the surface is connected to the pins 251 of the second chip 25 and the second connecting pillars 244, and a part of the surface of the third rewiring facing away from the second chip 25 is exposed.
  • the manufacturing process of the third rewiring layer 27 in this embodiment is the same as the manufacturing process of the first rewiring layer 21.
  • the material of the third insulating medium 271 and the material of the third insulating medium 271 are the same, and the material of the third metal line 272 and the first metal line 212 are the same.
  • the arrangement of the third metal line 272 and the solder balls 28 in FIG. 11 is only one of the examples listed in this embodiment. Of course, in other embodiments, the specific shape of the third metal line 272 and the solder ball 28 can be designed as required.
  • the manufacturing process of the third redistribution layer 27 may be different from the manufacturing process of the first redistribution layer 21, and the materials may also be different.
  • the carrier board 50 is removed, and a solder ball 28 is formed on the surface of the third redistribution layer 27 facing away from the second chip 25, so that the solder ball 28 is connected to the third metal circuit 272 that exposes the third wiring layer, specifically, the solder ball 28
  • the pad 35 is connected to the third metal line 272 that exposes the surface of the third redistribution layer 27 facing away from the second chip 25.
  • the third rewiring layer 27 is not only used to realize the electrical connection between the second metal line 242 and the third metal line 272, but also transfers the heat from the first chip 22 and the second chip 25 to the third metal line 272 through the solder balls 28. Pass to the outside world.
  • the solder balls 28 are used for electrical connection with other electronic components.
  • connection interface 29 is formed on the bottom surface 215 of the first redistribution layer 21, and the connection interface 29 is connected to the first metal circuit 212 partially exposed on the bottom surface 215 of the first redistribution layer 21 to form the package structure 20, and the other part exposes the first redistribution.
  • the first metal circuit 212 on the bottom surface 215 of the wiring layer 21 is used to conduct the heat of the first chip 22 and the second chip 25 to the outside, so as to improve the heat dissipation effect of the package structure 20.
  • the connection interface 29 is used for connecting with other electronic modules and realizing the grounding of the package structure 20.
  • the setting method of the connection interface 29 is not limited to that shown in FIG. 11.
  • the first chip 22 is connected to the first redistribution layer 21, and the back of the first chip 22 is connected to the first metal circuit 212 of the first redistribution layer 21 through the first heat conducting member 213,
  • the second chip 25 is connected to the second redistribution layer 24, and the back of the second chip 25 is connected to the second metal circuit 242 of the second redistribution layer 24 through the second heat conducting member 243 to connect the first chip 22 and the second redistribution layer 24.
  • the heat of the two chips 25 is transferred from the back to the first metal circuit 212 and the second metal circuit 242 through the first heat conducting member 213 and the second heat conducting member 243, and finally is discharged through the first metal circuit 212 and the second metal circuit 242, thereby effectively
  • the heat of the first chip 22 and the second chip 25 is discharged from the back side, so that the first chip 22 and the second chip 25 have a good heat dissipation effect in the vertical direction, and the first chip 22 and the second chip 25 are improved.
  • the electrical performance of the package structure 20 is further improved.
  • the package structure 20 can also realize the stacking of more than two chips of multi-layer chips, thereby realizing the multi-layer stacking of chips with higher heat dissipation chip requirements. While ensuring the heat dissipation effect of the chip, the integration degree of the packaging structure 20 is effectively improved.
  • FIG. 12 is a schematic flowchart of a manufacturing method of the packaging structure 20 shown in FIG. 4. As shown in FIG. 12, the manufacturing method of the second package structure 20 includes the following S210-S250.
  • the first redistribution layer 21 includes a first insulating medium 211 and a first insulating medium 211 built in Metal line 212.
  • the first insulating medium 211 and the first metal circuit 212 may be formed by a patterning process, so that a part of the first metal circuit 212 of the first redistribution layer 21 is exposed and a part of the bottom surface 215 of the first redistribution layer 21 is exposed.
  • the top surface 214 of the first rewiring layer 21 may be formed by a patterning process, so that a part of the first metal circuit 212 of the first redistribution layer 21 is exposed and a part of the bottom surface 215 of the first redistribution layer 21 is exposed.
  • the first insulating medium 211 may be an insulating resin material, such as benzocyclobutene (BCB) or polyimide (PI), etc., formed by patterning processes such as exposure, development, and curing.
  • the first metal circuit 212 may be formed by first forming a metal thin film layer by a deposition process, a sputtering process or an electroplating process, and then patterning the metal thin film layer by a patterning process such as etching.
  • the material of the first metal circuit 212 may include conductive materials such as metallic copper and metallic aluminum. It can be understood that the first metal line 212 in FIG.
  • first metal line 212 has a plurality of separated parts, and this figure is only a cross-sectional view of the position in the figure, and the first metal line 212 is actually connected at other positions.
  • the specific shape of the first metal circuit 212 can be designed as required.
  • the first heat conduction member 213 is formed at the same time, so that the first heat conduction member 213 is connected to the first metal circuit 212 and is at least partially exposed on the top surface 214 of the first redistribution layer 21.
  • the manufacturing process of the first heat-conducting member 213 is the same as that of the first metal circuit 212, and the material of the first heat-conducting member 213 is also the same as that of the first metal circuit 212. It is understandable that the first heat-conducting member 213 is embedded in the first rewiring layer 21, that is, the first heat-conducting member 213 does not occupy additional space, and the size of the packaging structure 20 will not change due to the addition of the first heat-conducting member 213. Big.
  • the first heat conducting member 213 is formed at the same time as the first rewiring layer 21 is formed, which reduces the manufacturing process, improves the production efficiency of the packaging structure 20, and reduces the production cost of the packaging structure 20. Of course, in other embodiments, the portion of the first rewiring layer 21 exposed by the plurality of first heat conducting members 213 protrudes from the top surface 214 of the first rewiring layer 21.
  • a first connection pillar 216 is formed on the first redistribution layer 21. Specifically, a first connecting pillar 216 is formed on the first metal line 212 partially exposed on the top surface 214 of the first redistribution layer 21, so that the first connecting pillar 216 is connected to the first metal line 212.
  • the specific forming process of the first connecting pillar 216 includes glue coating, photolithography, development and electroplating.
  • the material of the first connecting pillar 216 is the same as that of the first metal circuit 212.
  • the first connecting pillar 216 is used to connect the first metal line 212 and the second metal line 242 of the second rewiring formed in the subsequent process, and at the same time, it can conduct the heat of the first metal line 212 to other parts, further improving the package.
  • the heat dissipation effect of the structure 20 is used to connect the first metal line 212 and the second metal line 242 of the second rewiring formed in the subsequent process, and at the same time, it can conduct the heat of the first metal line 212 to other parts, further improving the package. The heat dissipation effect of the structure 20.
  • S220 Package the first chip 22 to the first redistribution layer 21 through the first package body 23, so that the back of the first chip 22 faces away from the first redistribution layer 21, and is connected to the first redistribution layer 21 through the first heat transfer member 41.
  • FIGS. 14-15 Before the first chip 22 is packaged to the first redistribution layer 21 through the first package body 23, a barrier layer 31 is formed on the back of the first chip 22, and the barrier layer 31 faces away from the A plurality of spaced first heat transfer elements 41 are formed on the surface of the first chip 22, and a protective layer 44 is formed on the surface of the barrier layer 31 facing away from the first chip 22.
  • the protective layer 44 covers the first heat transfer element 41.
  • a metal body 43 is formed in 44, and the metal body 43 is connected to the plurality of first heat transfer elements 41, and the part of the metal body 43 away from the first heat transfer body exposes the protective layer 44.
  • the first chip 22 is a memory chip.
  • the first heat transfer member 41 is, for example, a copper pillar or other metal pillar, and may be formed by a process such as electroplating.
  • the metal body 43 may be a thin metal layer or a metal mesh layer.
  • the material of the protective layer 44 is an insulating resin material, for example, one of polyimide, benzocyclobutene, and epoxy resin.
  • the first chip 22 may also be an active electronic device such as a CPU chip, a radio frequency drive chip, or other processor chips.
  • the first heat transfer member 41 may also have other shapes.
  • the heat of the first chip 22 is transferred from the back side through the plurality of first heat transfer elements 41, and the plurality of first heat transfer elements 41 can ensure the effective transfer of heat.
  • the metal body 43 transfers the plurality of first heat transfer elements.
  • the connection of the heat element 41 increases the heat dissipation area of the first chip 22.
  • the plurality of first heat transfer elements 41 can be more firmly connected to the subsequently formed heat conduction element through the metal body 43, so that the first chip 22 can be connected more firmly. It has a good heat dissipation effect in the vertical direction, improves the electrical performance of the first chip 22, and further improves the electrical performance of the package structure 20.
  • the barrier layer 31 is used to isolate the first chip 22 and the first heat transfer element 41 to prevent the metal material in the first heat transfer element 41 from diffusing into the semiconductor material (such as silicon) on the back of the first chip 22 to affect the conductivity of the semiconductor This further affects the electrical performance of the first chip 22, and even causes the first chip 22 to fail.
  • the material of the barrier layer 31 is, for example, silicon nitride. Of course, in other embodiments, the material of the barrier layer 31 can also be other materials that can prevent the material in the first heat transfer element 41 from diffusing into the first chip 22.
  • a barrier layer 31 is formed on the back of the first chip 22, and the barrier layer 31 faces away from the first rewiring layer 21.
  • a plurality of spaced first heat transfer elements 41 are formed on the surface of a chip 22, and the pins 221 of the first chip 22 are connected with the first metal circuit 212 partially exposed on the top surface 214, and then the first package body 23 is used to encapsulate the first heat transfer element 41.
  • the chip 22 grinds the surface of the first package body 23 facing away from the first redistribution layer 21 so that the surface of the plurality of first heat transfer elements 41 facing away from the first chip 22 exposes the surface of the first package body 23.
  • the heat of the first chip 22 is transferred from the back side through the plurality of first heat transfer elements 41 formed on the back side of the first chip 22.
  • the plurality of first heat transfer elements 41 can ensure effective heat transfer, so that the first chip 22 has a good heat dissipation effect in the vertical direction, improves the electrical performance of the first chip 22, and further improves the electrical performance of the package structure 20.
  • a barrier layer 31 is formed on the back of the first chip 22, and the barrier layer 31 faces away from the first rewiring layer 21.
  • a plurality of spaced first heat transfer elements 41 are formed on the surface of a chip 22, and a protective layer 44 is formed on the surface of the barrier layer 31 facing away from the first chip 22. The protective layer 44 covers the first heat transfer element 41.
  • the end of the component 41 away from the first chip 22 exposes the protective layer 44, connects the pins 221 of the first chip 22 with the first metal circuit 212 partially exposed on the top surface 214, and then encapsulates the first chip 22 with the first package body 23
  • the surface of the first package body 23 facing away from the first redistribution layer 21 is polished, so that the surface of the protective layer 44 facing away from the first chip 22 exposes the surface of the first package body 23.
  • the heat of the first chip 22 is transferred from the back side through the plurality of first heat transfer elements 41 formed on the back side of the first chip 22.
  • the plurality of first heat transfer elements 41 can ensure effective heat transfer, so that the first chip 22 has a good heat dissipation effect in the vertical direction, improves the electrical performance of the first chip 22, and further improves the electrical performance of the package structure 20.
  • a plurality of first heat transfer elements 41 are fixed by the protective layer 44, so that the first heat transfer elements 41 will not be skewed during the process of packaging the first chip 22, thereby further ensuring The heat dissipation effect of the first chip 22.
  • the first heat transfer member 41 is formed after the first package body 23 encapsulates the first chip 22. Specifically, before the first chip 22 is packaged to the first redistribution layer 21 through the first package body 23, a barrier layer 31 is formed on the back of the first chip 22, and the pins 221 and parts of the first chip 22 are exposed to the top surface. 214 is connected to the first metal circuit 212, and then the first chip 22 is packaged with the first package body 23. A plurality of spaced openings are formed on the first package body 23 to expose the barrier layer 31 on the back of the first chip 22. The first heat transfer member 41 is formed in the middle.
  • the first heat transfer member 41 is formed after the first package body 23 encapsulates the first chip 22. Specifically, before the first chip 22 is packaged to the first redistribution layer 21 through the first package body 23, a barrier layer 31 is formed on the back of the first chip 22, and the pins 221 and parts of the first chip 22 are exposed to the top surface. 214 is connected to the first metal circuit 212, and then the first chip 22 is packaged with the first package body 23, a first opening is formed in the first package body 23, and a plurality of spaced second openings are formed on the bottom wall of the first opening. The two openings expose the back side of the first chip 22, and the first heat transfer element 41 is formed in the first opening and the second opening.
  • the heat dissipation surface of the first heat transfer element 41 is enlarged, so that the first chip 22 has a good heat dissipation effect in the vertical direction, and the electrical performance of the first chip 22 is improved. In turn, the electrical performance of the packaging structure 20 is improved.
  • the first package body 23 encapsulates the first connecting pillars 216 at the same time, and then the first package body 23 is reversed to the first redistribution.
  • the surface of the layer 21 is polished so that the first connecting pillar 216 is partially exposed to the surface of the first package body 23.
  • the first connecting pillar 216 exposes the surface of the first package body 23 to facilitate electrical connection with other structures.
  • the material of the first package body 23 is an insulating resin material, for example, an epoxy resin material.
  • a second redistribution layer 24 is formed on the surface of the first package body 23 facing away from the first chip 22.
  • the second redistribution layer 24 includes a second insulating medium 241 and a second insulating medium. 241 of the second metal line 242.
  • the second insulating medium 241 and the second metal circuit 242 can be formed by a patterning process, so that a part of the first metal circuit 212 of the second redistribution layer 24 is exposed to the second redistribution layer 24 facing the first chip 22. On the surface, a part of the surface of the second redistribution layer 24 facing away from the first chip 22 is exposed.
  • the manufacturing process of the second rewiring layer 24 in this embodiment is the same as the manufacturing process of the first rewiring layer 21, and the materials used are also the same. It can be understood that the second metal circuit 242 in FIG. 16 is only a state of a cross-sectional view of the position in the figure. Of course, in other embodiments, the specific shape of the second metal line 242 can be designed as required.
  • the second heat conduction member 243 is formed at the same time, so that the second heat conduction member 243 is connected to the second metal circuit 242 and is at least partially exposed on the second redistribution layer 24 toward and away from the first The surface of the chip 22.
  • there are a plurality of second heat conducting elements 243 and the surface of the plurality of second heat conducting elements 243 exposed to the second redistribution layer 24 is flush with the surface of the second redistribution layer 24 facing the first chip 22.
  • the second heat conduction member 243 exposing the surface of the second rewiring layer 24 facing the first chip 22 is connected to the metal body 43.
  • the second heat conduction member 243 is used to connect the first heat transfer member 41 through the metal body 43, thereby connecting the first chip 22
  • the heat transferred to the first heat transfer member 41 is transferred to the second metal circuit 242 through the second heat conduction member 243 and conducted out through the second metal circuit 242, so that the first chip 22 has good heat dissipation in the vertical direction.
  • the electrical performance of the first chip 22 is improved, and thus the electrical performance of the package structure 20 is improved.
  • the manufacturing process of the second heat conducting member 243 is the same as the manufacturing process of the second metal circuit 242, and the material of the second heat conducting member 243 is also the same as that of the second metal circuit 242. It is understandable that the second heat-conducting member 243 is embedded in the second rewiring layer 24, that is, the second heat-conducting member 243 does not occupy additional space, and the size of the packaging structure 20 will not change due to the addition of the second heat-conducting member 243. Big. In addition, the second heat conducting member 243 is formed at the same time as the second rewiring layer 24 is formed, which reduces the manufacturing process, improves the production efficiency of the packaging structure 20, and reduces the production cost of the packaging structure 20.
  • the portion of the second redistribution layer 24 exposed by the plurality of second heat conduction members 243 protrudes from the surface of the second redistribution layer 24.
  • the second heat conducting member 243 exposing the surface of the second redistribution layer 24 facing the first chip 22 is connected to the first heat transfer member 41.
  • a second connection pillar 244 is formed on the second redistribution layer 24.
  • a second connecting pillar 244 is formed on the second metal line 242 partially exposing the surface of the second redistribution layer 24 facing away from the first chip 22, so that the second connecting pillar 244 is connected to the second metal line 242.
  • the specific forming process of the second connecting pillar 244 includes glue coating, photolithography, development and electroplating.
  • the material of the second connecting pillar 244 is the same as that of the second metal circuit 242.
  • the second connecting pillar 244 is used to connect the second metal line 242 to the third metal line 272 of the third rewiring formed in the subsequent process, and at the same time, it can also conduct the heat of the second metal line 242 to other parts, further improving the package.
  • the heat dissipation effect of the structure 20 is used to connect the second metal line 242 to the third metal line 272 of the third rewiring formed in the subsequent process, and at the same time, it can also conduct the heat of the second metal line 242 to other parts, further improving the package. The heat dissipation effect of the structure 20.
  • S240 Package the second chip 25 to the second redistribution layer 24 through the second package body 26, the back of the second chip 25 is opposite to the second redistribution layer 24, and is connected to the second package through the second heat transfer element 42
  • a barrier layer 33 is formed on the back of the second chip 25, and the barrier layer 33 faces away from the second chip.
  • a plurality of spaced second heat transfer elements 42 are formed on the surface of 25.
  • a protective layer 46 is formed on the surface of the barrier layer 33 facing away from the second chip 25. The protective layer 46 covers the second heat transfer element 42 and is formed in the protective layer 46.
  • the metal body 45 is connected to the plurality of second heat transfer elements 42, and a part of the metal body 45 away from the second heat transfer element 42 exposes the protective layer 46.
  • the second chip 25 is a CPU chip.
  • the second heat transfer member 42 is, for example, a copper pillar or other metal pillar, and may be formed by a process such as electroplating.
  • the metal body 45 may be a thin metal layer or a metal mesh layer.
  • the material of the protective layer 46 is an insulating resin material, for example, one of polyimide, benzocyclobutene, epoxy resin, and the like.
  • the second chip 25 may also be an active electronic device such as a memory chip, a radio frequency drive chip, or a chip of another processor.
  • the second heat transfer member 42 may also have other shapes.
  • the second heat conducting member 243 which exposes the surface of the second rewiring layer 24 facing away from the first chip 22, is connected to the second package body 26 to conduct heat in the second package body 26 through the second metal circuit 242 To the outside, the heat dissipation effect of the second chip 25 is effectively improved.
  • the heat of the second chip 25 is also transferred from the back through the plurality of second heat transfer elements 42.
  • the plurality of second heat transfer elements 42 can ensure effective heat transfer.
  • the plurality of second heat transfer elements 42 are connected by the metal body 45. On the one hand, the heat dissipation area of the second chip 25 is increased.
  • the plurality of second heat transfer members 42 can be more firmly connected to the subsequently formed heat conduction member through the metal body 45, so that the second chip 25 is in the vertical direction. It has a good heat dissipation effect, improves the electrical performance of the second chip 25, and further improves the electrical performance of the package structure 20.
  • the plurality of second heat transfer members 42 and the metal body 45 are fixed by the protective layer 46, so that the second heat transfer member 42 and the metal body 45 will not be in the process of packaging the second chip 25. The skew occurs in the second chip 25, thereby further ensuring the heat dissipation effect of the second chip 25.
  • the barrier layer 33 is used to isolate the second chip 25 and the second heat transfer element 42 to prevent the metal material in the second heat transfer element 42 from diffusing into the semiconductor material (such as silicon) on the back of the second chip 25 to affect the conductivity of the semiconductor This further affects the electrical performance of the second chip 25, and even causes the second chip 25 to fail.
  • the material of the barrier layer 33 is, for example, silicon nitride.
  • the material of the barrier layer 33 can also be other materials that can prevent the material in the second heat transfer element 42 from diffusing into the second chip 25.
  • the formation and structure of the second heat transfer element 42 including but not limited to the implementation of the first heat transfer element 41 listed in S220, and the second heat transfer element 42 Any formation method and structure of the second heat transfer element 42 can be combined to form a different solution.
  • the second package body 26 encapsulates the second connecting pillars 244 at the same time, and then the second package body 26 is reversed to the second redistribution.
  • the surface of the layer 24 is polished so that the second connecting pillar 244 is partially exposed to the surface of the second package body 26.
  • the second connecting pillar 244 exposes the surface of the second package body 26 to facilitate electrical connection with other structures.
  • the material of the second package body 26 and the material of the first package body 23 are the same.
  • a third redistribution layer 27 is formed on the back surface of the second package body 26 facing away from the second chip 25.
  • the third redistribution layer 27 includes a third insulating medium 271 and a third insulating medium 271.
  • the third insulating medium 271 and the third metal circuit 272 can be formed by a patterning process, so that a part of the third metal circuit 272 of the third redistribution layer 27 exposes the third redistribution layer 27 facing the second chip 25.
  • the surface is connected to the second connecting pillar 244, and a part of the surface of the third rewiring facing away from the second chip 25 is exposed.
  • the manufacturing process of the third rewiring layer 27 in this embodiment is the same as the manufacturing process of the first rewiring layer 21, and the materials used are also the same. It can be understood that the arrangement of the third metal line 272 in FIG. 18 is only one of the examples listed in this embodiment. Of course, in other embodiments, the specific shape of the third metal line 272 9 can be designed as required.
  • a third heat conduction member 273 is simultaneously formed, so that the third heat conduction member 273 is connected to the third metal circuit 272 and is at least partially exposed on the third redistribution layer 27 toward the second chip 25. surface.
  • the third heat-conducting member 273 is connected to the metal body 45 on the back side of the second chip 25, and the third heat-conducting member 273 is used to connect the second heat-transfer member 42 through the metal body 45 so as to transfer the second heat transfer to the second chip 25
  • the heat of the member 42 is transferred to the third metal circuit 272 through the third heat-conducting member 273 and is conducted out through the third metal circuit 272, so that the second chip 25 has a good heat dissipation effect in the vertical direction, which improves the second chip.
  • the electrical performance of 25 further improves the electrical performance of the package structure 20.
  • the manufacturing process of the third heat-conducting member 273 is the same as the manufacturing process of the third metal circuit 272, and the material of the third heat-conducting member 273 is also the same as the third metal circuit 272. It is understandable that the third heat conduction member 273 is embedded in the third rewiring layer 27, that is, the third heat conduction member 273 does not occupy additional space, and the size of the package structure 20 will not be changed due to the addition of the third heat conduction member 273. Big.
  • the third heat conducting member 273 is formed at the same time as the third rewiring layer 27 is formed, which reduces the manufacturing process, improves the production efficiency of the package structure 20, and reduces the production cost of the package structure 20.
  • the portion of the third redistribution layer 27 exposed by the plurality of third heat conduction members 273 protrudes from the surface of the third redistribution layer 27.
  • the third heat conducting member 273 exposing the surface of the third redistribution layer 27 facing the second chip 25 is connected to the second heat transfer member 42.
  • connection interface 29 is formed on the surface of the third redistribution layer 27 facing away from the second chip 25, and the connection interface 29 is partially exposed to the third metal circuit on the surface of the third redistribution layer 27 facing away from the second chip 25 272 connection, the connection interface 29 is used to connect with other electronic modules and realize the grounding of the package structure 20.
  • the other part of the third metal circuit 272 exposed to the surface of the third redistribution layer 27 facing away from the second chip 25 is used to conduct the heat of the first chip 22 and the second chip 25 to the outside, so as to improve the heat dissipation effect of the package structure 20.
  • the setting method of the connection interface 29 is not limited to that shown in FIG. 18.
  • a solder ball 28 is formed on the surface of the first redistribution layer 21 facing away from the first chip 22. Specifically, the solder ball 28 is connected to the first metal circuit 215 exposing the bottom surface 215 of the first redistribution layer 21 through the pad 35 to form the package structure 20.
  • the solder balls 28 are used for electrical connection with other electronic components, and at the same time, the heat transferred from the first chip 22 and the second chip 25 to the third metal circuit 272 can be transferred to the outside through the solder balls 28. In order to improve the heat dissipation effect of the package structure 20.
  • the arrangement of the solder balls 28 is not limited to that shown in FIG. 18.
  • the first heat transfer element 41 is arranged on the back side of the first chip 22, and the first heat transfer element 41 is exposed to the first package body 23 and connected to the second redistribution layer 24, and
  • the second heat transfer element 42 is provided on the back side of the second chip 25, and the second heat transfer element 42 is exposed to the second package body 26 and connected to the third redistribution layer 27.
  • the heat of the first chip 22 and the second chip 25 is transferred to the second redistribution layer 24 and the third redistribution layer 27 through the first heat transfer member 41 and the second heat transfer member 42, respectively, for heat dissipation, thereby effectively dissipating the first
  • the heat of the first chip 22 and the second chip 25 is conducted out of the package structure 20 from the back, so that the first chip 22 and the second chip 25 have a good heat dissipation effect in the vertical direction, and the first chip 22 and the second chip are improved.
  • the electrical performance of the two chips 25 further improves the electrical performance of the package structure 20.
  • the package structure 20 can also realize the stacking of more than two chips of multi-layer chips, thereby realizing the multi-layer stacking of chips with higher heat dissipation chip requirements. While ensuring the heat dissipation effect of the chip, the integration degree of the packaging structure 20 is effectively improved.
  • the thermal conductive structure is connected to the back of the first chip 22 , And conduct the heat dissipated by the first chip 22 to the outside through the heat-conducting structure (the first heat-conducting member 213 or the first heat-transfer member 41) (the conduction path may be one side of the first redistribution layer 21, or through conduction to the The first chip 22 faces away from the surface of the first package body 23 of the first redistribution layer 21).
  • the heat-conducting structure is connected to the back of the second chip 25, and the second chip 25 is distributed through the heat-conducting structure
  • the heat is conducted to the outside (the path of conduction may be one side of the second redistribution layer 24, or it may be conducted to the surface of the second package body 26 of the second chip 25 away from the second redistribution layer 24).

Abstract

提供一种封装结构(20)及其制备方法和电子设备(100)。所述封装结构(20)包括第一重布线层(21)和第一芯片(22),所述第一重布线层(21)包括第一金属线路(212)和与所述第一金属线路(212)连接的第一导热件(213),所述第一导热件(213)至少部分露出所述第一重布线层(21)的顶面(214),所述第一芯片(22)的背面一侧设于所述顶面(214),并与所述第一导热件(213)连接。提供的所述封装结构(20)具有很好的散热效果。

Description

封装结构及其制备方法和电子设备 技术领域
本申请涉及封装技术领域,尤其涉及一种封装结构及其制备方法和电子设备。
背景技术
随着摩尔定律步伐的放缓,芯片尺寸微缩的成本日益增加,封装在产业链的地位变得更加重要。采用堆叠封装(Package on Package,POP)方案,结合扇出型晶圆级封装(Fan Out Wafer Level Package,FOWLP)技术,可以极大地提高封装结构的集成度,具有显著的收益。但是现有的封装结构中的芯片在垂直方向上散热不良。
发明内容
本申请实施例提供一种封装结构,以提高封装结构的散热效果。
本申请实施例还提供一种封装结构的制备方法和电子设备。
本申请实施例提供一种封装结构,包括第一重布线层和第一芯片,所述第一重布线层包括第一金属线路和与所述第一金属线路连接的第一导热件,所述第一导热件至少部分露出所述第一重布线层的顶面,所述第一芯片的正面用于传递信号,所述第一芯片的背面为与所述第一芯片的正面相背设置的无源面,所述第一芯片的背面一侧设于所述顶面,并与所述第一导热件连接。
本申请实施例所述的封装结构中的第一芯片的背面一侧与第一导热件连接,以将第一芯片的热量从背面经第一导热件传递至第一金属线路,即,将第一芯片的热量从无源面经第一导热件传递至第一金属线路,最后经由第一金属线路导出,从而有效将第一芯片的热量从背面导出,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。
一些实施例中,所述第一芯片的背面设有阻隔层,所述阻隔层连接在所述背面和所述第一导热件之间。阻隔层用于隔离第一芯片和第一导热件,以避免第一导热件中的材料扩散到第一芯片中影响第一芯片的电性能,甚至导致第一芯片失效。阻隔层的材料例如为氮化硅。当然,在其他实施例中,阻隔层的材料还可以是其他可以阻止第一导热件中的材料扩散到第一芯片中的材料。
一些实施例中,所述阻隔层和所述第一导热件之间设有粘接层,所述粘接层将所述第一芯片粘接至所述顶面。粘接层用于将第一芯片固定于顶面上,以在第一封装体将第一芯片封装于第一重布线层上时,第一芯片不会在封装过程中发生偏位,提高了封装结构的成品品质。
一些实施例中,所述封装结构包括第一封装体,所述第一封装体封装于所述第一芯片上,所述第一芯片的正面的引脚露出所述第一封装体。第一芯片的引脚露出第一封装体的表面以便于第一芯片与其他结构电连接。
一些实施例中,所述封装结构包括第二重布线层,所述第二重布线层设于所述第一封装体上,所述第二重布线层包括第二金属线路和与所述第二金属线路连接的第二导热件,所述第二导热件露出所述第二重布线层背向所述第一芯片的表面,所述第二金属线路部分露出第二重布线层朝向所述第一芯片的表面并与所述第一芯片的引脚连接。
一些实施例中,所述封装结构包括第一连接柱,所述第一连接柱设于所述第一封装体内且连接在所述第一金属线路和所述第二金属线路之间。第一连接柱用于实现电连接的同时还 能实现第一金属线路和第二金属线路的热量传递以及将第一封装体中的热量传递出去,以进一步提高封装结构的散热效果。
一些实施例中,所述封装结构包括第二芯片和第二封装体,所述第二芯片的背面一侧设于所述第二重布线层上并与所述第二导热件连接,所述第二封装体封装于所述第二芯片上,所述第二芯片的引脚露出所述第二封装体。第二芯片的热量通过第二导热件传递至第二金属线路,再通过第二金属线路向外导热,以使第二芯片在垂直方向上的具有很好的散热效果,提高了第二芯片的电性能,进而提高了封装结构的电性能。
一些实施例中,所述第一芯片为存储芯片,所述第二芯片为CPU芯片。
一些实施例中,所述封装结构包括第三重布线层和焊球,所述第三重布线层设于所述第二封装体上,所述焊球设于所述第三重布线层上,所述第三重布线层的第三金属线路连接在所述第二芯片的引脚和所述焊球之间。第三重布线层不光用于实现电连接,同时还将第一芯片和第二芯片传递到第三金属线路的热量通过焊球向外界传递,焊球用于与其他电子元件电连接。
一些实施例中,所述封装结构包括第二连接柱,所述第二连接柱设于所述第二封装体中,并连接在所述第二金属线路和所述第三金属线路之间。第二连接柱用于实现电路之间的连接的同时还能将第二芯片传到第二金属线路的热量导到其他部分,进一步提高封装结构的散热效果。
本申请实施例还提供一种封装结构,包括第一重布线层、第一芯片、第一传热件和第一封装体,所述第一重布线层包括第一金属线路,所述第一金属线路部分露出所述第一重布线层的顶面,所述第一芯片的正面用于传递信号,所述第一芯片的背面为与所述第一芯片的正面相背设置的无源面,所述第一芯片的正面的引脚设于所述顶面并与所述第一金属线路连接,所述第一传热件设于所述第一芯片的背面一侧,所述第一封装体封装与所述第一芯片上,所述第一传热件露出所述第一封装体的表面。
本申请实施例所述的封装结构,通过将第一传热件设于所述第一芯片的背面一侧,即,将第一传热件设于所述第一芯片的无源面一侧,且所述第一传热件露出所述第一封装体的表面。即,第一芯片的热量通过第一传热件传递出第一封装体进行散热,从而有效将第一芯片的热量从背面导出到封装结构外,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。
一些实施例中,所述封装结构还包括金属体,所述第一传热件为多个,多个所述第一传热件间隔设置,所述金属体连接多个所述第一传热件背向所述第一芯片的一端,所述第一传热件通过所述金属体露出所述第一封装体。通过金属体将多个第一传热件连接一方面了增大了第一芯片的散热面积,另一方面多个第一传热件通过金属体能与后续形成的导热件连接更牢固,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。
一些实施例中,所述第一芯片的背面设有阻隔层,所述阻隔层连接在所述背面和所述第一传热件之间。阻隔层用于隔离第一芯片和第一传热件,以避免第一传热件中的材料扩散到第一芯片中影响第一芯片的电性能,甚至导致第一芯片失效。阻隔层的材料例如为氮化硅。当然,在其他实施例中,阻隔层的材料还可以是其他可以阻止第一传热件中的材料扩散到第一芯片中的材料。
一些实施例中,所述封装结构包括第二重布线层,所述第二重布线层设于所述第一封装 体上,所述第二重布线层包括第二金属线路和与所述第二金属线路连接的第二导热件,所述第二导热件露出所述第二重布线层朝向所述第一芯片的表面并与所述金属体或所述第一传热件连接,所述第二金属线路部分露出第二重布线层背向所述第一芯片的表面。第二导热件用于连接第一传热件,从而将第一芯片传递到的第一传热件的热量通过第二导热件传递到第二金属线路并通过第二金属线路传导出去,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。
一些实施例中,所述封装结构包括第一连接柱,所述第一连接柱设于所述第一封装体内且连接在所述第一金属线路和所述第二金属线路之间。第一连接柱用于连接第一金属线路和第二金属线路,同时还能将第一芯片传到第一封装体的热量导到其他部分,或将第二金属线路的热量传递到第一金属线路,进一步提高封装结构的散热效果。
一些实施例中,所述封装结构包括第二芯片、第二封装体和第二传热件,所述第二芯片的正面的引脚设于所述第二重布线层上并与所述第二金属线路连接,所述第二传热件设于所述第二芯片的背面一侧,所述第二封装体封装于所述第二芯片上,所述第二传热件露出所述第二封装体的表面。第二芯片的热量从背面通过第二传热件传递出去,以使第二芯片在垂直方向上的具有很好的散热效果,提高了第二芯片的电性能,进而提高了封装结构的电性能。
一些实施例中,所述第一芯片为存储芯片,所述第二芯片为CPU芯片。
一些实施例中,所述封装结构包括第三重布线层和焊球,所述第三重布线层设于所述第二封装体上,所述第三重布线层中与第三金属线路连接的第三导热件与所述第二传热件连接,所述焊球设于所述第一重布线层背向所述第一芯片的表面并与所述第一金属线路连接。第三重布线层不光用于实现电连接,同时还将第一芯片和第二芯片传递到第三金属线路的热量向外界传递,焊球用于与其他电子元件电连接。
一些实施例中,所述封装结构包括第二连接柱,所述第二连接柱设于所述第二封装体中,并连接在所述第二金属线路和所述第三金属线路之间。第二连接柱用于连接第二金属线路和第三金属线路并实现热量传递,同时还能将第二芯片传到第二封装体的热量导到其他部分,进一步提高封装结构的散热效果。
本申请实施例还提供一种电子设备,包括以上所述的封装结构。具有本申请提供的封装结构的电子设备散热性能和稳定性具有显著提升。
本申请实施例还提供一种封装结构的制备方法,所述制备方法包括如下步骤:
制作第一重布线层,所述第一重布线层内设第一金属线路;
将第一芯片连接至所述第一重布线层,使得所述第一芯片的背面面对所述第一重布线层,且通过第一导热件连接所述第一金属线路;或者,通过第一封装体将所述第一芯片封装至所述第一重布线层,使得所述第一芯片的背面背对所述第一重布线层,且通过第一传热件连接至所述第一封装体的表面,其中,所述第一芯片的正面用于传递信号,所述第一芯片的背面为与所述第一芯片的正面相背设置的无源面。
本申请实施例所述的制备方法包括两种方案,一种方案是:将第一芯片连接至第一重布线层上,第一芯片的背面通过第一导热件连接至第一重布线层的第一金属线路,以将第一芯片的热量从背面经第一导热件传递至第一金属线路,最后经由第一金属线路导出,从而有效将第一芯片的热量从背面导出,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。另一种方案是:将第一芯片背对第一重布线层封装于第一重布线层上,第一芯片的背面通过第一传热件连接至第一封装体的表面, 即,第一芯片的热量通过第一传热件传递出第一封装体进行散热,从而有效将第一芯片的热量从背面导出到封装结构外,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。本申请提供的封装结构的制备方法中,不管第一芯片正装至第一重布线层,或者倒装至第一重布线层,均通过将导热结构(第一导热件或第一传热件)连接在第一芯片的背面,并通过导热结构将第一芯片散发的热传导至外部(传导的路径可以为第一重布线层的一侧,也可以通过传导至第一芯片背离第一重布线层的第一封装体的表面)。
一些实施例中,所述第一导热件为在制作所述第一重布线层的过程中形成在所述第一重布线层内,且与所述第一金属线路连接,所述第一导热件至少部分外露在所述第一重布线层的顶面,将所述第一芯片连接至所述第一重布线层的过程中,所述第一芯片的背面面对所述顶面。换言之,第一导热件嵌设于第一重布线层内,即第一导热件不占用额外的空间,不会因为增加第一导热件而使封装结构的尺寸变大。且在形成第一重布线层的同时形成第一导热件,减少制作工艺,在为第一芯片散热的同时,提高封装结构的生产效率,降低了封装结构的生产成本。
一些实施例中,所述第一导热件为金属材质,将所述第一芯片连接至所述第一重布线层之前,在所述第一芯片的背面制作阻隔层,所述阻隔层将所述背面和所述第一导热件隔开。阻隔层用于隔离第一芯片和第一导热件,以避免第一导热件中的材料扩散到第一芯片中影响第一芯片的电性能,甚至导致第一芯片失效。阻隔层的材料例如为氮化硅。当然,在其他实施例中,阻隔层的材料还可以是其他可以阻止第一导热件中的材料扩散到第一芯片中的材料。
一些实施例中,所述阻隔层与所述第一重布线层的顶面之间通过粘接层固定连接。换言之,粘接层用于将第一芯片固定于第一重布线层上,以在第一封装体将第一芯片封装于第一重布线层上时,第一芯片不会在封装过程中发生偏位,提高了封装结构的成品品质。
一些实施例中,将所述第一芯片连接至所述第一重布线层之后,通过第一封装体将所述第一芯片封装至所述第一重布线层,所述第一芯片的正面的引脚露出所述第一封装体的表面。第一芯片的引脚露出第一封装体的表面以便于第一芯片与其他结构电连接。
一些实施例中,在制作所述第一重布线层之后,在所述第一重布线层上形成第一连接柱,所述第一连接柱与所述第一金属线路连接,在通过所述第一封装体将所述第一芯片封装至所述第一重布线层的过程中,所述第一封装体同时封装所述第一连接柱,所述第一连接柱部分外露至所述第一封装体的表面。第一连接柱与露出第一重布线层的表面的部分第一金属线路连接,第一连接柱用于将第一金属线路和后续工艺中形成的第二重布线的第二金属线路连接,同时还能将第一芯片传到第一金属线路的热量导到其他部分,进一步提高封装结构的散热效果。
一些实施例中,所述制备方法还包括在所述第一封装体上制作第二重布线层,所述第二重布线层内设第二金属线路和与所述第二金属线路连接的第二导热件,所述第二导热件露出所述第二重布线层背向所述第一芯片的表面,所述第二金属线路部分露出第二重布线层朝向所述第一芯片的表面并与所述第一芯片的引脚和所述第一连接柱连接。第二导热件在制作第二重布线层的同时形成,有效简化封装结构的制备工艺,提高生产效率,降低生产成本。
一些实施例中,所述制备方法还包括将第二芯片连接至所述第二重布线层,使得所述第二芯片的背面面对所述第二重布线层,且通过第二导热件连接所述第二金属线路。第二芯片的热量通过第二导热件传递至第二金属线路,再通过第二金属线路向外导热,以使第二芯片 在垂直方向上的具有很好的散热效果,提高了第二芯片的电性能,进而提高了封装结构的电性能。
一些实施例中,所述第一芯片为存储芯片,所述第二芯片为CPU芯片。
一些实施例中,将所述第二芯片连接至所述第二重布线层之后,通过第二封装体将所述第二芯片封装至所述第二重布线层,所述第二芯片的正面的引脚露出所述第二封装体的表面。第二芯片的引脚露出第二封装体的表面以便于第二芯片与其他结构的电连接。
一些实施例中,在制作所述第二重布线层之后,在所述第二重布线层上形成第二连接柱,所述第二连接柱与所述第二金属线路连接,在通过所述第二封装体将所述第二芯片封装至所述第二重布线层的过程中,所述第二封装体同时封装所述第二连接柱,所述第二连接柱部分外露至所述第二封装体的表面。第二连接柱与露出第二重布线层的表面的部分第二金属线路连接,第二连接柱用于将第二金属线路和后续工艺中形成的第三重布线的第三金属线路连接,同时还能将第二芯片传到第二金属线路的热量导到其他部分,进一步提高封装结构的散热效果。
一些实施例中,所述制备方法还包括在所述第二封装体上制作第三重布线层,在所述第三重布线层上形成焊球,所述第三重布线层的第三金属线路连接所述第二芯片的引脚和所述第二连接柱。第三重布线层不光用于实现电连接,同时还将第一芯片和第二芯片传递到第三金属线路的热量通过焊球向外界传递,焊球用于与其他电子元件电连接。
一些实施例中,在通过所述第一封装体将所述第一芯片封装至所述第一重布线层之前,在所述第一芯片的背面一侧形成多个间隔的所述第一传热件,在所述第一封装体封装所述第一芯片之后,所述第一芯片的背面通过多个所述第一传热件连接至所述第一封装体的表面。第一芯片的热量从背面通过形成于第一芯片背面一侧的多个第一传热件传递出去,多个第一传热件能保证热量的有效传递,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。
一些实施例中,在通过所述第一封装体将所述第一芯片封装至所述第一重布线层之前,在所述第一芯片的背面一侧形成多个间隔的所述第一传热件,在所述第一芯片的背面一侧形成保护层,所述保护层包覆所述第一传热件,所述第一传热件远离所述第一芯片的端部露出所述保护层,在所述第一封装体封装所述第一芯片之后,所述保护层背向所述第一芯片的表面露出所述第一封装体的表面。第一芯片的热量从背面通过形成于第一芯片背面一侧的多个第一传热件传递出去,多个第一传热件能保证热量的有效传递,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。同时,在第一芯片封装之前,通过保护层固定多个第一传热件,以使第一传热件不会在封装第一芯片的过程中发生歪斜,从而进一步保证了第一芯片的散热效果。
一些实施例中,在通过所述第一封装体将所述第一芯片封装至所述第一重布线层之前,在所述第一芯片的背面一侧形成多个间隔的所述第一传热件,在所述第一芯片的背面一侧形成保护层,所述保护层包覆所述第一传热件,在所述保护层内形成金属体,所述金属体与多个所述第一传热件连接,所述金属体远离所述第一传热体的部分露出所述保护层,在所述第一封装体封装所述第一芯片之后,所述保护层背向所述第一芯片的表面露出所述第一封装体的表面。第一芯片的热量从背面通过形成于第一芯片背面一侧的多个第一传热件传递出去,多个第一传热件能保证热量的有效传递,通过金属体将多个第一传热件连接一方面了增大了第一芯片的散热面积,另一方面多个第一传热件通过金属体能与后续形成的导热件连接更牢 固,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。同时,在第一芯片封装之前,通过保护层固定多个第一传热件和金属体,以使第一传热件和金属体不会在封装第一芯片的过程中发生歪斜,从而进一步保证了第一芯片的散热效果。
一些实施例中,在所述第一封装体封装所述第一芯片之后,在所述第一封装体上形成多个间隔的开口以露出所述第一芯片的背面一侧,在所述开口中形成所述第一传热件。第一芯片的热量从背面通过形成于第一芯片背面一侧的多个第一传热件传递出去,多个第一传热件能保证热量的有效传递,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。
一些实施例中,在所述第一封装体封装所述第一芯片之后,在所述第一封装体上形成第一开口,在所述第一开口底壁形成多个间隔的第二开口,所述第二开口露出所述第一芯片的背面一侧,在所述第一开口和所述第二开口中形成所述第一传热件。以形成异形第一传热件,增大第一传热件的散热面,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。
一些实施例中,所述第一传热件为金属材质,在所述第一芯片的背面一侧形成所述第一传热件之前,在所述第一芯片的背面制作阻隔层,所述阻隔层将所述背面和所述第一传热件隔开。阻隔层用于隔离第一芯片和第一传热件,以避免第一传热件中的材料扩散到第一芯片中影响第一芯片的电性能,甚至导致第一芯片失效。阻隔层的材料例如为氮化硅。当然,在其他实施例中,阻隔层的材料还可以是其他可以阻止第一传热件中的材料扩散到第一芯片中的材料。
一些实施例中,在制作所述第一重布线层之后,在所述第一重布线层上形成第一连接柱,所述第一连接柱与所述第一金属线路连接,在通过所述第一封装体将所述第一芯片封装至所述第一重布线层的过程中,所述第一封装体同时封装所述第一连接柱,所述第一连接柱部分外露至所述第一封装体的表面。第一连接柱与露出第一重布线层的表面的部分第一金属线路连接,第一连接柱用于将第一金属线路和后续工艺中形成的第二重布线的第二金属线路连接,同时还能将第一芯片传到第一封装体的热量导到其他部分,进一步提高封装结构的散热效果。
一些实施例中,所述制备方法还包括在所述第一封装体上制作第二重布线层,所述第二重布线层内设第二金属线路和与所述第二金属线路连接的第二导热件,所述第二导热件露出所述第二重布线层朝向所述第一芯片的表面并与所述第一传热件或所述金属体连接,所述第二金属线路部分露出第二重布线层背向所述第一芯片的表面。第二导热件在制作第二重布线层的同时形成,有效简化封装结构的制备工艺,提高生产效率,降低生产成本。且第二导热件用于连接第一传热件,从而将第一芯片传递到的第一传热件的热量通过第二导热件传递到第二金属线路并通过第二金属线路传导出去,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。
一些实施例中,所述制备方法还包括通过第二封装体将第二芯片封装至所述第二重布线层,使得所述第二芯片的引脚与所述第二金属线路连接,所述第二芯片的背面背对所述第二重布线层,且通过第二传热件连接至所述第二封装体的表面。第二芯片的热量从背面通过第二传热件传递出去,以使第二芯片在垂直方向上的具有很好的散热效果,提高了第二芯片的电性能,进而提高了封装结构的电性能。
一些实施例中,所述第一芯片为存储芯片,所述第二芯片为CPU芯片。
一些实施例中,在制作所述第二重布线层之后,在所述第二重布线层上形成第二连接柱,所述第二连接柱与所述第二金属线路连接,在通过所述第二封装体将所述第二芯片封装至所述第二重布线层的过程中,所述第二封装体同时封装所述第二连接柱,所述第二连接柱部分外露至所述第二封装体的表面。第二连接柱与露出第二重布线层的表面的部分第二金属线路连接,第二连接柱用于将第二金属线路和后续工艺中形成的第三重布线的第三金属线路连接,同时还能将第二芯片传到第二封装体的热量导到其他部分,进一步提高封装结构的散热效果。
一些实施例中,所述制备方法还包括在所述第二封装体上制作第三重布线层,在所述第一重布线层背向所述第一芯片的表面形成焊球,所述第三重布线层的第三金属线路连接所述第二传热件和所述第二连接柱。第三重布线层不光用于实现电连接,同时还将第一芯片和第二芯片传递到第三金属线路的热量向外界传递,焊球用于与其他电子元件电连接。
本申请实施例所述的封装结构具有两种方案,一种方案中的第一芯片的背面一侧与第一导热件连接,以将第一芯片的热量从背面经第一导热件传递至第一金属线路,即,将第一芯片的热量从无源面经第一导热件传递至第一金属线路,最后经由第一金属线路导出,从而有效将第一芯片的热量从背面导出,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。另一种方案中的第一芯片通过将第一传热件设于所述第一芯片的背面一侧,即,将第一传热件设于所述第一芯片的无源面一侧,且所述第一传热件露出所述第一封装体的表面。即,第一芯片的热量通过第一传热件传递出第一封装体进行散热,从而有效将第一芯片的热量从背面导出到封装结构外,以使第一芯片在垂直方向上的具有很好的散热效果,提高了第一芯片的电性能,进而提高了封装结构的电性能。本申请提供的封装结构,不管第一芯片正装至第一重布线层,或者倒装至第一重布线层,均通过将导热结构(第一导热件或第一传热件)连接在第一芯片的背面(无源面),并通过导热结构将第一芯片散发的热传导至外部(传导的路径可以为第一重布线层的一侧,也可以通过传导至第一芯片背离第一重布线层的第一封装体的表面),从而有效提高封装结构在垂直方向的散热效果,进而提高了封装结构的电性能。
附图说明
图1是本申请实施例提供的一种电子设备的部分结构示意图。
图2是图1所示电子设备中的封装结构的结构示意图。
图3是图2所示的封装结构的另一种结构示意图。
图4是本申请提供的第二种封装结构的结构示意图。
图5是图2所示的封装结构的制备方法的流程示意图。
图6-图11是图5所示的制备方法的具体工艺流程图。
图12是图4所示的封装结构的制备方法的流程示意图。
图13-图18是图12所示的制备方法的具体工艺流程图。
具体实施方式
下面将结合本申请实施例中的附图对本申请实施例进行描述。
请参阅图1,图1是本申请实施例提供的一种电子设备100的部分结构示意图。
电子设备100包括壳体、电路板10和封装结构20,电路板10和封装结构20均收容于壳体内,封装结构20通过焊球连接于电路板10上。本实施例中的电子设备100包括且不限 于手机、平板电脑、电子书阅读器、笔记本电脑、台式电脑等具有封装结构20的电子设备。其中,封装结构20中埋入了多个芯片,芯片可以为不同功能的芯片,如存储芯片、CPU芯片、射频驱动芯片或者其他处理器的芯片等有源芯片元器件,以辅助电子设备100实现多种功能。本申请的封装结构20具有很好的散热效果和集成度,具有本申请提供的封装结构20的电子设备100散热性能和稳定性具有了显著提升,也满足轻量化设计的需求。
本申请提供的封装结构包括两种方案,一种方案是:请参阅图2,图2是图1所示电子设备100中的封装结构20的结构示意图。图2为封装结构20的第一种实施例。
封装结构20包括第一重布线层21、第一芯片22、第一封装体23、第二重布线层24、第二芯片25、第二封装体26、第三重布线层27和焊球28。第一封装体23将第一芯片22封装于第一重布线层21上,第一芯片22的背面朝向第一重布线层21,第一芯片22的正面的引脚221露出第一封装体23的表面。第二重布线层24设于第一封装体23上并与第一芯片22的引脚221和第一重布线层21电连接,第二封装体26将第二芯片25封装于第二重布线层24上,第二芯片25的背面朝向第二重布线层24,第二芯片25的正面的引脚251露出第二封装体26的表面。第三重布线层27设于第二封装体26上并与第二芯片25的引脚251和第二重布线层24电连接,焊球28连接于第三重布线层27并通过第三重布线层27与第一芯片22和第二芯片25电连接。本实施例中,第一芯片22和第二芯片25的正面为设有用于传递信号的引脚的表面,第一芯片22的背面为与第一芯片22的正面相背设置的无源面,第二芯片25的背面为与第二芯片25的正面相背设置的无源面。
第一重布线层21包括第一绝缘介质211、第一金属线路212和第一导热件213。第一金属线路212和第一导热件213连接并均设于第一绝缘介质211内。第一重布线层21具有相背设置的顶面214和底面215,第一重布线层21的顶面214和底面215即为第一绝缘介质211的顶面和底面。本实施例中的第一导热件213具有多个,多个第一导热件213间隔设置并至少部分露出第一重布线层21的顶面214。具体的,多个第一导热件213露出第一重布线层21的表面与顶面214平齐,第一芯片22的背面一侧设于顶面214,并与多个第一导热件213连接,以将第一芯片22的热量从背面经第一导热件213传递至第一金属线路212,最后经由第一金属线路212导出,从而有效将第一芯片22的热量从背面导出,以使第一芯片22在垂直方向上的具有很好的散热效果,提高了第一芯片22的电性能,进而提高了封装结构20的电性能。
本实施例中的第一绝缘介质211、第一金属线路212和第一导热件213可以通过构图工艺形成。例如,第一绝缘介质211可以为采用绝缘的树脂材料,例如苯并环丁烯(Benzo cyclo butene,BCB)或者聚酰亚胺(Polyimide,PI)等,通过曝光、显影、固化等构图工艺形成预设的薄膜图案。第一金属线路212和第一导热件213可以先采用沉积工艺、溅射工艺或者电镀工艺先形成一层金属薄膜层,然后采用刻蚀等构图工艺对上述金属薄膜层进行图案化形成。第一金属线路212和第一导热件213的材料可以包括金属铜、金属铝等导电材料。可以理解的是,图2中的第一金属线路212的中间部分和两边部分是隔开的,该图仅仅为图中位置剖视图的状态,实际上在其他位置第一金属线路212是连接的。当然,在其他实施例中,第一金属线路212的具体形状可根据需要设计。
本实施例中,还有部分第一导热件213露出顶面214与第一封装体23连接,以将第一芯片22传导到第一封装体23中的热量传递出去,提高第一芯片22的散热效果。第一金属线路212部分露出第一重布线层21的底面215,连接接口29设于底面215并与露出底面215的第 一金属线路212的一部分连接,以实现封装结构20与其他模块的连接。露出底面215的第一金属线路212的另一部分用于将第一芯片22的热量传递到外界,以提高封装结构20的散热效果。当然,第一导热件213和连接接口29的实现形式不限于上述描述。
本实施例中,第一芯片22为存储芯片。第一芯片22的背面设有阻隔层31,阻隔层31连接在第一芯片22的背面和第一导热件213之间。阻隔层31用于隔离第一芯片22和第一导热件213,以避免第一导热件213中的金属材料扩散到第一芯片22背面的半导体材料(例如硅)中影响半导体的导电性能,进而影响第一芯片22的电性能,甚至导致第一芯片22失效。阻隔层31的材料例如为氮化硅。当然,在其他实施例中,第一芯片22还可以是例如为CPU芯片、射频驱动芯片或者其他处理器的芯片等有源的电子器件。阻隔层31的材料还可以是其他可以阻止第一导热件213中的材料扩散到第一芯片22中的材料。
本实施例中,设于第一芯片22背面的阻隔层31和第一导热件213之间设有粘接层32,粘接层32将第一芯片22粘接至顶面214。粘接层32用于将第一芯片22固定于顶面214上,以在第一封装体23将第一芯片22封装于第一重布线层21上时,第一芯片22不会在封装过程中发生偏位,提高了封装结构20的成品品质。当粘接层32不能良好填充至第一导热件213和第一芯片22之间时,阻隔层31能有效防止第一导热件213在第一芯片22中扩散,提高了封装结构20的制备良率。
当然,在其他实施例中,请参阅图3,多个第一导热件213露出第一重布线层21的部分凸出于顶面214,以使粘接层32粘接至顶面214时,部分凸出于顶面214的第一导热件213嵌入粘接层32中。还有部分凸出于顶面214的第一导热件213嵌入第一封装体23中,以增大第一导热件213与粘接层32和第一封装体23接触面积,以使第一芯片22和第一芯片22传递到第一封装体23中的热量快速通过第一导热件213传递到第一金属线路212,进而通过第一金属线路212传递到外界,有效提高封装结构20的散热效果。当然,多个第一导热件213露出第一重布线层21的部分还可以直接抵持于隔离层31上,换言之,多个第一导热件213和隔离层31之间未设有粘接层,以将第一芯片22的热量直接通过第一导热件213导出,有效提高封装结构20的散热效果。
如图2所示,第二重布线层24包括第二绝缘介质241、第二金属线路242和第二导热件243。第二金属线路242和第二导热件243连接并均设于第二绝缘介质241内。第二金属线路242部分露出第二重布线层24朝向第一芯片22的表面并与第一芯片22的引脚221连接。本实施例中的第二导热件243具有多个,多个第二导热件243间隔设置并至少部分露出第二重布线层24背向第一芯片22的表面。具体的,多个第二导热件243露出第二重布线层24的表面与第二重布线层24背向第一芯片22的表面平齐,第二芯片25的背面一侧设于第二重布线层24背向第一芯片22的表面上,并与多个第二导热件243连接,以将第二芯片25的热量从背面经第二导热件243传递至第二金属线路242,最后经由第二金属线路242导出,从而有效将第二芯片25的热量从背面导出,以使第二芯片25在垂直方向上的具有很好的散热效果,提高了第二芯片25的电性能,进而提高了封装结构20的电性能。本实施例中,第二重布线层24采用与第一重布线层21相同的制作工艺形成。还有部分第二导热件243露出第二重布线层24与第二封装体26连接,以将第二芯片25传导到第二封装体26中的热量传递出去,提高第二芯片25的散热效果。图2中的第二金属线路242仅仅为图中位置剖视图的状态。当然,在其他实施例中,第二金属线路242的具体形状可根据需要设计。第二导热件243的实现形式不限于上述描述。
本实施例中,第二芯片25为CPU芯片。第二芯片25的背面设有阻隔层33,阻隔层33连接在第二芯片25背面和第二导热件243之间。阻隔层33用于隔离第二芯片25和第二导热件243,以避免第二导热件243中的金属材料扩散到第二芯片25背面的半导体材料(例如硅)中影响半导体的导电性能,进而影响第二芯片25的电性能,甚至导致第二芯片25失效。阻隔层33的材料例如为氮化硅。当然,在其他实施例中,第二芯片25还可以是存储芯片、射频驱动芯片或者其他处理器的芯片等有源的电子器件。阻隔层33的材料还可以是其他可以阻止第二导热件243中的材料扩散到第二芯片25中的材料。
本实施例中,设于第二芯片25背面的阻隔层33和第二导热件243之间设有粘接层34,粘接层34将第二芯片25粘接至第二重布线层24上。粘接层34用于将第二芯片25固定于第二重布线层24上,以在第二封装体26将第二芯片25封装于第二重布线层24上时,第二芯片25不会在封装过程中发生偏位,提高了封装结构20的成品品质。当粘接层34不能良好填充至第二导热件243和第二芯片25之间时,阻隔层34能有效防止第二导热件243在第二芯片25中扩散,提高了封装结构20的制备良率。
当然,在其他实施例中,请参阅图3,多个第二导热件243露出第二重布线层21的部分凸出于第二重布线层21背向第一芯片22的表面,以使粘接层34粘接至第二重布线层21背向第一芯片22的表面时,部分凸出于第二重布线层21背向第一芯片22的表面的第二导热件243嵌入粘接层34中。还有部分凸出于第二重布线层21背向第一芯片22的表面的第二导热件243嵌入第二封装体26中,以增大第二导热件243与粘接层34和第二封装体26接触面积,以使第二芯片25和第二芯片25传递到第二封装体26中的热量快速通过第二导热件243传递到第二金属线路242,进而通过第二金属线路242传递到外界,有效提高封装结构20的散热效果。当然,多个第二导热件243露出第二重布线层24的部分还可以直接抵持于隔离层34上,换言之,多个第二导热件243和隔离层34之间未设有粘接层,以将第二芯片25的热量直接通过第二导热件243导出,有效提高封装结构20的散热效果。
如图2所示,封装结构20还包括第一连接柱216,第一连接柱216设于第一封装体23内,两端分别被连接至第一重布线层21和第二重布线层24上,并且与第一重布线层21和第二重布线层24中的第一金属线路212和第二金属线路242接触。与第一连接柱216连接的第一金属线路212和第二金属线路242的部分露出顶面214和第二重布线层24朝向第一连接柱216的表面,以便于与第一连接柱216电连接。第一连接柱216用于实现第一金属线路212和第二金属线路242电连接的同时还能实现第一金属线路212和第二金属线路242的热量传递以及将第一封装体23中的热量传递出去,以进一步提高封装结构20的散热效果。
第三重布线层27包括第三绝缘介质271和第三金属线路272,第三金属线路272设于第三绝缘介质271内。部分第三金属线路272露出第三重布线层27朝向第二芯片25的表面,并与第二芯片25的引脚251连接,部分第三金属线路272露出第三重布线层27背向第二芯片25的表面并与焊球28连接,具体的,焊球28通过焊盘35与露出第三重布线层27背向第二芯片25的表面的第三金属线路272连接。本实施例中,第三重布线层27采用与第一重布线层21相同的制作工艺形成。第三重布线层27不光用于实现焊球28与第一芯片22和第二芯片25的电连接,同时还将第一芯片22和第二芯片25传递到第三金属线路272的热量通过焊球28向外界传递,焊球28用于与其他电子元件电连接。图2中的第三金属线路272和焊球28的设置方式仅仅为本实施例中列举的一种。当然,在其他实施例中,第三金属线路272和焊球28的具体形状可根据需要设计。
封装结构20包括第二连接柱244,第二连接柱244设于第二封装体26中,两端分别被连接至第二重布线层24和第三重布线层27上,并且与第二重布线层24和第三重布线层27中的第二金属线路242和第三金属线路272接触。与第二连接柱244连接的第二金属线路242和第三金属线路272的部分露出第二重布线层24和第三重布线层27朝向第二连接柱244的表面,以便于与第二连接柱244电连接。第二连接柱244用于实现电路之间的连接的同时还能将第二芯片25传到第二金属线路242的热量导到其他部分,进一步提高封装结构20的散热效果。
本申请实施例的封装结构20封装有两个芯片,第一芯片22和第二芯片25的背面一侧分别与第一导热件213和第二导热件243连接,以将第一芯片22的热量从背面经第一导热件213传递至第一金属线路212,将第二芯片25的热量从背面经第二导热件243传递至第二金属线路242,最后经由第一金属线路212和第二金属线路242导出,从而有效将第一芯片22和第二芯片25的热量从背面导出,以使第一芯片22和第二芯片25在垂直方向上的具有很好的散热效果,提高了第一芯片22和第二芯片25的电性能,进而提高了封装结构20的电性能。同时,由于本申请的封装结构20解决了芯片在垂直方向上的散热问题,封装结构20还可以实现两个芯片以上的多层芯片的堆叠,从而实现散热芯片要求较高的芯片的多层堆叠,保证芯片散热效果的同时有效提高封装结构20的集成度。
另一种方案是:请参阅图4,图4是本申请提供的第二种封装结构20的结构示意图。封装结构20包括第一重布线层21、第一芯片22、第一封装体23、第二重布线层24、第二芯片25、第二封装体26、第三重布线层27和焊球28。第一封装体23将第一芯片22封装于第一重布线层21上,第一芯片22的正面的引脚221设于第一重布线层21上并与第一重布线层21连接,设于第一芯片22背面一侧的第一传热件41露出第一封装体23的表面。第二重布线层24设于第一封装体23上并与设于第一芯片22背面一侧的第一传热件41和第一重布线层21电连接,第二封装体26将第二芯片25封装于第二重布线层24上,第二芯片25的正面的引脚251设于第二重布线层24上并与第二重布线层24连接,设于第二芯片25背面一侧的第二传热件42露出第二封装体26的表面。第三重布线层27设于第二封装体26上并与设于第二芯片25背面一侧的第二传热件42和第二重布线层24电连接,焊球28连接于第一重布线层21并通过第一重布线层21与第一芯片22和第二芯片25电连接。本实施例中,第一芯片22和第二芯片25的正面为设有用于传递信号的引脚的表面,第一芯片22的背面为与第一芯片22的正面相背设置的无源面,第二芯片25的背面为与第二芯片25的正面相背设置的无源面。
本申请实施例的封装结构20封装有两个芯片,通过将第一传热件41设于第一芯片22的背面一侧,且第一传热件41露出第一封装体23与第二重布线层24连接,和通过将第二传热件42设于第二芯片25的背面一侧,且第二传热件42露出第二封装体26与第三重布线层27连接。即,第一芯片22和第二芯片25的热量分别通过第一传热件41和第二传热件42传递到第二重布线层24和第三重布线层27进行散热,从而有效将第一芯片22和第二芯片25的热量从背面导出到封装结构20外,以使第一芯片22和第二芯片25在垂直方向上的具有很好的散热效果,提高了第一芯片22和第二芯片25的电性能,进而提高了封装结构20的电性能。同时,由于本申请的封装结构20解决了芯片在垂直方向上的散热问题,封装结构20还可以实现两个芯片以上的多层芯片的堆叠,从而实现散热芯片要求较高的芯片的多层堆叠,保证芯片散热效果的同时有效提高封装结构20的集成度。
第一重布线层21包括第一绝缘介质211、第一金属线路212和第一导热件213。第一金属线路212和第一导热件213连接并均设于第一绝缘介质211内。第一重布线层21具有相背设置的顶面214和底面215,第一重布线层21的顶面214和底面215即为第一绝缘介质211的顶面和底面。第一金属线路212部分露出顶面214与第一芯片22的引脚221连接,第一金属线路212还有部分露出底面215以与焊球28连接,具体的,焊球28通过焊盘35与露出底面215的第一金属线路212连接。焊球28用于与其他电子元件电连接。可以理解的是,图4中的第一金属线路212具有多个隔开的部分,该图仅仅为图中位置剖视图的状态,实际上在其他位置第一金属线路212是连接的。当然,在其他实施例中,第一金属线路212的具体形状可根据需要设计。
本实施例中的第一导热件213具有多个,多个第一导热件213间隔设置并至少部分露出第一重布线层21的顶面214。具体的,多个第一导热件213露出第一重布线层21的表面与顶面214平齐,第一导热件213露出顶面214与第一封装体23连接以将第一芯片22传导到第一封装体23中的热量通过第一金属线路212传递出去,有效提高第一芯片22的散热效果。当然,在其他实施例中,多个第一导热件213露出第一重布线层21的部分凸出于顶面214。第一导热件213和焊球28的实现形式不限于上述描述。
本实施例中,第一芯片22为存储芯片。第一芯片22的背面设有阻隔层31,阻隔层31连接在第一芯片22的背面和第一传热件41之间。阻隔层31用于隔离第一芯片22和第一传热件41,以避免第一传热件41中的金属材料扩散到第一芯片22背面的半导体材料(例如硅)中影响半导体的导电性能,进而影响第一芯片22的电性能,甚至导致第一芯片22失效。阻隔层31的材料例如为氮化硅。当然,在其他实施例中,第一芯片22还可以是例如为CPU芯片、射频驱动芯片或者其他处理器的芯片等有源的电子器件。阻隔层31的材料还可以是其他可以阻止第一传热件41中的材料扩散到第一芯片22中的材料。
封装结构20还包括金属体43,本实施例中的第一传热件41为多个,且为柱状,多个第一传热件41间隔连接在阻隔层31和金属体43之间。多个第一传热件41和金属体43通过保护层44封装于第一芯片22的背面,保护层44露出第一封装体23的表面,金属体43露出保护层44背向第一芯片22的表面,也即,第一传热件41通过金属体43露出第一封装体23与第二重布线层24连接。本实施例中,金属体43可以为金属薄层,或者为金属网层。通过金属体43将多个第一传热件41连接一方面了增大了第一芯片22的散热面积,另一方面多个第一传热件41通过金属体43能与第二重布线层24连接更牢固,以使第一芯片22在垂直方向上的具有很好的散热效果,提高了第一芯片22的电性能,进而提高了封装结构20的电性能。当然,在其他实施例中,封装结构20中未设有金属体43,第一传热件41直接连接在阻隔层31和第二重布线层24之间。
第二重布线层24包括第二绝缘介质241、第二金属线路242和第二导热件243,第二金属线路242和第二导热件243连接并均设于第二绝缘介质241内。第二金属线路242部分露出第二重布线层24背向第一芯片22的表面与第二芯片25的引脚251连接,第二导热件243一部分露出第二重布线层24背向第一芯片22的表面与第二封装体26连接,以将第二芯片25传导到第二封装体26的热量传递出去,第二导热件243另一部分露出第二重布线层24朝向第一芯片22的表面与第一芯片22的金属体43连接,以将第一芯片22的热量通过第一传热件41、金属体43和第二导热件243传导到第二金属线路242并通过第二金属线路242传导出去,以使第一芯片22在垂直方向上的具有很好的散热效果,提高了第一芯片22的电性 能,进而提高了封装结构20的电性能。图4中的第二金属线路242仅仅为图中位置剖视图的状态。当然,在其他实施例中,第二金属线路242的具体形状可根据需要设计。第二导热件243另一部分露出第二重布线层24朝向第一芯片22的表面与第一芯片22的第一传热件41连接,以将第一芯片22的热量通过第一传热件41和第二导热件243传导到第二金属线路242并通过第二金属线路242传导出去。第二导热件243的实现形式不限于上述描述。
本实施例中,第二芯片25为CPU芯片。第二芯片25的背面设有阻隔层33,阻隔层33连接在第二芯片25的背面和第二传热件42之间。阻隔层33用于隔离第二芯片25和第二传热件42,以避免第二传热件42中的金属材料扩散到第二芯片25背面的半导体材料(例如硅)中影响半导体的导电性能,进而影响第二芯片25的电性能,甚至导致第二芯片25失效。阻隔层33的材料例如为氮化硅。当然,在其他实施例中,第二芯片25还可以是存储芯片、、射频驱动芯片或者其他处理器的芯片等有源的电子器件。阻隔层33的材料还可以是其他可以阻止第二传热件42中的材料扩散到第二芯片25中的材料。
第二传热件42远离阻隔层33的端部连接有金属体45,本实施例中的第二传热件42为多个,且为柱状,多个第二传热件42连接在阻隔层33和金属体45之间。多个第二传热件42和金属体45通过保护层46封装于第二芯片25的背面,保护层46露出第二封装体26的表面,金属体45露出保护层46背向第二芯片25的表面,也即,第二传热件42通过金属体45露出第二封装体26与第三重布线层27连接。本实施例中,金属体45可以为金属薄层,或者为金属网层。通过金属体45将多个第二传热件42连接一方面了增大了第二芯片25的散热面积,另一方面多个第二传热件42通过金属体45能与第三重布线层27连接更牢固,以使第二芯片25在垂直方向上的具有很好的散热效果,提高了第二芯片25的电性能,进而提高了封装结构20的电性能。当然,在其他实施例中,封装结构20中未设有金属体45,第二传热件42直接连接在阻隔层33和第三重布线层27之间。
封装结构20还包括第一连接柱216,第一连接柱216设于第一封装体23内,两端分别被连接至第一重布线层21和第二重布线层24上,并且与第一重布线层21和第二重布线层24中的第一金属线路212和第二金属线路242接触。与第一连接柱216连接的第一金属线路和第二金属线路242的部分露出顶面214和第二重布线层24朝向第一连接柱216的表面,以便于与第一连接柱216电连接。第一连接柱216用于连接第一金属线路212和第二金属线路242,同时还能将第一芯片22传到第一封装体23的热量导到其他部分,或将第二金属线路242的热量传递到第一金属线路212,进一步提高封装结构20的散热效果。
第三重布线层27包括第三绝缘介质271、第三金属线路272和第三导热件273,第三金属线路272和第三导热件273连接且均设于第三绝缘介质271内。第三导热件273露出第三重布线层27朝向第二芯片25的表面,一部分与第二封装体26连接,以将第二芯片25传导到第二封装体26的热量传导出去,一部分通过金属体45与第二传热件42连接,以将第二芯片25的热量从背面通过第二传热件42传递出去,以使第二芯片25在垂直方向上的具有很好的散热效果,提高了第二芯片25的电性能,进而提高了封装结构20的电性能。第三重布线层27背向第二芯片25的表面设有连接接口29,第三金属线部分露出第三重布线层27背向第二芯片25的表面,一部分用于与连接接口29连接,以实现封装结构20与其他模块的连接及封装结构20接地,另一部分用于将第二芯片25的热量传递到外界,以提高封装结构20的散热效果。可以理解的是,图3中的第三金属线路272和连接接口29的设置方式仅仅为本实施例中列举的一种。当然,在其他实施例中,第三金属线路272和连接接口29的具体形状可 根据需要设计。
封装结构20包括第二连接柱244,第二连接柱244设于第二封装体26中,两端分别被连接至第二重布线层24和第三重布线层27上,并且与第二重布线层24和第三重布线层27中的第二金属线路242和第三金属线路272接触。与第二连接柱244连接的第二金属线路242和第三金属线路272的部分露出第二重布线层24和第三重布线层27朝向第二连接柱244的表面,第二连接柱244用于连接第二金属线路242和第三金属线路272并实现热量传递,同时还能将第二芯片25传到第二封装体26的热量导到其他部分,进一步提高封装结构20的散热效果。
本申请提供的封装结构20中,不管第一芯片22正装至第一重布线层21,或者倒装至第一重布线层21,均通过将导热结构(第一导热件213或第一传热件41)连接在第一芯片22的背面,并通过导热结构将第一芯片22散发的热传导至外部(传导的路径可以为第一重布线层21的一侧,也可以通过传导至第一芯片22背离第一重布线层21的第一封装体23的表面)。不管第二芯片25正装至第二重布线层24,或者倒装至第二重布线层24,均通过将导热结构连接在第二芯片25的背面,并通过导热结构将第二芯片25散发的热传导至外部(传导的路径可以为第二重布线层24的一侧,也可以通过传导至第二芯片25背离第二重布线层24的第二封装体26的表面)。
请参阅图5,图5是图2所示的封装结构20的制备方法的流程示意图。如图5所示,第一种封装结构20的制备方法包括如下的S110~S150。
S110:制作第一重布线层21,第一重布线层21内设第一金属线路212。
具体的,请参阅图6,提供载板50,在载板50上制作第一重布线层21,第一重布线层21包括第一绝缘介质211和内设于第一绝缘介质211的第一金属线路212。本实施例中,第一绝缘介质211和第一金属线路212可以通过构图工艺形成,以使第一重布线层21的第一金属线路212一部分露出第一重布线层21的底面215,一部分露出第一重布线层21的顶面214。例如,第一绝缘介质211可以为采用绝缘的树脂材料,例如苯并环丁烯(Benzo cyclo butene,BCB)或者聚酰亚胺(Polyimide,PI)等,通过曝光、显影、固化等构图工艺形成预设的薄膜图案。第一金属线路212可以先采用沉积工艺、溅射工艺或者电镀工艺先形成一层金属薄膜层,然后采用刻蚀等构图工艺对上述金属薄膜层进行图案化形成。第一金属线路212的材料可以包括金属铜、金属铝等导电材料。可以理解的是,图6中的第一金属线路212的中间部分和两边部分是隔开的,该图仅仅为图中位置剖视图的状态,实际上在其他位置第一金属线路212是连接的。当然,在其他实施例中,第一金属线路212的具体形状可根据需要设计。
在制作第一重布线层21的过程中同时形成第一导热件213,以使第一导热件213与第一金属线路212连接且至少部分外露在第一重布线层21的顶面214。本实施例中,第一导热件213具有多个,多个第一导热件213间隔设置,且多个第一导热件213露出第一重布线层21的表面与顶面214平齐。第一导热件213的制作工艺和第一金属线路212的制作工艺相同,第一导热件213的材料也和第一金属线路212相同。可以理解的是,第一导热件213嵌设于第一重布线层21内,即第一导热件213不占用额外的空间,不会因为增加第一导热件213而使封装结构20的尺寸变大。且在形成第一重布线层21的同时形成第一导热件213,减少制作工艺,提高封装结构20的生产效率,降低了封装结构20的生产成本。当然,在其他实施例中,多个第一导热件213露出第一重布线层21的部分凸出于第一重布线层21的顶面214。
在制作第一重布线层21之后,在第一重布线层21上形成第一连接柱216。具体的,在 露出第一重布线层21的顶面214的第一金属线路212上形成第一连接柱216,以使第一连接柱216与第一金属线路212连接。第一连接柱216具体形成工艺为涂胶、光刻、显影和电镀。第一连接柱216的材质和第一金属线路212相同。第一连接柱216用于将第一金属线路212和后续工艺中形成的第二重布线的第二金属线路242连接,同时还能将第一金属线路212的热量导到其他部分,进一步提高封装结构20的散热效果。
S120:将第一芯片22连接至第一重布线层21,使得第一芯片22的背面面对第一重布线层21,且通过第一导热件213连接第一金属线路212,其中,第一芯片22的正面用于传递信号,第一芯片22的背面为与第一芯片22的正面相背设置的无源面。
具体的,请参阅图7-图8,将第一芯片22连接至第一重布线层21之前,在第一芯片22的背面制作阻隔层31,然后在阻隔层31背向第一芯片22的表面粘贴粘接层32,然后将第一芯片22的背面面对顶面214并通过粘接层32固定于顶面214并与露出顶面214的第一导热件213连接,以使第一芯片22的背面通过第一导热件213连接至第一金属线路212,以将第一芯片22的热量从背面经第一导热件213传递至第一金属线路212,最后经由第一金属线路212导出,从而有效将第一芯片22的热量从背面导出,以使第一芯片22在垂直方向上的具有很好的散热效果,提高了第一芯片22的电性能,进而提高了封装结构20的电性能。
本实施例中的第一芯片22例如为为存储芯片。阻隔层31用于隔离第一芯片22和第一导热件213,当粘接层32不能良好填充至第一导热件213和第一芯片22之间时,阻隔层31能有效防止第一导热件213在第一芯片22中扩散,以避免第一导热件213中的金属材料通过粘接层32扩散到第一芯片22背面的半导体材料(例如硅)中影响半导体的导电性能,进而影响第一芯片22的电性能,甚至导致第一芯片22失效。阻隔层31的材料例如为氮化硅。粘接层32用于将第一芯片22固定于第一重布线层21上,以在第一封装体23将第一芯片22封装于第一重布线层21上时,第一芯片22不会在封装过程中发生偏位,提高了封装结构20的成品品质。当然,在其他实施例中,第一芯片22还可以是CPU芯片、射频驱动芯片或者其他处理器的芯片等有源的电子器件。阻隔层31的材料还可以是其他可以阻止第一导热件213中的材料扩散到第一芯片22中的材料。当然,多个第一导热件213露出第一重布线层21的部分还可以直接抵持于隔离层31上,换言之,多个第一导热件213和隔离层31之间未设有粘接层,以将第一芯片22的热量直接通过第一导热件213导出,有效提高封装结构20的散热效果。
将第一芯片22连接至第一重布线层21之后,通过第一封装体23将第一芯片22封装至第一重布线层21,在第一封装体23封装第一芯片22的同时,也将第一连接柱216封装在第一封装体23内,然后对第一封装体23背向第一重布线层21的表面进行研磨,以使第一芯片22的正面的引脚221和第一连接柱216露出第一封装体23的表面。第一芯片22的引脚221和第一连接柱216露出第一封装体23的表面以便于第一芯片22和第一连接柱216与其他结构电连接。本实施例中,第一封装体23的材料为绝缘的树脂材料,例如为环氧树脂材料。
S130:在第一封装体23上制作第二重布线层24。
具体的,请参阅图9,在第一封装体23背向第一重布线层21的表面制作第二重布线层24,第二重布线层24包括第二绝缘介质241和内设于第二绝缘介质241的第二金属线路242。本实施例中,第二绝缘介质241和第二金属线路242可以通过构图工艺形成,以使第二重布线层24的第二金属线路242一部分露出第二重布线层24朝向第一芯片22的表面与第一芯片22的引脚221和第一连接柱216连接,一部分露出第二重布线层24背向第一芯片22的表面。 本实施例中的第二重布线层24的制作工艺和第一重布线层21的制作工艺相同。第二绝缘介质241的材料和第一绝缘介质211的材料相同,第二金属线路242和第一金属线路212的材料相同。图9中的第二金属线路242仅仅为图中位置剖视图的状态。当然,在其他实施例中,第二金属线路242的具体形状可根据需要设计。第二重布线层24的制作工艺可以和第一重布线层21的制作工艺不同,材料也可以不同。
在制作第二重布线层24的过程中同时形成第二导热件243,以使第二导热件243与第二金属线路242连接且至少部分外露在第二重布线层24背向第一芯片22的表面。本实施例中,第二导热件243具有多个,多个第二导热件243间隔设置,且多个第二导热件243露出第二重布线层24的表面与第二重布线层24背向第一芯片22的平齐。第二导热件243的制作工艺和第二金属线路242的制作工艺相同,第二导热件243的材料也和第二金属线路242相同。可以理解的是,第二导热件243嵌设于第二重布线层24内,即第二导热件243不占用额外的空间,不会因为增加第二导热件243而使封装结构20的尺寸变大。且在形成第二重布线层24的同时形成第二导热件243,减少制作工艺,提高封装结构20的生产效率,降低了封装结构20的生产成本。当然,在其他实施例中,多个第二导热件243露出第二重布线层24的部分凸出于第二重布线层24背向第一芯片22的表面。
在制作第二重布线层24之后,在第二重布线层24上形成第二连接柱244。具体的,在露出第二重布线层24的背向第一芯片22的表面的第二金属线路242上形成第二连接柱244,以使第二连接柱244与第二金属线路242连接。第二连接柱244具体形成工艺为涂胶、光刻、显影和电镀。第二连接柱244的材质和第二金属线路242相同。第二连接柱244用于将第二金属线路242和后续工艺中形成的第三重布线的第三金属线路连接,同时还能将第二金属线路242的热量导到其他部分,进一步提高封装结构20的散热效果。
S140:将第二芯片25连接至第二重布线层24,使得第二芯片25的背面面对第二重布线层24,且通过第二导热件243连接第二金属线路242,其中,第二芯片25的正面用于传递信号,第二芯片25的背面为与第二芯片25的正面相背设置的无源面。
具体的,请参阅图10,将第二芯片25连接至第二重布线层24之前,在第二芯片25的背面制作阻隔层33,然后在阻隔层33背向第二芯片25的表面粘贴粘接层34,然后将第二芯片25的背面面对第二重布线层24背向第一芯片22的表面并通过粘接层34固定于第二重布线层24背向第一芯片22的表面并与露出第二重布线层24背向第一芯片22的表面的第二导热件243连接,以使第二芯片25的背面通过第二导热件243连接至第二金属线路242,以将第二芯片25的热量从背面经第二导热件243传递至第二金属线路242,最后经由第二金属线路242导出,从而有效将第二芯片25的热量从背面导出,以使第二芯片25在垂直方向上的具有很好的散热效果,提高了第二芯片25的电性能,进而提高了封装结构20的电性能。
本实施例中的第二芯片25为CPU芯片。阻隔层33用于隔离第二芯片25和第二导热件243,当粘接层34不能良好填充至第二导热件243和第二芯片25之间时,阻隔层34能有效防止第二导热件243在第二芯片25中扩散,以避免第二导热件243中的金属材料通过粘接层34扩散到第二芯片25背面的半导体材料(例如硅)中影响半导体的导电性能,进而影响第二芯片25的电性能,甚至导致第二芯片25失效。阻隔层33的材料例如为氮化硅。粘接层34用于将第二芯片25固定于第二重布线层24上,以在第二封装体26将第二芯片25封装于第二重布线层24上时,第二芯片25不会在封装过程中发生偏位,提高了封装结构20的成品品质。当然,在其他实施例中,第二芯片25还可以是存储芯片、射频驱动芯片或者其他处理 器的芯片等有源的电子器件。阻隔层33的材料还可以是其他可以阻止第二导热件243中的材料扩散到第二芯片25中的材料。当然,多个第二导热件243露出第二重布线层24的部分还可以直接抵持于隔离层34上,换言之,多个第二导热件243和隔离层34之间未设有粘接层,以将第二芯片25的热量直接通过第二导热件243导出,有效提高封装结构20的散热效果。
将第二芯片25连接至第二重布线层24之后,通过第二封装体26将第二芯片25封装至第二重布线层24,在第二封装体26封装第二芯片25的同时,也将第二连接柱244封装在第二封装体26内,然后对第二封装体26背向第二重布线层24的表面进行研磨,以使第二芯片25的正面的引脚251和第二连接柱244露出第二封装体26的表面。第二芯片25的引脚251和第二连接柱244露出第二封装体26的表面以便于第二芯片25和第二连接柱244与其他结构电连接。本实施例中,第二封装体26的材料与第一封装体23的材料相同。
S150:在第二封装体26上制作第三重布线层27,在第三重布线层27上形成焊球28。
具体的,请参阅图11,在第二封装体26背向第二芯片25的背面制作第三重布线层27,第三重布线层27包括第三绝缘介质271和设于第三绝缘介质271的第三金属线路272。本实施例中,第三绝缘介质271和第三金属线路272可以通过构图工艺形成,以使第三重布线层27的第三金属线路272一部分露出第三重布线层27朝向第二芯片25的表面并与第二芯片25的引脚251和第二连接柱244连接,一部分露出第三重布线背向第二芯片25的表面。本实施例中的第三重布线层27的制作工艺和第一重布线层21的制作工艺相同。第三绝缘介质271的材料和第三绝缘介质271的材料相同,第三金属线路272和第一金属线路212的材料相同。图11中的第三金属线路272和焊球28的设置方式仅仅为本实施例中列举的一种。当然,在其他实施例中,第三金属线路272和焊球28的具体形状可根据需要设计。第三重布线层27的制作工艺可以和第一重布线层21的制作工艺不同,材料也可以不同。
去除载板50,在第三重布线层27背向第二芯片25的表面形成焊球28,以使焊球28与露出第三布线层的第三金属线路272连接,具体的,焊球28通过焊盘35与露出第三重布线层27背向第二芯片25的表面的第三金属线路272连接。第三重布线层27不光用于实现第二金属线路242和第三金属线路272的电连接,同时还将第一芯片22和第二芯片25传递到第三金属线路272的热量通过焊球28向外界传递。焊球28用于与其他电子元件电连接。
在第一重布线层21的底面215形成连接接口29,连接接口29与部分露出第一重布线层21的底面215的第一金属线路212连接,以形成封装结构20,另一部分露出第一重布线层21的底面215的第一金属线路212用于将第一芯片22和第二芯片25的热量传导外界,以提高封装结构20的散热效果。连接接口29用于与其他电子模块连接及实现封装结构20接地。连接接口29的设置方式不限于图11所示。
本申请实施例的制备方法,将第一芯片22连接至第一重布线层21上,第一芯片22的背面通过第一导热件213连接至第一重布线层21的第一金属线路212,将第二芯片25连接至第二重布线层24上,第二芯片25的背面通过第二导热件243连接至第二重布线层24的第二金属线路242,以将第一芯片22和第二芯片25的热量从背面经第一导热件213和第二导热件243传递至第一金属线路212和第二金属线路242,最后经由第一金属线路212和第二金属线路242导出,从而有效将第一芯片22和第二芯片25的热量从背面导出,以使第一芯片22和第二芯片25在垂直方向上的具有很好的散热效果,提高了第一芯片22和第二芯片25的电性能,进而提高了封装结构20的电性能。同时,由于本申请的制备方法解决了芯片在垂直方向上的散热问题,封装结构20还可以实现两个芯片以上的多层芯片的堆叠,从而实现散 热芯片要求较高的芯片的多层堆叠,保证芯片散热效果的同时有效提高封装结构20的集成度。
请参阅图12,图12是图4所示的封装结构20的制备方法的流程示意图。如图12所示,第二种封装结构20的制备方法包括如下的S210~S250。
S210:制作第一重布线层21,第一重布线层21内设第一金属线路212。
具体的,请参阅图13,提供载板50,在载板50上制作第一重布线层21,第一重布线层21包括第一绝缘介质211和内设于第一绝缘介质211的第一金属线路212。本实施例中,第一绝缘介质211和第一金属线路212可以通过构图工艺形成,以使第一重布线层21的第一金属线路212一部分露出第一重布线层21的底面215,一部分露出第一重布线层21的顶面214。例如,第一绝缘介质211可以为采用绝缘的树脂材料,例如苯并环丁烯(Benzo cyclo butene,BCB)或者聚酰亚胺(Polyimide,PI)等,通过曝光、显影、固化等构图工艺形成预设的薄膜图案。第一金属线路212可以先采用沉积工艺、溅射工艺或者电镀工艺先形成一层金属薄膜层,然后采用刻蚀等构图工艺对上述金属薄膜层进行图案化形成。第一金属线路212的材料可以包括金属铜、金属铝等导电材料。可以理解的是,图13中的第一金属线路212具有多个隔开的部分,该图仅仅为图中位置剖视图的状态,实际上在其他位置第一金属线路212是连接的。当然,在其他实施例中,第一金属线路212的具体形状可根据需要设计。
在制作第一重布线层21的过程中同时形成第一导热件213,以使第一导热件213与第一金属线路212连接且至少部分外露在第一重布线层21的顶面214。本实施例中,第一导热件213具有多个,多个第一导热件213间隔设置,且多个第一导热件213露出第一重布线层21的表面与顶面214平齐。第一导热件213的制作工艺和第一金属线路212的制作工艺相同,第一导热件213的材料也和第一金属线路212相同。可以理解的是,第一导热件213嵌设于第一重布线层21内,即第一导热件213不占用额外的空间,不会因为增加第一导热件213而使封装结构20的尺寸变大。且在形成第一重布线层21的同时形成第一导热件213,减少制作工艺,提高封装结构20的生产效率,降低了封装结构20的生产成本。当然,在其他实施例中,多个第一导热件213露出第一重布线层21的部分凸出于第一重布线层21的顶面214。
在制作第一重布线层21之后,在第一重布线层21上形成第一连接柱216。具体的,在部分露出第一重布线层21的顶面214的第一金属线路212上形成第一连接柱216,以使第一连接柱216与第一金属线路212连接。第一连接柱216具体形成工艺为涂胶、光刻、显影和电镀。第一连接柱216的材质和第一金属线路212相同。第一连接柱216用于将第一金属线路212和后续工艺中形成的第二重布线的第二金属线路242连接,同时还能将第一金属线路212的热量导到其他部分,进一步提高封装结构20的散热效果。
S220:通过第一封装体23将第一芯片22封装至第一重布线层21,使得第一芯片22的背面背对第一重布线层21,且通过第一传热件41连接至第一封装体23的表面,其中,第一芯片22的正面用于传递信号,第一芯片22的背面为与第一芯片22的正面相背设置的无源面。
具体的,请参阅图14-图15,通过第一封装体23将第一芯片22封装至第一重布线层21之前,在第一芯片22的背面制作阻隔层31,在阻隔层31背向第一芯片22的表面形成多个间隔的第一传热件41,在阻隔层31背向第一芯片22的表面形成保护层44,保护层44包覆第一传热件41,在保护层44内形成金属体43,金属体43与多个第一传热件41连接,金属体43远离第一传热体的部分露出保护层44。将第一芯片22的引脚221与部分露出顶面214的第一金属线路212连接,然后用第一封装体23封装第一芯片22,对第一封装体23背向第 一重布线层21的表面进行研磨,以使保护层44背向第一芯片22的表面露出第一封装体23的表面。本实施例中,第一芯片22为存储芯片。第一传热件41例如为铜柱或其他金属柱,可以通过电镀等工艺形成。金属体43可以为金属薄层,或者为金属网层。保护层44的材料为绝缘树脂材料,例如为如聚酰亚胺、苯并环丁烯和环氧树脂等中的一种。当然,在其他实施例中,第一芯片22还可以是CPU芯片、射频驱动芯片或者其他处理器的芯片等有源的电子器件。第一传热件41还可以是其他形状。
本实施例中,第一芯片22的热量从背面通过多个第一传热件41传递出去,多个第一传热件41能保证热量的有效传递,通过金属体43将多个第一传热件41连接一方面了增大了第一芯片22的散热面积,另一方面多个第一传热件41通过金属体43能与后续形成的导热件连接更牢固,以使第一芯片22在垂直方向上的具有很好的散热效果,提高了第一芯片22的电性能,进而提高了封装结构20的电性能。同时,在第一芯片22封装之前,通过保护层44固定多个第一传热件41和金属体43,以使第一传热件41和金属体43不会在封装第一芯片22的过程中发生歪斜,从而进一步保证了第一芯片22的散热效果。阻隔层31用于隔离第一芯片22和第一传热件41,以避免第一传热件41中的金属材料扩散到第一芯片22背面的半导体材料(例如硅)中影响半导体的导电性能,进而影响第一芯片22的电性能,甚至导致第一芯片22失效。阻隔层31的材料例如为氮化硅。当然,在其他实施例中,阻隔层31的材料还可以是其他可以阻止第一传热件41中的材料扩散到第一芯片22中的材料。
当然,在其他实施例中,还可以通过第一封装体23将第一芯片22封装至第一重布线层21之前,在第一芯片22的背面制作阻隔层31,在阻隔层31背向第一芯片22的表面形成多个间隔的第一传热件41,将第一芯片22的引脚221与部分露出顶面214的第一金属线路212连接,然后用第一封装体23封装第一芯片22,对第一封装体23背向第一重布线层21的表面进行研磨,以使多个第一传热件41背向第一芯片22的表面露出第一封装体23的表面。第一芯片22的热量从背面通过形成于第一芯片22背面一侧的多个第一传热件41传递出去,多个第一传热件41能保证热量的有效传递,以使第一芯片22在垂直方向上的具有很好的散热效果,提高了第一芯片22的电性能,进而提高了封装结构20的电性能。
当然,在其他实施例中,还可以通过第一封装体23将第一芯片22封装至第一重布线层21之前,在第一芯片22的背面制作阻隔层31,在阻隔层31背向第一芯片22的表面形成多个间隔的第一传热件41,在阻隔层31背向第一芯片22的表面形成保护层44,保护层44包覆第一传热件41,第一传热件41远离第一芯片22的端部露出保护层44,将第一芯片22的引脚221与部分露出顶面214的第一金属线路212连接,然后用第一封装体23封装第一芯片22,对第一封装体23背向第一重布线层21的表面进行研磨,以使保护层44背向第一芯片22的表面露出第一封装体23的表面。第一芯片22的热量从背面通过形成于第一芯片22背面一侧的多个第一传热件41传递出去,多个第一传热件41能保证热量的有效传递,以使第一芯片22在垂直方向上的具有很好的散热效果,提高了第一芯片22的电性能,进而提高了封装结构20的电性能。同时,在第一芯片22封装之前,通过保护层44固定多个第一传热件41,以使第一传热件41不会在封装第一芯片22的过程中发生歪斜,从而进一步保证了第一芯片22的散热效果。
当然,在其他实施例中,第一传热件41在第一封装体23封装第一芯片22之后形成。具体的,通过第一封装体23将第一芯片22封装至第一重布线层21之前,在第一芯片22的背面制作阻隔层31,将第一芯片22的引脚221与部分露出顶面214的第一金属线路212连接, 然后用第一封装体23封装第一芯片22,在第一封装体23上形成多个间隔的开口以露出第一芯片22的背面的阻隔层31,在开口中形成第一传热件41。
当然,在其他实施例中,第一传热件41在第一封装体23封装第一芯片22之后形成。具体的,通过第一封装体23将第一芯片22封装至第一重布线层21之前,在第一芯片22的背面制作阻隔层31,将第一芯片22的引脚221与部分露出顶面214的第一金属线路212连接,然后用第一封装体23封装第一芯片22,在第一封装体23上形成第一开口,在第一开口底壁形成多个间隔的第二开口,第二开口露出第一芯片22的背面一侧,在第一开口和第二开口中形成第一传热件41。以形成异形第一传热件41,增大第一传热件41的散热面,以使第一芯片22在垂直方向上的具有很好的散热效果,提高了第一芯片22的电性能,进而提高了封装结构20的电性能。
在通过第一封装体23将第一芯片22封装至第一重布线层21的过程中,第一封装体23同时封装第一连接柱216,然后对第一封装体23背向第一重布线层21的表面进行研磨,以使第一连接柱216部分外露至第一封装体23的表面。第一连接柱216露出第一封装体23的表面以便于与其他结构电连接。本实施例中,第一封装体23的材料为绝缘的树脂材料,例如为环氧树脂材料。
S230:在第一封装体23上制作第二重布线层24。
具体的,请参阅图16,在第一封装体23背向第一芯片22的表面制作第二重布线层24,第二重布线层24包括第二绝缘介质241和内设于第二绝缘介质241的第二金属线路242。本实施例中,第二绝缘介质241和第二金属线路242可以通过构图工艺形成,以使第二重布线层24的第一金属线路212一部分露出第二重布线层24朝向第一芯片22的表面,一部分露出第二重布线层24背向第一芯片22的表面。本实施例中的第二重布线层24的制作工艺和第一重布线层21的制造工艺相同,且采用的材料也相同。可以理解的是,图16中的第二金属线路242仅仅为图中位置剖视图的状态。当然,在其他实施例中,第二金属线路242的具体形状可根据需要设计。
在制作第二重布线层24的过程中同时形成第二导热件243,以使第二导热件243与第二金属线路242连接且至少部分外露在第二重布线层24朝向和背向第一芯片22的表面。本实施例中,第二导热件243具有多个,多个第二导热件243露出第二重布线层24的表面与第二重布线层24朝向第一芯片22的表面平齐。露出第二重布线层24朝向第一芯片22的表面的第二导热件243连接金属体43,第二导热件243用于通过金属体43连接第一传热件41,从而将第一芯片22传递到的第一传热件41的热量通过第二导热件243传递到第二金属线路242并通过第二金属线路242传导出去,以使第一芯片22在垂直方向上的具有很好的散热效果,提高了第一芯片22的电性能,进而提高了封装结构20的电性能。
本实施例中,第二导热件243的制作工艺和第二金属线路242的制作工艺相同,第二导热件243的材料也和第二金属线路242相同。可以理解的是,第二导热件243嵌设于第二重布线层24内,即第二导热件243不占用额外的空间,不会因为增加第二导热件243而使封装结构20的尺寸变大。且在形成第二重布线层24的同时形成第二导热件243,减少制作工艺,提高封装结构20的生产效率,降低了封装结构20的生产成本。当然,在其他实施例中,多个第二导热件243露出第二重布线层24的部分凸出于第二重布线层24的表面。露出第二重布线层24朝向第一芯片22的表面的第二导热件243连接第一传热件41。
在制作第二重布线层24之后,在第二重布线层24上形成第二连接柱244。具体的,在 部分露出第二重布线层24背向第一芯片22的表面的第二金属线路242上形成第二连接柱244,以使第二连接柱244与第二金属线路242连接。第二连接柱244具体形成工艺为涂胶、光刻、显影和电镀。第二连接柱244的材质和第二金属线路242相同。第二连接柱244用于将第二金属线路242和后续工艺中形成的第三重布线的第三金属线路272连接,同时还能将第二金属线路242的热量导到其他部分,进一步提高封装结构20的散热效果。
S240:通过第二封装体26将第二芯片25封装至第二重布线层24,第二芯片25的背面背对第二重布线层24,且通过第二传热件42连接至第二封装体26的表面,其中,第二芯片25的正面用于传递信号,第二芯片25的背面为与第二芯片25的正面相背设置的无源面。
具体的,请参阅图17,通过第二封装体26将第二芯片25封装至第二重布线层24之前,在第二芯片25的背面制作阻隔层33,在阻隔层33背向第二芯片25的表面形成多个间隔的第二传热件42,在阻隔层33背向第二芯片25的表面形成保护层46,保护层46包覆第二传热件42,在保护层46内形成金属体45,金属体45与多个第二传热件42连接,金属体45远离第二传热件42的部分露出保护层46。将第二芯片25的引脚251与部分露出顶面214的第二金属线路242连接,然后用第二封装体26封装第二芯片25,对第二封装体26背向第二重布线层24的表面进行研磨,以使保护层46背向第二芯片25的表面露出第二封装体26的表面。本实施例中,第二芯片25为CPU芯片。第二传热件42例如为铜柱或其他金属柱,可以通过电镀等工艺形成。金属体45可以为金属薄层,或者为金属网层。保护层46的材料为绝缘树脂材料,例如为如聚酰亚胺、苯并环丁烯和环氧树脂等中的一种。当然,在其他实施例中,第二芯片25还可以是存储芯片、射频驱动芯片或者其他处理器的芯片等有源的电子器件。第二传热件42还可以是其他形状。
本实施例中,露出第二重布线层24背向第一芯片22的表面的第二导热件243与第二封装体26连接,以将第二封装体26中热量通过第二金属线路242传导到外界,有效提高第二芯片25的散热效果。第二芯片25的热量还从背面通过多个第二传热件42传递出去,多个第二传热件42能保证热量的有效传递,通过金属体45将多个第二传热件42连接一方面了增大了第二芯片25的散热面积,另一方面多个第二传热件42通过金属体45能与后续形成的导热件连接更牢固,以使第二芯片25在垂直方向上的具有很好的散热效果,提高了第二芯片25的电性能,进而提高了封装结构20的电性能。同时,在第二芯片25封装之前,通过保护层46固定多个第二传热件42和金属体45,以使第二传热件42和金属体45不会在封装第二芯片25的过程中发生歪斜,从而进一步保证了第二芯片25的散热效果。阻隔层33用于隔离第二芯片25和第二传热件42,以避免第二传热件42中的金属材料扩散到第二芯片25背面的半导体材料(例如硅)中影响半导体的导电性能,进而影响第二芯片25的电性能,甚至导致第二芯片25失效。阻隔层33的材料例如为氮化硅。当然,在其他实施例中,阻隔层33的材料还可以是其他可以阻止第二传热件42中的材料扩散到第二芯片25中的材料。
当然,在其他实施例中,第二传热件42的形成方式及结构还有多种实施方式,包括不限于第一传热件41在S220中罗列的实施方式,且第二传热件42的任一形成方式及结构可以与第二传热件42的任一形成方式及结构进行组合形成不同的方案。
在通过第二封装体26将第二芯片25封装至第二重布线层24的过程中,第二封装体26同时封装第二连接柱244,然后对第二封装体26背向第二重布线层24的表面进行研磨,以使第二连接柱244部分外露至第二封装体26的表面。第二连接柱244露出第二封装体26的表面以便于与其他结构电连接。本实施例中,第二封装体26的材料和第一封装体23的材料 相同。
S250:在第二封装体26上制作第三重布线层27,在第一重布线层21背向第一芯片22的表面形成焊球28。
具体的,请参阅图18,在第二封装体26背向第二芯片25的背面制作第三重布线层27,第三重布线层27包括第三绝缘介质271和设于第三绝缘介质271的第三金属线路272。本实施例中,第三绝缘介质271和第三金属线路272可以通过构图工艺形成,以使第三重布线层27的第三金属线路272一部分露出第三重布线层27朝向第二芯片25的表面并与第二连接柱244连接,一部分露出第三重布线背向第二芯片25的表面。本实施例中的第三重布线层27的制作工艺和第一重布线层21的制造工艺相同,且采用的材料也相同。可以理解的是,图18中的第三金属线路272的设置方式仅仅为本实施例中列举的一种。当然,在其他实施例中,第三金属线路272 9的具体形状可根据需要设计。
在制作第三重布线层27的过程中同时形成第三导热件273,以使第三导热件273与第三金属线路272连接且至少部分外露在第三重布线层27朝向第二芯片25的表面。本实施例中,第三导热件273具有多个,多个第三导热件273露出第三重布线层27的表面与第三重布线层27朝向第二芯片25的表面平齐。第三导热件273连接第二芯片25背面一侧的金属体45,第三导热件273用于通过金属体45连接第二传热件42,从而将第二芯片25传递到的第二传热件42的热量通过第三导热件273传递到第三金属线路272并通过第三金属线路272传导出去,以使第二芯片25在垂直方向上的具有很好的散热效果,提高了第二芯片25的电性能,进而提高了封装结构20的电性能。
本实施例中,第三导热件273的制作工艺和第三金属线路272的制作工艺相同,第三导热件273的材料也和第三金属线路272相同。可以理解的是,第三导热件273嵌设于第三重布线层27内,即第三导热件273不占用额外的空间,不会因为增加第三导热件273而使封装结构20的尺寸变大。且在形成第三重布线层27的同时形成第三导热件273,减少制作工艺,提高封装结构20的生产效率,降低了封装结构20的生产成本。当然,在其他实施例中,多个第三导热件273露出第三重布线层27的部分凸出于第三重布线层27的表面。露出第三重布线层27朝向第二芯片25的表面的第三导热件273连接第二传热件42。
去除载板50,在第三重布线层27背向第二芯片25的表面形成连接接口29,连接接口29与部分露出第三重布线层27背向第二芯片25的表面的第三金属线路272连接,连接接口29用于与其他电子模块连接及实现封装结构20接地。另一部分露出第三重布线层27背向第二芯片25的表面的第三金属线路272用于将第一芯片22和第二芯片25的热量传导外界,以提高封装结构20的散热效果。连接接口29的设置方式不限于图18所示。
在第一重布线层21背向第一芯片22的表面形成焊球28。具体的,焊球28通过焊盘35连接在露出第一重布线层21底面215的第一金属线路215上,以形成封装结构20。焊球28用于与其他电子元件电连接,同时还能将第一芯片22和第二芯片25传递到第三金属线路272的热量通过焊球28向外界传递。以提高封装结构20的散热效果。焊球28的设置方式不限于图18所示。
本申请实施例的制备方法,通过将第一传热件41设于第一芯片22的背面一侧,且第一传热件41露出第一封装体23与第二重布线层24连接,和通过将第二传热件42设于第二芯片25的背面一侧,且第二传热件42露出第二封装体26与第三重布线层27连接。即,第一芯片22和第二芯片25的热量分别通过第一传热件41和第二传热件42传递到第二重布线层 24和第三重布线层27进行散热,从而有效将第一芯片22和第二芯片25的热量从背面导出到封装结构20外,以使第一芯片22和第二芯片25在垂直方向上的具有很好的散热效果,提高了第一芯片22和第二芯片25的电性能,进而提高了封装结构20的电性能。同时,由于本申请的制备方法解决了芯片在垂直方向上的散热问题,封装结构20还可以实现两个芯片以上的多层芯片的堆叠,从而实现散热芯片要求较高的芯片的多层堆叠,保证芯片散热效果的同时有效提高封装结构20的集成度。
本申请提供的封装结构20的制备方法中,不管第一芯片22正装至第一重布线层21,或者倒装至第一重布线层21,均通过将导热结构连接在第一芯片22的背面,并通过导热结构(第一导热件213或第一传热件41)将第一芯片22散发的热传导至外部(传导的路径可以为第一重布线层21的一侧,也可以通过传导至第一芯片22背离第一重布线层21的第一封装体23的表面)。不管第二芯片25正装至第二重布线层24,或者倒装至第二重布线层24,均通过将导热结构连接在第二芯片25的背面,并通过导热结构将第二芯片25散发的热传导至外部(传导的路径可以为第二重布线层24的一侧,也可以通过传导至第二芯片25背离第二重布线层24的第二封装体26的表面)。
以上所述,仅为本申请的具体实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应以所述权利要求的保护范围为准。

Claims (44)

  1. 一种封装结构,其特征在于,包括第一重布线层和第一芯片,所述第一重布线层包括第一金属线路和与所述第一金属线路连接的第一导热件,所述第一导热件至少部分露出所述第一重布线层的顶面,所述第一芯片的背面一侧设于所述顶面,并与所述第一导热件连接。
  2. 根据权利要求1所述的封装结构,其特征在于,所述第一芯片的背面设有阻隔层,所述阻隔层连接在所述背面和所述第一导热件之间。
  3. 根据权利要求2所述的封装结构,其特征在于,所述阻隔层和所述第一导热件之间设有粘接层,所述粘接层将所述第一芯片粘接至所述顶面。
  4. 根据权利要求3所述的封装结构,其特征在于,所述封装结构包括第一封装体,所述第一封装体封装于所述第一芯片上,所述第一芯片的正面的引脚露出所述第一封装体。
  5. 根据权利要求4所述的封装结构,其特征在于,所述封装结构包括第二重布线层,所述第二重布线层设于所述第一封装体上,所述第二重布线层包括第二金属线路和与所述第二金属线路连接的第二导热件,所述第二导热件露出所述第二重布线层背向所述第一芯片的表面,所述第二金属线路部分露出第二重布线层朝向所述第一芯片的表面并与所述第一芯片的引脚连接。
  6. 根据权利要求5所述的封装结构,其特征在于,所述封装结构包括第一连接柱,所述第一连接柱设于所述第一封装体内且连接在所述第一金属线路和所述第二金属线路之间。
  7. 根据权利要求6所述的封装结构,其特征在于,所述封装结构包括第二芯片和第二封装体,所述第二芯片的背面一侧设于所述第二重布线层上并与所述第二导热件连接,所述第二封装体封装于所述第二芯片上,所述第二芯片的引脚露出所述第二封装体。
  8. 根据权利要求7所述的封装结构,其特征在于,所述第一芯片为存储芯片,所述第二芯片为CPU芯片。
  9. 根据权利要求8所述的封装结构,其特征在于,所述封装结构包括第三重布线层和焊球,所述第三重布线层设于所述第二封装体上,所述焊球设于所述第三重布线层上,所述第三重布线层的第三金属线路连接在所述第二芯片的引脚和所述焊球之间。
  10. 根据权利要求9所述的封装结构,其特征在于,所述封装结构包括第二连接柱,所述第二连接柱设于所述第二封装体中,并连接在所述第二金属线路和所述第三金属线路之间。
  11. 一种封装结构,其特征在于,包括第一重布线层、第一芯片、第一传热件和第一封装体,所述第一重布线层包括第一金属线路,所述第一金属线路部分露出所述第一重布线层的顶面,所述第一芯片的正面的引脚设于所述顶面并与所述第一金属线路连接,所述第一传热件设于所述第一芯片的背面一侧,所述第一封装体封装与所述第一芯片上,所述第一传热件露出所述第一封装体的表面。
  12. 根据权利要求11所述的封装结构,其特征在于,所述封装结构还包括金属体,所述第一传热件为多个,多个所述第一传热件间隔设置,所述金属体连接多个所述第一传热件背向所述第一芯片的一端,所述第一传热件通过所述金属体露出所述第一封装体。
  13. 根据权利要求11或12所述的封装结构,其特征在于,所述第一芯片的背面设有阻隔层,所述阻隔层连接在所述背面和所述第一传热件之间。
  14. 根据权利要求13所述的封装结构,其特征在于,所述封装结构包括第二重布线层,所述第二重布线层设于所述第一封装体上,所述第二重布线层包括第二金属线路和与所述第二金属线路连接的第二导热件,所述第二导热件露出所述第二重布线层朝向所述第一芯片的 表面并与所述金属体或所述第一传热件连接,所述第二金属线路部分露出第二重布线层背向所述第一芯片的表面。
  15. 根据权利要求14所述的封装结构,其特征在于,所述封装结构包括第一连接柱,所述第一连接柱设于所述第一封装体内且连接在所述第一金属线路和所述第二金属线路之间。
  16. 根据权利要求15所述的封装结构,其特征在于,所述封装结构包括第二芯片、第二封装体和第二传热件,所述第二芯片的正面的引脚设于所述第二重布线层上并与所述第二金属线路连接,所述第二传热件设于所述第二芯片的背面一侧,所述第二封装体封装于所述第二芯片上,所述第二传热件露出所述第二封装体的表面。
  17. 根据权利要求16所述的封装结构,其特征在于,所述第一芯片为存储芯片,所述第二芯片为CPU芯片。
  18. 根据权利要求17所述的封装结构,其特征在于,所述封装结构包括第三重布线层和焊球,所述第三重布线层设于所述第二封装体上,所述第三重布线层中与第三金属线路连接的第三导热件与所述第二传热件连接,所述焊球设于所述第一重布线层背向所述第一芯片的表面并与所述第一金属线路连接。
  19. 根据权利要求18所述的封装结构,其特征在于,所述封装结构包括第二连接柱,所述第二连接柱设于所述第二封装体中,并连接在所述第二金属线路和所述第三金属线路之间。
  20. 一种电子设备,其特征在于,包括如权利要求1-19任一项所述的封装结构。
  21. 一种封装结构的制备方法,其特征在于,所述制备方法包括:
    制作第一重布线层,所述第一重布线层内设第一金属线路;
    将第一芯片连接至所述第一重布线层,使得所述第一芯片的背面面对所述第一重布线层,且通过第一导热件连接所述第一金属线路;或者,通过第一封装体将所述第一芯片封装至所述第一重布线层,使得所述第一芯片的背面背对所述第一重布线层,且通过第一传热件连接至所述第一封装体的表面。
  22. 根据权利要求21所述的制备方法,其特征在于,所述第一导热件为在制作所述第一重布线层的过程中形成在所述第一重布线层内,且与所述第一金属线路连接,所述第一导热件至少部分外露在所述第一重布线层的顶面,将所述第一芯片连接至所述第一重布线层的过程中,所述第一芯片的背面面对所述顶面。
  23. 如权利要求22所述的制备方法,其特征在于,所述第一导热件为金属材质,将所述第一芯片连接至所述第一重布线层之前,在所述第一芯片的背面制作阻隔层,所述阻隔层将所述背面和所述第一导热件隔开。
  24. 如权利要求23所述的制备方法,其特征在于,所述阻隔层与所述第一重布线层的顶面之间通过粘接层固定连接。
  25. 如权利要求24所述的制备方法,其特征在于,将所述第一芯片连接至所述第一重布线层之后,通过第一封装体将所述第一芯片封装至所述第一重布线层,所述第一芯片的正面的引脚露出所述第一封装体的表面。
  26. 如权利要求25所述的制备方法,其特征在于,在制作所述第一重布线层之后,在所述第一重布线层上形成第一连接柱,所述第一连接柱与所述第一金属线路连接,在通过所述第一封装体将所述第一芯片封装至所述第一重布线层的过程中,所述第一封装体同时封装所述第一连接柱,所述第一连接柱部分外露至所述第一封装体的表面。
  27. 如权利要求26所述的制备方法,其特征在于,所述制备方法还包括在所述第一封装 体上制作第二重布线层,所述第二重布线层内设第二金属线路和与所述第二金属线路连接的第二导热件,所述第二导热件露出所述第二重布线层背向所述第一芯片的表面,所述第二金属线路部分露出第二重布线层朝向所述第一芯片的表面并与所述第一芯片的引脚和所述第一连接柱连接。
  28. 如权利要求27所述的制备方法,其特征在于,所述制备方法还包括将第二芯片连接至所述第二重布线层,使得所述第二芯片的背面面对所述第二重布线层,且通过第二导热件连接所述第二金属线路。
  29. 根据权利要求28所述的封装结构,其特征在于,所述第一芯片为存储芯片,所述第二芯片为CPU芯片。
  30. 如权利要求29所述的制备方法,其特征在于,将所述第二芯片连接至所述第二重布线层之后,通过第二封装体将所述第二芯片封装至所述第二重布线层,所述第二芯片的正面的引脚露出所述第二封装体的表面。
  31. 如权利要求30所述的制备方法,其特征在于,在制作所述第二重布线层之后,在所述第二重布线层上形成第二连接柱,所述第二连接柱与所述第二金属线路连接,在通过所述第二封装体将所述第二芯片封装至所述第二重布线层的过程中,所述第二封装体同时封装所述第二连接柱,所述第二连接柱部分外露至所述第二封装体的表面。
  32. 如权利要求31所述的制备方法,其特征在于,所述制备方法还包括在所述第二封装体上制作第三重布线层,在所述第三重布线层上形成焊球,所述第三重布线层的第三金属线路连接所述第二芯片的引脚和所述第二连接柱。
  33. 根据权利要求21所述的制备方法,其特征在于,在通过所述第一封装体将所述第一芯片封装至所述第一重布线层之前,在所述第一芯片的背面一侧形成多个间隔的所述第一传热件,在所述第一封装体封装所述第一芯片之后,所述第一芯片的背面通过多个所述第一传热件连接至所述第一封装体的表面。
  34. 根据权利要求21所述的制备方法,其特征在于,在通过所述第一封装体将所述第一芯片封装至所述第一重布线层之前,在所述第一芯片的背面一侧形成多个间隔的所述第一传热件,在所述第一芯片的背面一侧形成保护层,所述保护层包覆所述第一传热件,所述第一传热件远离所述第一芯片的端部露出所述保护层,在所述第一封装体封装所述第一芯片之后,所述保护层背向所述第一芯片的表面露出所述第一封装体的表面。
  35. 根据权利要求21所述的制备方法,其特征在于,在通过所述第一封装体将所述第一芯片封装至所述第一重布线层之前,在所述第一芯片的背面一侧形成多个间隔的所述第一传热件,在所述第一芯片的背面一侧形成保护层,所述保护层包覆所述第一传热件,在所述保护层内形成金属体,所述金属体与多个所述第一传热件连接,所述金属体远离所述第一传热体的部分露出所述保护层,在所述第一封装体封装所述第一芯片之后,所述保护层背向所述第一芯片的表面露出所述第一封装体的表面。
  36. 根据权利要求21所述的制备方法,其特征在于,在所述第一封装体封装所述第一芯片之后,在所述第一封装体上形成多个间隔的开口以露出所述第一芯片的背面一侧,在所述开口中形成所述第一传热件。
  37. 根据权利要求21所述的制备方法,其特征在于,在所述第一封装体封装所述第一芯片之后,在所述第一封装体上形成第一开口,在所述第一开口底壁形成多个间隔的第二开口,所述第二开口露出所述第一芯片的背面一侧,在所述第一开口和所述第二开口中形成所述第 一传热件。
  38. 根据权利要求33-37任一项所述的制备方法,其特征在于,所述第一传热件为金属材质,在所述第一芯片的背面一侧形成所述第一传热件之前,在所述第一芯片的背面制作阻隔层,所述阻隔层将所述背面和所述第一传热件隔开。
  39. 根据权利要求38所述的制备方法,其特征在于,在制作所述第一重布线层之后,在所述第一重布线层上形成第一连接柱,所述第一连接柱与所述第一金属线路连接,在通过所述第一封装体将所述第一芯片封装至所述第一重布线层的过程中,所述第一封装体同时封装所述第一连接柱,所述第一连接柱部分外露至所述第一封装体的表面。
  40. 根据权利要求39所述的制备方法,其特征在于,所述制备方法还包括在所述第一封装体上制作第二重布线层,所述第二重布线层内设第二金属线路和与所述第二金属线路连接的第二导热件,所述第二导热件露出所述第二重布线层朝向所述第一芯片的表面并与所述第一传热件或所述金属体连接,所述第二金属线路部分露出第二重布线层背向所述第一芯片的表面。
  41. 根据权利要求40所述的制备方法,其特征在于,所述制备方法还包括通过第二封装体将第二芯片封装至所述第二重布线层,使得所述第二芯片的引脚与所述第二金属线路连接,所述第二芯片的背面背对所述第二重布线层,且通过第二传热件连接至所述第二封装体的表面。
  42. 根据权利要求41所述的封装结构,其特征在于,所述第一芯片为存储芯片,所述第二芯片为CPU芯片。
  43. 根据权利要求42所述的制备方法,其特征在于,在制作所述第二重布线层之后,在所述第二重布线层上形成第二连接柱,所述第二连接柱与所述第二金属线路连接,在通过所述第二封装体将所述第二芯片封装至所述第二重布线层的过程中,所述第二封装体同时封装所述第二连接柱,所述第二连接柱部分外露至所述第二封装体的表面。
  44. 根据权利要求43所述的制备方法,其特征在于,所述制备方法还包括在所述第二封装体上制作第三重布线层,在所述第一重布线层背向所述第一芯片的表面形成焊球,所述第三重布线层的第三金属线路连接所述第二传热件和所述第二连接柱。
PCT/CN2020/074879 2020-02-12 2020-02-12 封装结构及其制备方法和电子设备 WO2021159306A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202080096220.2A CN115066746A (zh) 2020-02-12 2020-02-12 封装结构及其制备方法和电子设备
PCT/CN2020/074879 WO2021159306A1 (zh) 2020-02-12 2020-02-12 封装结构及其制备方法和电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/074879 WO2021159306A1 (zh) 2020-02-12 2020-02-12 封装结构及其制备方法和电子设备

Publications (1)

Publication Number Publication Date
WO2021159306A1 true WO2021159306A1 (zh) 2021-08-19

Family

ID=77291971

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/074879 WO2021159306A1 (zh) 2020-02-12 2020-02-12 封装结构及其制备方法和电子设备

Country Status (2)

Country Link
CN (1) CN115066746A (zh)
WO (1) WO2021159306A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114334945A (zh) * 2021-12-01 2022-04-12 长电科技管理有限公司 一种封装结构及制作方法
CN116130451A (zh) * 2023-04-17 2023-05-16 深圳宏芯宇电子股份有限公司 芯片封装结构及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1870253A (zh) * 2006-06-19 2006-11-29 上海集成电路研发中心有限公司 降低半导体器件发热的散热方法、制造方法及相应半导体器件
CN201307606Y (zh) * 2008-12-10 2009-09-09 潮州三环(集团)股份有限公司 一种新型陶瓷封装基座
US20120299173A1 (en) * 2011-05-26 2012-11-29 Futurewei Technologies, Inc. Thermally Enhanced Stacked Package and Method
CN208819865U (zh) * 2018-08-17 2019-05-03 深南电路股份有限公司 开关管及其芯片组件
CN110299329A (zh) * 2018-03-21 2019-10-01 华为技术有限公司 一种封装结构及其制作方法、电子设备
CN110767614A (zh) * 2019-10-10 2020-02-07 华为技术有限公司 封装结构和电子装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1870253A (zh) * 2006-06-19 2006-11-29 上海集成电路研发中心有限公司 降低半导体器件发热的散热方法、制造方法及相应半导体器件
CN201307606Y (zh) * 2008-12-10 2009-09-09 潮州三环(集团)股份有限公司 一种新型陶瓷封装基座
US20120299173A1 (en) * 2011-05-26 2012-11-29 Futurewei Technologies, Inc. Thermally Enhanced Stacked Package and Method
CN110299329A (zh) * 2018-03-21 2019-10-01 华为技术有限公司 一种封装结构及其制作方法、电子设备
CN208819865U (zh) * 2018-08-17 2019-05-03 深南电路股份有限公司 开关管及其芯片组件
CN110767614A (zh) * 2019-10-10 2020-02-07 华为技术有限公司 封装结构和电子装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114334945A (zh) * 2021-12-01 2022-04-12 长电科技管理有限公司 一种封装结构及制作方法
CN114334945B (zh) * 2021-12-01 2024-03-08 长电科技管理有限公司 一种封装结构及制作方法
CN116130451A (zh) * 2023-04-17 2023-05-16 深圳宏芯宇电子股份有限公司 芯片封装结构及其制备方法

Also Published As

Publication number Publication date
CN115066746A (zh) 2022-09-16

Similar Documents

Publication Publication Date Title
TWI667762B (zh) 半導體封裝中的重佈線層及其形成方法
TWI713129B (zh) 半導體元件及其形成方法
KR102131759B1 (ko) 통합 팬-아웃 패키지 및 통합 팬-아웃 패키지 형성 방법
TWI747127B (zh) 晶片封裝結構及其製造方法
US9041205B2 (en) Reliable microstrip routing for electronics components
TWI773404B (zh) 半導體封裝
US20180233441A1 (en) PoP Device
WO2017114323A1 (zh) 封装结构、电子设备及封装方法
TW201911476A (zh) 半導體封裝及其形成方法
US11515290B2 (en) Semiconductor package
TW201903994A (zh) 半導體封裝
CN116169110A (zh) 一种芯片及封装方法
TW202115836A (zh) 多晶片封裝件及其製造方法
KR20150094135A (ko) 반도체 패키지 및 이의 제조방법
TWI723885B (zh) 半導體封裝
TWI585906B (zh) 超薄封裝上封裝PoP之封裝
TWI738445B (zh) 半導體封裝結構
TWI531283B (zh) 連接基板及層疊封裝結構
WO2021159306A1 (zh) 封装结构及其制备方法和电子设备
TW202109794A (zh) 半導體封裝
WO2016165074A1 (zh) 一种芯片
JP2022023830A (ja) 半導体パッケージにおける放熱及びその形成方法
TWI753587B (zh) 封裝結構及其形成方法
TWI734401B (zh) 電子封裝件
US20230253285A1 (en) Package structure and method for manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20918278

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20918278

Country of ref document: EP

Kind code of ref document: A1