CN110337719B - 引线框架和集成电路连接布置 - Google Patents

引线框架和集成电路连接布置 Download PDF

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Publication number
CN110337719B
CN110337719B CN201880012873.0A CN201880012873A CN110337719B CN 110337719 B CN110337719 B CN 110337719B CN 201880012873 A CN201880012873 A CN 201880012873A CN 110337719 B CN110337719 B CN 110337719B
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electrical contact
low
front side
electrically coupled
semiconductor die
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CN110337719A (zh
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S.L.涂
M.A.斯图伯
B.塔斯巴斯
S.B.莫林
R.蒋
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Silanna Asia Pte Ltd
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Silanna Asia Pte Ltd
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Abstract

一种半导体封装包括：引线框架，所述引线框架具有周边封装引线和电连接器；单个半导体管芯，所述单个半导体管芯具有后侧电触点和前侧电触点；导电夹(“夹”)；以及顶部半导体管芯，所述顶部半导体管芯具有前侧和后侧。所述单个半导体管芯包括两个或更多个晶体管。所述半导体管芯的所述前侧电触点中的两者或更多者电耦合并被物理安装到所述引线框架的相应的电触点。所述夹的电接触表面电耦合并被物理安装到所述引线框架的电连接器。所述夹的另一电接触表面被物理安装并电耦合到所述半导体管芯的所述后侧电触点。所述顶部半导体管芯的所述后侧被物理安装到所述导电夹的另一表面。

Description

引线框架和集成电路连接布置
相关申请的交叉引用
本申请要求在2017年8月17日提交的标题为“Leadframe and IntegratedCircuit Connection Arrangement”的美国非临时专利申请No.15/680,034的优先权；所述美国非临时专利申请要求在2017年2月20日提交的标题为“Backside Contact IntegratedLaterally Diffused MOS Apparatus and Methods”的美国临时申请No.62/461,117的权益，所有所述申请以引用的方式并入以用于所有目的。
背景技术
半导体电力装置是通常用作电力电子器件电路中的开关或整流器的专用装置。半导体电力装置的特征在于它们承受与高功率操作相关联的高电压和大电流以及高温的能力。举例来说，开关式电压调节器通常包括一直以同步的方式接通和关断来调节电压的两个电力装置。所述电力装置在此情形下需要吸收接通状态下的系统级电流、承受关断状态下的电源的全电位，并且消散大量的热。理想的电力装置能够在高功率状况下操作、可以在接通状态与关断状态之间快速切换，并且展现出低热阻和接通状态电阻。
典型的半导体电力装置封装包括一组分立的功率晶体管，所述功率晶体管中的每一者被制造于其自身的相应的半导体管芯上。单独的管芯被囊封于具有引线框架的绝缘的模具化合物中，所述引线框架为形成于半导体管芯中的单独的装置或集成电路提供外部电连接。
高功率半导体应用，例如电力开关和电力处置，需要半导体管芯衬垫与封装引线之间的电连接，所述电连接的特征在于高电流载运能力、低电阻和/或低电感。出于这些原因，已经努力使用由铜、铜合金或铝组成的导电带或预先形成的夹而不是接合线来用于半导体封装内的高功率电连接。然而，导电夹在物理上较大且难以在芯片上高精度地机械定位。
在典型的半导体电力装置封装中，每个分立的功率晶体管半导体管芯电连接到所述封装，所述封装具有单个前侧高电流封装引线、用于栅极控制的单个前侧低电流封装引线，以及到封装焊盘的后侧连接。在每个半导体管芯仅有单个高电流前侧连接的情况下，可以容易在不损害可制造性或性能的情况下将导电夹用于这些类型的封装布置中的前侧连接。
可以使用横向扩散场效应晶体管(LDFET)，例如横向扩散金属氧化物半导体(LDMOS)晶体管，来实施电力装置。这些类型的晶体管的特征在于“横向扩散”区域(或低掺杂或轻度掺杂漏极(LDD)区域)，所述区域对应于没有核心漏极区域那么强地掺杂的漏极区域的延伸部并且横向地延伸远离沟道。所述横向扩散区域增加了LDFET的以下能力：通过吸收原本将导致源极-漏极贯穿的电场的部分来处置关断状态下的更高的电压；以及通过防止在漏极-主体界面处积累较大的电位降来处置接通状态下的更大的电流，所述较大的电位降原本将经由将热的载流子喷射到装置的主体中而导致装置的劣化。
横向电力装置，例如LDFET，通常具有前侧源极触点和漏极触点，所述触点中的每一者通常具有其自身的高电流、低电阻和/或低电感前侧电连接。对外部(例如，封装)和芯片上电连接的需求随着集成于同一半导体管芯上的横向电力装置的数目而增加。然而，半导体管芯的前侧具有可用于容纳相对大的高性能电连接的有限空间。此限制严重地约束了集成的横向电力装置电路的电路设计的灵活性、性能以及可制造性。
发明内容
在一些实施方案中，一种集成电路(IC)封装包括引线框架，所述引线框架具有周边封装引线、第一电连接器、第二电连接器和第三电连接器。所述IC封装另外包括具有前侧和后侧的单个半导体功率管芯。半导体功率管芯的后侧具有后侧电触点，所述前侧具有第一前侧电触点和第二前侧电触点。第一前侧电触点电耦合并被物理安装到第一电连接器，并且第二前侧电触点电耦合并被物理安装到第二电连接器。所述IC封装还包括导电夹，所述导电夹具有第一电接触表面、第二电接触表面和第三电接触表面。所述第二电接触表面和所述第三电接触表面处于所述导电夹的一部分的相对侧上。所述第一电接触表面电耦合并被物理安装到第三电连接器，并且所述第二电接触表面电耦合并被物理安装到单个半导体功率管芯的后侧电触点。所述IC封装还包括控制器管芯，所述控制器管芯具有控制器前侧、控制器后侧和控制器后侧电触点。所述控制器后侧被物理安装到所述导电夹的第三电接触表面。
在一些实施方案中，一种用于将半导体装置封装于IC封装中的方法涉及提供引线框架，所述引线框架具有周边封装引线、第一电连接器、第二电连接器和第三电连接器。形成具有前侧和后侧的单个半导体功率管芯。所述半导体功率管芯的后侧具有后侧电触点，并且所述前侧具有第一前侧电触点和第二前侧电触点。所述方法包括将第一前侧电触点电耦合并物理安装到第一电连接器，并且将第二前侧电触点电耦合并物理安装到第二电连接器。提供导电夹，所述导电夹具有第一电接触表面、第二电接触表面和第三电接触表面。所述第二电接触表面和所述第三电接触表面处于所述导电夹的一部分的相对侧上。所述方法包括将第一电接触表面电耦合并物理安装到引线框架的第三电连接器，并且将导电夹的第二电接触表面电耦合并物理安装到单个半导体功率管芯的后侧电触点。提供控制器管芯，所述控制器管芯具有控制器前侧、控制器后侧和控制器后侧电触点。所述控制器管芯的控制器后侧被物理安装到所述导电夹的第三电接触表面。
附图说明
图1是并入有一些实施方案的高功率半导体开关的示例的电路图。
图2A是根据一些实施方案的集成电路封装的一部分的简化示例的图解顶部正视图。
图2B是根据一些实施方案的集成电路封装的一部分的简化示例的图解横截面。
图2C是根据一些实施方案的集成电路封装的一部分的简化示例的图解横截面。
图3是根据一些实施方案的集成电路封装的一部分的简化示例的图解横截面。
图4是根据一些实施方案的集成电路封装的一部分的简化示例的图解横截面。
图5是根据一些实施方案的集成电路封装的一部分的简化示例的图解横截面。
图6是根据一些实施方案的集成电路封装的一部分的简化示例的图解横截面。
图7A是并入有一些实施方案的高功率半导体开关的示例的电路图。
图7B是根据一些实施方案的集成电路封装的一部分的简化示例的图解横截面。
图8示出了根据一些实施方案的用于将半导体装置封装于具有引线框架的集成电路封装中的方法的简化示例。
具体实施方式
在以下描述中，使用相同的参考数字来识别相同的元件。此外，附图意在通过图解的方式说明示例性实施方案的主要特征。附图无意描绘实际实施方案的每个特征或所描绘的元件的相对尺寸，并且未按比例绘制。
本文描述的一些示例提供了用于倒装芯片定向型半导体装置的有利的导电夹布置，以促进集成电路封装的导电性和排热。所述集成电路封装包括控制器管芯，以及处于单个半导体管芯内的两个或更多个功率晶体管。本文包括的集成电路封装的一些示例包括以下实施方案，其中控制器管芯被直接安装到导电夹(“夹”)，使得控制器管芯的电触点电耦合到所述夹(例如，所述夹耦合到集成电路封装的接地节点，且控制器管芯的接地节点电耦合到所述夹)。在其他示例中，控制器管芯被直接安装到所述夹，但控制器管芯与所述夹基本上电隔离。
本文提供的半导体管芯包括形成于半导体管芯上的集成的横向扩散场效应晶体管(LDFET)电路，所述电路包括到后侧电连接的至少一个衬底触点，这减少了所需的前侧电连接的数目。以此方式，这些示例增加了可用于容纳相对大的高性能电连接(例如，引线框架的电连接器，例如能够传导高电流的金属条带)的前侧空间，进而增加了集成的LDFET电力装置电路的电路设计灵活性、性能和可制造性。在一些示例中，使具有衬底触点的LDFET与同一电路中的其他LDFET电隔离，以通过防止在连接到衬底的LDFET与未连接到衬底的LDFET之间形成共同节点来进一步提高电路的性能。
仅出于说明的目的，本公开在类似于在图1中示出的示例性高功率半导体开关电路10的实施方案的背景下描述了单个半导体管芯集成的LDFET电路的特定示例。可以使用相同或类似的教导来制造适合于电力和非电力应用的其他单个半导体管芯集成的LDFET电路。
高功率半导体开关电路10包括高侧场效应晶体管(FET)12和低侧FET 14。高侧FET12的源极在相节点16(VPHASE)处耦合到低侧FET 14的漏极。驱动器输入端子18、20控制高侧FET 12和低侧FET 14的占空比，以将输入节点23处的输入电压(VIN)转换为相节点16处的特定输出电压(VPHASE)。一般来说，可以使用广泛多种半导体材料系统和技术中的任一者，包括硅、锗和复合半导体技术，来制造FET 12、14。
图2A示出了根据一些实施方案的集成电路(IC)封装200的一部分的简化示例的顶部正视图，所述集成电路封装包括引线框架220、半导体管芯230、导电夹235和顶部半导体管芯(例如，控制器管芯222)。在一些实施方案中，所述顶部半导体管芯是以下各者中的一者：(i)控制器管芯；(ii)块体半导体管芯；(iii)微处理器；(iv)微控制器；(v)数字信号处理器；或(vi)在本领域中已知的另一半导体。在本文描述的示例性实施方案中，所述顶部半导体管芯是控制器管芯(控制器管芯222)。IC封装200还包括接合线292a-d。在所示出的示例中，半导体管芯230体现集成的负荷点(POL)电压转换器，并且控制器管芯222被配置成使POL电压转换器的晶体管的相应的接通/关断状态同步。在所示出的简化示例中，半导体管芯230体现在图1中示出的高功率半导体开关电路10的示例性实现方式。然而，所述半导体装置可以是在本领域中已知的另一半导体装置。
如所示，控制器管芯222具有控制器前侧223a(以及如图2B中所示的其他侧)和控制器前侧电触点224。半导体管芯230具有后侧231a，以及如图2B中所示的其他侧。类似地，导电夹(“夹”)235具有电接触表面240a，以及如图2B中所示的其他电接触表面。还示出了稍后参考图2B至图2C论述的横截面切割线233a-b。
一般来说，引线框架220包括电连接器275a-c和周边封装引线291a-h。在图2A中或本文的图中的任一者中示出的电连接器和/或周边封装引线的数目被示出为简化示例。在一些实施方案中，可以使用更多或更少的电连接器和/或周边封装引线。如所示，夹235的与电接触表面240a相对的电接触表面被物理安装到半导体管芯230的后侧231a。控制器管芯222的与控制器前侧223a相对的控制器后侧被物理安装到夹235的电接触表面240a。与半导体管芯230的后侧231a相对的半导体管芯230的前侧的相应的电触点(在图2B和图2C中示出)电耦合并被物理安装到引线框架的电连接器275b-c。
控制器管芯222的前侧电触点中的一者或多者电耦合到周边封装引线291a-h、引线框架220和/或半导体管芯230中的一者或多者，以接收或发送用于控制在下文描述的半导体管芯230中的高功率半导体开关电路的电子组件(例如，晶体管)的信号、命令和/或反馈。举例来说，控制器前侧电触点224的触点通过接合线292a耦合到周边封装引线291a。控制器前侧电触点224的另一触点通过接合线292b耦合到周边封装引线291b，另一触点通过接合线292c耦合到电连接器275c，并且另一触点通过接合线292d耦合到电连接器275b。
导电夹235在至少一个尺寸上大于接合线292a-d。因此，导电夹235相比而言传导更大量的热，并且具有比接合线更大的导电性。通过将导电夹235有利地设置在半导体管芯230与控制器管芯222(或其他顶部半导体管芯)之间，可以通过导电夹235将从这些管芯中的任一者或两者产生的热传导出IC封装200或传导到所述IC封装的外部周边。
常常使用铜(Cu)预先形成(例如，不是沉积)导电夹，例如导电夹235，所述导电夹与半导体管芯和/或接合线相比在机械上较大、具有比接合线更大的结构强度、具有比接合线更大的导电性能力，并且具有比接合线更大的导热能力。举例来说，导电夹通常具有约100μm的最小特征大小和实质性横截面积。如先前提及，将导电夹235有利地设置于半导体管芯230与控制器管芯222之间并且耦合到所述半导体管芯和所述控制器管芯以促进将热输离那些部分。
图2B示出了根据一些实施方案的包括半导体装置的引线框架220的集成电路(IC)封装200的简化示例的一部分的图解横截面视图。IC封装200的横截面视图是穿过由图2A的切割线233a指示的图2A的IC封装200的一部分而取得的横截面。
图2B的IC封装200包括在图2A中介绍的元件，以及安装介质215a-c、控制器后侧223b、半导体管芯230的前侧231b，和夹235的电接触表面240b-c。
夹235的电接触表面240b通过安装介质215b电耦合并被物理安装到电连接器275a。夹235的电接触表面240c通过安装介质215a电耦合并被物理安装到半导体管芯230的后侧231a。在一些实施方案中，安装介质215a-c包括管芯附接粘合剂、烧结银、焊膏、导热粘合剂，或适合于形成物理连接、热连接和电连接的任何物质。如将描述，在一些实施方案中，安装介质215c是电绝缘材料。在一些实施方案中，半导体管芯230的前侧电触点包括铜柱或焊料凸点。半导体管芯230的第一前侧电触点282电耦合并被物理安装到电连接器275b，并且第二前侧电连接器284电耦合并被物理安装到电连接器275c(例如，通过管芯附接粘合剂或其他合适的安装技术)。接合线292a将(例如，图2A的周边封装引线291a-h的)周边封装引线291a电耦合到控制器管芯222的控制器前侧电触点。
在一些实施方案中，半导体管芯230的第一前侧电触点282和第二前侧电触点284一般表示半导体管芯230的多个金属层中的顶部金属层。半导体管芯230被颠倒或处于倒装芯片配置，因此在图式中分别在底部和顶部上示出半导体管芯230的“顶部”/“前侧”和“底部”/“后侧”。已经出于简单起见而省略了一些金属层、连接、接合线或其他特征。可以存在中介金属层、导电粘合剂、铜柱、焊料凸点或其他金属接合结构。在一些实施方案中，在半导体管芯230、引线框架220和/或控制器管芯222之间形成至少五个电连接。参考图1，这五个电连接包括到输入节点23(VIN)的电连接、到相节点16(VPHASE)的电连接、到接地节点的电连接、到驱动器输入端子18(例如，高侧FET 12的栅极节点)的电连接，以及到驱动器输入端子20(例如，低侧FET 14的栅极节点)的电连接。
在一些实施方案中，控制器管芯222的控制器后侧223b上的后侧电触点通过安装介质215c电耦合到夹235的电接触表面240a，所述安装介质是管芯附接粘合剂、烧结银、焊膏、导热粘合剂，或适合于形成物理连接、热连接和电连接的任何物质。在其他实施方案中，通过安装介质215c使控制器管芯222的控制器后侧223b上的后侧电触点与夹235的电接触表面240a基本上电隔离，所述安装介质是管芯附接粘合剂或适合于形成物理连接和热连接的任何物质。在任一实施方案中，由半导体管芯230和控制器管芯222产生的热被有利地传导(通过安装介质215a、c、夹235和安装介质215b)到IC封装200的外向部分(例如，传导到电连接器275a)。
图2C示出了根据一些实施方案的包括半导体装置的引线框架220的集成电路(IC)封装200的简化示例的一部分的图解横截面视图。在图2C中示出的IC封装200的横截面视图是穿过由图2A的切割线233b指示的图2A的IC封装200的一部分而取得的横截面。
图2C的IC封装200包括在图2A-B中介绍的元件，以及半导体管芯230的第三前侧电触点286。在一些实施方案中，第三前侧电触点286电耦合到半导体管芯230的晶体管的栅极触点。如所示，第三前侧电触点286电耦合并被物理安装到在半导体管芯230下方延伸的周边封装引线291b。虽然将第三前侧触点286示出为物理安装到周边封装引线291b，但在一些实施方案中，第三前侧电触点286电耦合到周边封装引线291b(例如，通过接合线)而不被物理安装到周边封装引线291b。
在所示出的实施方案中，接合线292b将周边封装引线291b电耦合到控制器管芯222的控制器前侧电触点，且进而将第三前侧触点286电耦合到控制器管芯222的触点。
在一些实施方案中，第三前侧电触点286一般表示半导体管芯230的多个金属层的顶部金属层。已经出于简单起见而省略了一些金属层、连接、接合线或其他特征。可以存在中介金属层、导电粘合剂、铜柱、焊料凸点或其他金属接合结构。
图3示出了根据一些实施方案的包括引线框架320的集成电路(IC)封装300的一部分的简化的图解横截面侧视图。所示出的引线框架320的所述部分一般包括电连接器75a-c。已经出于简单起见而省略了引线框架320的其他部分。举例来说，与图2A的周边封装引线291a-h类似的周边封装引线可以是引线框架320的部分。IC封装300包括具有第一前侧电触点82和第二前侧电触点84的半导体管芯30。IC封装300还包括导电夹(“夹”)35，以及具有后侧电触点81的控制器管芯22。IC封装300的部分类似于参考图2A-C所论述的IC封装200的部分。举例来说：夹35类似于夹235，并且电连接器75a-c类似于电连接器275a-c。
在所示出的简化的示例性实施方案中，半导体管芯30体现图1的高功率半导体开关电路10。在此示例中，LDFET 32实施开关电路10的高侧FET 12，并且LDFET 34实施开关电路10的低侧FET 14。在一种示例性配置中，高侧LDFET 32的第一前侧触点82对应于开关电路10的输入节点23，第二前侧触点84对应于开关电路10的相节点16，并且后侧电触点40对应于开关电路10的接地节点。在一些实施方案中，控制器管芯22的前侧电触点(例如，类似于在图2A中示出的控制器前侧触点224)经由线接合和/或通过引线框架320电耦合到LDFET32和/或LDFET 34的栅极节点。此配置使得控制器管芯22能够控制高侧LDFET 32和低侧LDFET 34的接通/关断状态。在一些实施方案中，半导体管芯30包括p型高侧晶体管和n型低侧晶体管。在一些实施方案中，使用两个栅极触点单独地或使用单个栅极触点一起(例如，其中高侧晶体管的栅极和低侧晶体管的栅极电耦合到单个栅极触点)同时地开关高侧晶体管和低侧晶体管两者。
在上文描述和图3中示出的高功率半导体开关电路10的示例性实现方式中，高侧LDFET 32的漏极触点56连接到输入节点23，高侧LDFET 32的源极触点54和低侧LDFET 34的漏极触点56’连接到相节点16，并且低侧LDFET 34的源极触点54’连接到接地节点。如上文提及，其他节点连接布置是可能的。举例来说，这些其他连接布置包括第一LDFET与第二LDFET之间的任何连接布置，所述连接布置包括：(i)电连接到第一LDFET的源极和第二LDFET的漏极的共同节点；(ii)第一LDFET的漏极、第二LDFET的源极和共同节点中的至少一者电连接到半导体衬底；以及(iii)与未电连接到半导体衬底的第一LDFET的漏极、第二LDFET的源极和共同节点中的至少两者连接的至少两个前侧触点。
在有效层42中实施高侧LDFET和低侧LDFET32、34。有效层42可以是以下各者中的任一者：半导体晶片块体的掺杂部分、形成于半导体晶片的较大掺杂部分中的局部阱、绝缘体上半导体(SOI)晶片的有效层，以及形成于SOI晶片中的局部阱。在所说明的示例中，有效层42是在SOI衬底45上的掩埋介电层44上形成的薄膜。在所说明的示例中，介电隔离势垒47在高侧LDFET和低侧LDFET32、34之间从有效层42的顶部延伸到掩埋介电层44。在一些示例中，使用浅沟槽隔离(STI)工艺形成介电隔离势垒47。
有效层42的高侧LDFET 32包括：源极区域46，所述源极区域形成于掺杂区域48中；轻度掺杂的漏极(LDD)区域50，所述区域具有形成于掺杂区域51中的更重掺杂的延伸区域49；以及漏极区域52。源极区域46、掺杂区域48、LDD区域50、延伸区域49以及漏极区域52可以包括通过(例如)将杂质植入到有效层42中而形成的掺杂半导体材料。每个区域46-52的掺杂半导体材料具有类似的导电类型(例如，n型或p型)。因此，可以通过同一掺杂剂种类，例如通过植入一种掺杂剂原子，来形成每个区域46-52。LDD区域50具有比漏极区域52更低的掺杂剂浓度并且还可以具有比源极区域46更低的掺杂剂浓度。LDD区域50依据其截止大电压且在吸收大电流时不劣化的能力而向LDFET提供了其作为电力装置的优良性能。LDD区域50的存在向LDFET提供了其具有非对称的源极区域和漏极区域的特性。在一些方法中，LDD区域50大体上从漏极区域52横向地延伸了是掺杂区域48从源极区域46延伸的距离至少两倍的距离。
有效层42的高侧LDFET部分还包括主体区域60和深阱区域62，所述主体区域和深阱区域具有与源极区域、掺杂区域、LDD区域、延伸区域和漏极区域46-52的导电类型相反的导电类型。深阱区域62在源极区域46和主体区域60的其中形成沟道的部分下方横向地延伸。深阱区域62增强了高侧LDFET 32承受大电压的能力，并且用于从主体区域60移除不想要的电荷载流子，以防止寄生双极结型晶体管在高侧LDFET 32的接通状态期间启动。
在有效层42上方，高侧LDFET 32包括栅极结构，所述栅极结构包括栅极屏蔽物66和栅极电极68。分别通过介电材料70、72使栅极电极68与有效层42和栅极屏蔽物66电绝缘。源极区域46电耦合到源极触点54，所述源极触点连接到第二前侧电触点(相位)84。漏极区域52电耦合到漏极触点56，所述漏极触点连接到第一前侧电触点(输入)82。漏极区域52可以是高度掺杂漏极区域并且可以形成漏极触点56与LDD区域50之间的导电路径。电绝缘材料74(例如，层间电介质)使有效层42上方的电组件电隔离。一般来说，电绝缘材料74和介电材料70、72可以是相同或类似的材料。另外，在特定方法中，可以将绝缘材料74与介电材料70、72的组合概念化为完成的装置中的单个绝缘层，而不管它们形成的时间和方式如何。
响应于将电压施加到栅极电极68(例如，通过控制器管芯22)而在源极触点54与漏极触点56之间形成导电路径。源极触点54与漏极触点56之间的导电路径包括在施加到栅极电极68的前述电压的影响下选择性地形成于主体区域60中的沟道。当形成所述沟道时，晶体管被认为接通。当未形成沟道并且在源极触点54与漏极触点56之间不存在导电路径时，晶体管被认为关断。在此情形下之所以不存在导电路径是因为源极区域46和漏极区域50、52具有与主体区域60相反的导电类型，使得在它们的界面处形成二极管结。
栅极屏蔽物66与源极触点54处于欧姆接触。栅极屏蔽物66是使得高侧FET 32更经得起高功率应用的另一特征。通过将栅极屏蔽物66偏置于给定电压，漏极触点56上的高功率信号被屏蔽而不会对栅极区域具有明显影响。虽然将栅极屏蔽物66说明为欧姆耦合到源极触点54，但还可以独立地偏置栅极屏蔽物66。在一些示例中，栅极屏蔽物66和源极触点54可以在两个不同的步骤中形成，并且可以包括两种不同的材料。然而，在此情况下，此类特征在大多数情形下对于装置的操作并不重要，因为栅极屏蔽物66和源极触点54是高度导电材料的一个邻接区域，其中从介电材料74上方一直到有效层42的表面都具有不间断的欧姆接触。因此，可以将栅极屏蔽物66与源极触点54的组合概念化为单个源极触点。
一般来说，源极触点54和漏极触点56实现了从可以与LDFET集成在同一集成电路上或可以不与LDFET集成在同一集成电路上的其他电路到高侧LDFET 32的电连接。源极区域46可以经由形成于源极区域46的表面上的硅化物层而电耦合到源极触点54。更一般来说，源极区域46可以使用在结构的两个区域之间形成欧姆接触或非整流接触的任何工艺来耦合到源极触点54。漏极触点56与漏极区域52之间的连接可以包括上文参考源极触点54和源极区域46所描述的变化中的任一者。源极触点54和漏极触点56可以包括金属、金属合金、金属硅化物或导电半导体材料，例如掺杂多晶硅。示例性金属、金属合金和金属硅化物可以各自包括铜、钨、钼和铝。
在图3中示出的示例中，有效层42的低侧LDFET部分34的一些元件按照与有效层42的高侧LDFET部分32的对应元件类似的方式起作用。在此方面，将使用后面带有撇号的高侧LDFET的对应元件的参考数字来标记低侧LDFET 34的在功能上类似的元件。举例来说，使用参考数字52’来标记与高侧LDFET 32的在功能上类似的漏极区域52相对应的低侧LDFET 34的漏极区域。因此，低侧LDFET 34包括以下元件：源极区域46’、掺杂区域48’、具有形成于掺杂区域51’中的更重掺杂的延伸区域49’的LDD区域50’、漏极区域52’、源极触点54’、漏极触点56’、主体区域60’、深阱区域62’、栅极屏蔽物66’、栅极电极68’和介电材料70’、72’。
在此示例中，低侧LDFET 34的源极触点54’不仅从有效层42上方延伸穿过源极区域和掺杂区域46’、48’到达深阱区域62’，而且还延伸穿过深阱区域62’和掩埋介电层44并且延伸进入衬底45。以此方式，低侧LDFET 34的源极触点54’提供了到衬底45且进而到后侧电触点40的沿着源极的电连接，所述衬底触点对应于高功率半导体开关电路10的接地节点。
第二前侧电触点84(相节点)使高侧LDFET的源极触点54与低侧LDFET的漏极触点56’电互连，且进而形成高侧LDFET 32的源极区域46和低侧LDFET 34的漏极区域52’的共同节点。应注意，掩埋介电层44和介电隔离势垒47使高侧LDFET 32与衬底45电隔离，以防止在电力开关电路10的操作期间与低侧LDFET 34的源极触点54’形成共同节点。
将半导体管芯30安装在IC封装300的引线框架320的部分之上和之内。如所示，半导体管芯30的第一前侧电触点82电耦合并被物理安装到电连接器75b，第二前侧电触点84电耦合并被物理安装到电连接器75c，夹35电耦合并被物理安装到半导体管芯30的后侧电触点40，并且夹35电耦合并被物理安装到电连接器75a。形成了控制器管芯22与半导体管芯之间的额外的电连接，这与在图2A-C中示出的类似，但在图3中出于简单起见而省略了所述额外的电连接。
控制器管芯22的控制器后侧电触点81电耦合并被物理安装到夹35。如上文提及，将夹35有利地设置于半导体管芯30与控制器管芯22之间并且耦合到所述半导体管芯和所述控制器管芯以促进将热输离那些部分。在图3中示出的金属层(例如，第一前侧电触点82和第二前侧电触点84)大体上表示在需要时布设连接的多个金属层，包括用于半导体管芯衬垫的顶部金属层，和半导体管芯衬垫与绝缘材料(例如，74)或有效层(例如，42)之间的额外的金属层。已经出于简单起见而省略了一些金属层、连接、接合线或其他特征。可以存在中介金属层、导电粘合剂、铜柱、焊料凸点或其他金属接合结构。出于简单起见，简化的图解横截面侧视图仅示出了单个晶体管“指”。在一些实施方案中，并联连接了多个晶体管指以增加所体现的电路的电力处置能力并且在需要时通过应用所体现的电路来减小总电阻。半导体管芯30被颠倒或处于倒装芯片配置，因此在图式中分别在底部和顶部上示出半导体管芯30的“顶部”/“前侧”和“底部”/“后侧”。
图4示出了根据一些实施方案的包括引线框架420的集成电路(IC)封装400的部分的简化的图解横截面侧视图。所示出的引线框架420的所述部分一般包括电连接器475a-d。已经出于简单起见而省略了引线框架420的其他部分。举例来说，与周边封装引线291a-h类似的周边封装引线可以是引线框架420的部分。
IC封装400包括半导体管芯430(类似于图3的半导体管芯30)，所述半导体管芯具有第一前侧电触点480、第二前侧电触点482和第三前侧电触点484。IC封装400还包括导电夹(“夹”)435、控制器管芯422(类似于图3的控制器管芯22)以及电绝缘和导热材料483。IC封装400的部分类似于参考图2A-C所论述的IC封装200的部分。举例来说：夹435类似于夹235，并且电连接器475a-d类似于电连接器275a-c。
在所示出的实施方案中，半导体管芯430体现图1的高功率半导体开关电路10。在一种示例性配置中，高侧LDFET 432的第一前侧电触点480对应于开关电路10(参见图1)的输入节点23，后侧电触点440对应于开关电路10的相节点16，并且第三前侧电触点484对应于开关电路10的接地节点。
在图3中示出的半导体管芯30的高侧LDFET 32以及引线框架320的一些元件按照与在图4中示出的高侧LDFET 432和引线框架420的对应元件类似的方式起作用。在此方面，使用前面有数字“4”的图3的高侧LDFET的对应元件的参考数字来标记高侧LDFET 432的在功能上类似的元件。举例来说，使用参考数字“452”来标记与图3的高侧LDFET 32的在功能上类似的漏极区域52相对应的图4的高侧LDFET 432的漏极区域。另外，图4的电连接器475a类似于图3的电连接器75a。
高侧LDFET 432包括以下元件：源极区域446、掺杂区域448、具有形成于掺杂区域451中的更重掺杂的延伸区域449的LDD区域450、漏极区域452、源极触点454、漏极触点456、主体区域460、深阱区域462、栅极屏蔽物466、栅极电极468、介电材料470、472和绝缘材料474。另外，使用后面带有撇号的高侧LDFET 432的对应元件的参考数字来标记低侧LDFET434的在功能上类似的元件。因此，低侧LDFET 434包括以下元件：源极区域446’、掺杂区域448’、具有形成于掺杂区域451’中的更重掺杂的延伸区域449’的LDD区域450’、漏极区域452’、源极触点454’、漏极触点456’、主体区域460’、深阱区域462’、栅极屏蔽物466’、栅极电极468’和介电材料470’、472’。
在所示出的示例性实施方案中，通过包括平面外部分489的第二前侧电触点482(例如，电导体)将低侧LDFET 434的漏极触点456’和高侧LDFET 432的源极触点454电连接。另外，高侧LDFET 432的源极触点454不仅从有效层上方延伸穿过源极区域和掺杂区域446、448到达深阱区域462，而且还延伸穿过深阱区域462和掩埋介电层444并且延伸进入晶片衬底445。以此方式，高侧LDFET 432的源极触点454提供了到衬底445且进而到用于高功率半导体开关电路10的相节点16的后侧电触点440的沿着源极的电连接。应注意，掩埋介电层444和介电隔离势垒447使低侧LDFET 434与衬底445电隔离，以防止在电力开关电路的操作期间与高侧LDFET 432的源极触点454形成共同节点。
半导体管芯430被安装在引线框架420的一部分上。如所示，第一前侧电触点480电耦合并被物理安装到引线框架420的电连接器475d，第二前侧电触点482电耦合并被物理安装到电连接器475c，并且第三前侧电触点484电耦合并被物理安装到电连接器475b。夹435电耦合并被物理安装到半导体管芯430的后侧电触点440并且电耦合并被物理安装到电连接器475a。另外，控制器管芯422物理安装到夹435，但通过电绝缘材料483与夹435基本上电隔离。也就是说，在所示出的实施方案中，控制器管芯422的后侧电触点不电耦合到夹435。形成了控制器管芯422与半导体管芯之间的额外的电连接，这与在图2A-C中示出的类似，但在图4中出于简单起见而省略了所述额外的电连接。替代地，在一些实施方案中，在后侧电触点440对应于开关电路的相节点16且电耦合到夹435的情况下，电连接器475c是任选的或不包括所述电连接器。
如上文提及，将夹435有利地设置于半导体管芯430与控制器管芯422之间并且耦合到所述半导体管芯和所述控制器管芯以促进将热输离那些部分。在图4中示出的金属层(例如，前侧电触点480、482和484)大体上表示在需要时布设连接的多个金属层，包括用于半导体管芯衬垫的顶部金属层，和半导体管芯衬垫与绝缘材料(例如，474)或有效层之间的额外的金属层。已经出于简单起见而省略了一些金属层、连接、接合线或其他特征。可以存在中介金属层、导电粘合剂、铜柱、焊料凸点或其他金属接合结构。半导体管芯430被颠倒或处于倒装芯片配置，因此在图式中分别在底部和顶部上示出半导体管芯430的“顶部”/“前侧”和“底部”/“后侧”。
图5示出了根据一些实施方案的包括引线框架520的集成电路(IC)封装500的一部分的简化的图解横截面侧视图。所示出的引线框架520的所述部分一般包括电连接器575a-c。已经出于简单起见而省略了引线框架520的其他部分。举例来说，与图2A的周边封装引线291a-h类似的周边封装引线可以是引线框架520的部分。IC封装500还包括具有第一前侧电触点580和第二前侧电触点584的半导体管芯530、导电夹(“夹”)535、控制器管芯522以及电绝缘和导热材料582。IC封装500的部分类似于参考图2A-C所论述的IC封装200的部分。举例来说：夹535类似于夹235，并且电连接器575a-c类似于电连接器275a-c。
在所示出的实施方案中，半导体管芯530体现图1的高功率半导体开关电路10。在一个示例中，高侧LDFET的第一前侧触点580连接到开关电路10的输入节点(VIN)(参见图1)，后侧电触点540连接到开关电路10的相节点16(VPHASE)，并且第二前侧触点584连接到开关电路10的接地节点(GND)。后侧电触点540对应于开关电路10的相节点。
在此示例中，在图3中示出的半导体管芯30的高侧LDFET 32的一些元件按照与在图5中示出的高侧LDFET的对应元件类似的方式起作用。在此方面，使用前面有数字“5”的图3的高侧LDFET的对应元件的参考数字来标记图5的高侧LDFET的在功能上类似的元件。举例来说，使用参考数字“552”来标记与图3的高侧LDFET 32的在功能上类似的漏极区域52相对应的图5的高侧LDFET的漏极区域。类似地，使用前面有数字“5”的图3的引线框架320的对应元件的参考数字来标记图5的引线框架520的在功能上类似的元件。因此，高侧LDFET包括以下元件：源极区域546、漏极区域552、源极触点554、漏极触点556和栅极电极568。另外，使用后面带有撇号的高侧LDFET的对应元件的参考数字来标记低侧LDFET的在功能上类似的元件。因此，在图5中示出的低侧LDFET包括以下元件：源极区域546’、漏极区域552’、源极触点554’、漏极触点556’和栅极电极568’。
在此示例中，使用支持形成源极和漏极衬底触点的工艺来将高侧源极触点554和低侧漏极触点556’制造成延伸穿过掩埋介电层544到达衬底545的衬底触点。因此，不是如图4中示出的示例中使用前侧触点将高侧源极区域546连接到低侧漏极区域552’，高功率半导体开关电路10的此实现方式使用两个衬底触点554和556’分别将高侧源极区域546和低侧漏极区域552’连接到相节点(VPHASE)。以此方式，前侧连接的数目从三个减少至两个。
如所示，第一前侧电触点580电耦合并被物理安装到引线框架520的电连接器575c，第二前侧电触点584电耦合并被物理安装到电触点575b，夹535电耦合并被物理安装到半导体管芯530的后侧电触点540，并且夹535电耦合并被物理安装到电连接器575a。另外，控制器管芯522被物理安装到夹535，但通过电绝缘材料582与夹535基本上电隔离。然而，在控制器管芯522与半导体管芯530之间可以存在(例如，到栅极电极568/568’)的其他电连接，在图5中出于简单起见而省略了所述其他电连接。半导体管芯530被颠倒或处于倒装芯片配置，因此在图式中分别在底部和顶部上示出半导体管芯530的“顶部”/“前侧”和“底部”/“后侧”。
如上文提及，将夹535有利地设置于半导体管芯530与控制器管芯522之间并且耦合到所述半导体管芯和所述控制器管芯以促进将热输离那些部分。在图5中示出的金属层(例如，第一前侧触点580和第二前侧电触点584)大体上表示在需要时布设连接的多个金属层，包括用于半导体管芯衬垫的顶部金属层，和如上文针对其他实施方案中的金属层所提及的半导体管芯衬垫与绝缘材料或有效层之间的额外的金属层。已经出于简单起见而省略了一些金属层、连接、接合线或其他特征。可以存在中介金属层、导电粘合剂、铜柱或其他金属接合结构。
图6示出了根据一些实施方案的包括引线框架620的集成电路(IC)封装600的一部分的简化的图解横截面侧视图。所示出的引线框架620的所述部分一般包括电连接器675a-c。已经出于简单起见而省略了引线框架620的其他部分。举例来说，与图2A的周边封装引线291a-h类似的周边封装引线可以是引线框架620的部分。IC封装600还包括具有第一前侧电触点680和第二前侧电触点684的半导体管芯630。IC封装600还包括导电夹(“夹”)635，以及具有后侧电触点681的控制器管芯622。IC封装600的部分类似于参考图2A-C所论述的IC封装200的部分。举例来说：夹635类似于夹235，并且电连接器675a-d类似于电连接器275a-c。
在所示出的实施方案中，半导体管芯630体现图1的高功率半导体开关电路10。在一种示例性配置中，高侧LDFET的第一前侧触点680连接到开关电路10的输入节点(VIN)(参见图1)，第二前侧触点684连接到开关电路10的相节点(VPHASE)，并且通过夹635穿过后侧触点640将接触衬底645的源极触点654’连接到开关电路10的接地节点(GND)。
在图3中示出的半导体管芯30的高侧LDFET 32的一些元件按照与在图6中示出的高侧LDFET的对应元件类似的方式起作用。在此方面，使用前面有数字“6”的图3的高侧LDFET的对应元件的参考数字来标记图6的高侧LDFET的在功能上类似的元件。举例来说，使用参考数字“652”来标记与图3的高侧LDFET 32的在功能上类似的漏极区域52相对应的图6的高侧LDFET的漏极区域。因此，高侧LDFET包括以下元件：源极区域646、漏极区域652、源极触点654、漏极触点656和栅极电极668。另外，使用后面带有撇号的高侧LDFET的对应元件的参考数字来标记低侧LDFET的在功能上类似的元件。因此，在图6中示出的低侧LDFET包括以下元件：源极区域646’、漏极区域652’、源极触点654’、漏极触点656’和栅极电极668’。
如所示，第一前侧电触点680电耦合并被物理安装到电连接器675b，第二前侧电触点684电耦合并被物理安装到电触点675c，夹635电耦合并被物理安装到半导体管芯630的后侧电触点640，并且夹635电耦合并被物理安装到电连接器675a。另外，控制器管芯622被物理安装到夹635并通过控制器后侧电触点681电耦合到夹635。
如上文提及，将夹635有利地设置于半导体管芯630与控制器管芯622之间并且耦合到所述半导体管芯和所述控制器管芯以促进将热输离那些部分。在图6中示出的金属层(例如，触点680和684)大体上表示在需要时布设连接的多个金属层，包括用于半导体管芯衬垫的顶部金属层，和如上文针对其他实施方案中的金属层所提及的半导体管芯衬垫与绝缘材料或有效层之间的额外的金属层。已经出于简单起见而省略了一些金属层、连接、接合线或其他特征。可以存在中介金属层、导电粘合剂、铜柱、焊料凸点或其他金属接合结构。半导体管芯630被颠倒或处于倒装芯片配置，因此在图式中分别在底部和顶部上示出半导体管芯630的“顶部”/“前侧”和“底部”/“后侧”。
图7A示出了包括高侧场效应晶体管(FET)780、第一低侧FET 782和第二低侧FET784的高功率半导体开关电路794的示例。高侧FET 780的源极在相节点716处耦合到第一低侧FET 782的漏极和第二低侧FET 784的漏极。
图7B示出了根据一些实施方案的体现图7A的高功率开关电路794的包括引线框架720的集成电路(IC)封装700的一部分的简化的图解横截面侧视图。所示出的引线框架720的所述部分一般包括电连接器775a-d。已经出于简单起见而省略了引线框架720的其他部分。举例来说，与周边封装引线291a-h类似的周边封装引线可以是引线框架720的部分。IC封装700还包括半导体管芯730，所述半导体管芯具有第一前侧电触点786、第二前侧电触点788和第三前侧电触点790。IC封装700还包括导电夹(“夹”)735，和具有后侧电触点781的控制器管芯722。IC封装700的部分类似于参考图2A-C所论述的IC封装200的部分。举例来说：夹735类似于夹235，并且电连接器775a-d类似于电连接器275a-c。
在所示出的示例性实施方案中，半导体管芯730体现了包括一个高侧LDFET 780和两个低侧LDFET 782和784的高功率半导体开关电路794。在一种示例性配置中，第一前侧触点786将高侧LDFET 780的源极触点756和低侧LDFET 784的漏极触点754”连接到开关电路794的相节点716(VPHASE)(参见图7A)，第二前侧触点788将高侧LDFET 780的漏极触点754连接到开关电路794的输入节点723(VIN)，并且第三前侧触点790将低侧LDFET 782的漏极触点754’连接到相节点(VPHASE)。在一些实施方案中，第一前侧触点786和第三前侧触点790在图7B中示出的横截面的平面外彼此电耦合。
在图3中示出的半导体管芯30的高侧LDFET 32的一些元件按照与在图7B中示出的高侧LDFET 780的对应元件类似的方式起作用。在此方面，使用前面有数字“7”的图3的高侧LDFET的对应元件的参考数字来标记图7B的高侧LDFET 780的在功能上类似的元件。举例来说，使用参考数字“752”来标记与图3的高侧LDFET 32的在功能上类似的漏极区域52相对应的图7B的高侧LDFET 780的漏极区域。因此，高侧LDFET 780包括以下元件：源极区域746、漏极区域752、漏极触点754、源极触点756和栅极电极768。另外，使用后面带有撇号的高侧LDFET的对应元件的参考数字来标记低侧LDFET 782的在功能上类似的元件。因此，在图7B中示出的低侧LDFET 782包括以下元件：源极区域746’、漏极区域752’、漏极触点754’、源极触点756’和栅极电极768’。类似地，使用后面带有双撇号的高侧LDFET的对应元件的参考数字来标记低侧LDFET 784的在功能上类似的元件。因此，在图7B中示出的低侧LDFET 784包括以下元件：源极区域746”、漏极区域752”、漏极触点754”、源极触点756”和栅极电极768”。
在所示出的示例性实施方案中，通过第一前侧触点786和高侧源极触点756以及低侧漏极触点754”将高侧源极区域746和邻近的低侧漏极区域752”互连。通过使用衬底触点756’和756”将源极区域746’和746”分别连接到接地节点(GND)，更大的金属区域可用于低侧漏极区域752’的前侧相节点触点790，以使得能够减小平面外电阻。
如所示，第一前侧电触点786电耦合并被物理安装到电连接器775d，第二前侧电触点788电耦合并被物理安装到电连接器775c，第三前侧电触点790电耦合并被物理安装到电连接器775b，夹735电耦合并被物理安装到半导体管芯730的后侧电触点740，并且夹735电耦合并被物理安装到电连接器775a。替代地，在其中第一前侧触点786和第三前侧触点790在图7B中示出的横截面的平面外彼此电耦合的一些实施方案中，电连接器775b或775d中的一者是任选的或不包括所述一者。另外，控制器管芯722被物理安装到夹735并通过控制器后侧电触点781电耦合到夹735。
如上文提及，将夹735有利地设置于半导体管芯730与控制器管芯722之间并且耦合到所述半导体管芯和所述控制器管芯以促进将热输离那些部分。在图7B中示出的金属层(例如，触点786、788、790)大体上表示在需要时布设连接的多个金属层，包括用于半导体管芯衬垫的顶部金属层，和如上文针对其他实施方案中的金属层所提及的半导体管芯衬垫与绝缘材料或有效层之间的额外的金属层。已经出于简单起见而省略了一些金属层、连接、接合线或其他特征。可以存在中介金属层、导电粘合剂、铜柱或其他金属接合结构。半导体管芯730被颠倒或处于倒装芯片配置，因此在图式中分别在底部和顶部上示出半导体管芯730的“顶部”/“前侧”和“底部”/“后侧”。
虽然已经示出了将两个LDFET和三个LDFET集成到单个功率半导体管芯中的示例，但可以用于实施集成的LDFET装置的组成LDFET的结构和布置的众多变化是可能的。另外，这些单独的LDFET结构中的两者或更多者可以彼此组合以产生额外的集成的LDFET电路实施方案。可以将任何数目个晶体管和/或晶体管指单片集成于半导体管芯730中。举例来说，多个电力块(各自具有它们的自身的独立的高侧晶体管和低侧晶体管)可以在半导体管芯730内共存，每个晶体管共享共同的后侧电位(接地或Vin)。
图8示出了根据一些实施方案的用于将倒装芯片定向型半导体装置封装于具有引线框架的集成电路(IC)封装中的方法800的简化示例。在步骤805处提供IC封装的引线框架。在一些实施方案中，所述引线框架具有多个电连接器和周边封装引线，这类似于在图2A-C中示出的IC封装200的引线框架220的示例性部分。一般来说，电连接器是相应的金属条带(例如，如图2A中所示的275a-c)，并且在至少一个尺寸上比周边封装引线更大。在一些实施方案中，电连接器是具有厚度、宽度和长度的金属条带，其中电连接器的长度基本上长于电连接器的宽度。
在步骤810处，形成或提供单个半导体管芯。一般来说，半导体管芯具有前侧和后侧，所述前侧具有一个或多个前侧电触点并且所述后侧具有后侧电触点。在一些实施方案中，单个半导体管芯是根据本文论述、尤其是关于图3到图7B所论述的内容的管芯。在一些实施方案中，所述单个半导体管芯属于电力装置并且包括两个或更多个LDFET晶体管。在其他实施方案中，所述单个半导体管芯包括两个或更多个不是LDFET晶体管的晶体管。
在步骤815处，所述单个半导体管芯被颠倒并且按照倒装芯片配置被物理安装到IC封装的引线框架。单个半导体管芯的一个或多个前侧电触点电耦合并被物理安装到引线框架的相应的电连接器。在一些实施方案中，单个半导体管芯的前侧电触点中的一者或多者电耦合并被物理安装到引线框架的相应的周边封装引线。举例来说，在一些实施方案中，所述单个半导体管芯包括两个或更多个LDFET，每个LDFET具有耦合到单个半导体管芯的相应的前侧电触点的相应的栅极节点。耦合到相应的栅极节点的前侧电触点可以电耦合到相应的周边封装引线，并且在一些实施方案中可以被物理安装到相应的封装引线。
在步骤820处，提供导电和导热夹。在一些实施方案中，所述导电夹是由例如铜的导电材料制成，这也有助于热运输。在一些实施方案中，所述导电夹具有约100微米的最小特征大小。
在步骤825处，将所述导电夹的表面电耦合并物理安装到引线框架(例如，电连接器)的电触点。在一些实施方案中，所述电触点是引线框架焊盘。在其他实施方案中，所述电触点是金属条带，所述条带具有厚度、宽度和长度，其中所述长度基本上长于所述宽度。在一些实施方案中，所述电触点还是散热器。在步骤830处，将导电夹的另一表面电耦合并物理安装到单个半导体管芯的后侧电触点(例如，使用管芯附接粘合剂、焊膏、烧结银、导热粘合剂，或另一适当的技术)。
在步骤835处，形成或提供控制器管芯，所述控制器管芯具有前侧和后侧。在一些实施方案中，所述控制器管芯具有后侧电触点(例如，接地触点)。在其他实施方案中，所述控制器管芯不具有后侧电触点。根据一些实施方案，所述控制器管芯电耦合到所述半导体管芯并且包括被配置成控制和同步半导体管芯内的晶体管的状态(例如，接通/断开、导通/不导通)的电路。
在步骤840处，将所述控制器管芯物理安装到导电夹的表面(例如，使用管芯附接粘合剂、焊膏、烧结银、导热粘合剂，或另一适当的技术)。可以将控制器管芯的后侧安装到导电夹的表面，所述导电夹的所述表面与安装到单个半导体管芯的后侧电触点的导电夹的表面相对。然而，其他安装配置是可能的。举例来说，可以将控制器管芯的前侧安装到导电夹的表面。在一些实施方案中，将控制器管芯安装到导电夹的表面，使得使控制器管芯与导电夹基本上电隔离。在其他实施方案中，将控制器管芯安装到导电夹的表面，使得控制器管芯电耦合到导电夹。
在步骤845处，形成IC封装内的其他电连接(例如，使用接合线)。此类电连接包括控制器管芯与单个半导体管芯之间的电连接、控制器管芯与周边封装引线之间的电连接、控制器管芯与引线框架的电连接器之间的电连接、单个半导体管芯与周边封装引线中的一者或多者之间的电连接，以及控制器管芯和/或单个半导体管芯与引线框架之间的其他电连接。方法800中的其他步骤可以完成IC封装。
已经详细参考了所公开的发明的实施方案，已经在附图中说明了所述实施方案的一个或多个示例。已经通过阐释本技术提供了每个示例，而不是作为对本技术的限制。实际上，虽然已经关于本发明的特定实施方案详细描述了说明书，但将了解，本领域技术人员在理解前述内容之后可以容易想到对这些实施方案的更改、变化和等效物。例如，被说明或描述为一个实施方案的部分的特征可以用于另一实施方案以产生又一实施方案。因此，期望本主题涵盖处于所附权利要求以及其等效物的范围内的所有此类修改和变化。在不脱离本发明的范围的情况下，本领域技术人员可以实践对本发明的这些和其他修改和变化，在所附权利要求中更具体地陈述了本发明的范围。此外，本领域技术人员将了解，前述描述仅是举例，并且无意限制本发明。

Claims (22)

1.一种集成电路封装，所述集成电路封装包括：
引线框架，所述引线框架具有周边封装引线、第一电连接器、第二电连接器和第三电连接器；
单个半导体管芯，所述单个半导体管芯具有前侧和后侧，所述后侧具有后侧电触点，所述前侧具有第一前侧电触点和第二前侧电触点，所述第一前侧电触点电耦合并被物理安装到所述第一电连接器，并且所述第二前侧电触点电耦合并被物理安装到所述第二电连接器；
导电夹，所述导电夹具有第一电接触表面、第二电接触表面和第三电接触表面，所述第二电接触表面和所述第三电接触表面处于所述导电夹的一部分的相对侧上，所述第一电接触表面电耦合并被物理安装到所述第三电连接器，并且所述第二电接触表面电耦合并被物理安装到所述单个半导体管芯的所述后侧电触点；以及
顶部半导体管芯，所述顶部半导体管芯具有顶部半导体前侧、顶部半导体后侧和顶部半导体后侧电触点，所述顶部半导体后侧被物理安装到所述导电夹的所述第三电接触表面，
其中：
所述单个半导体管芯包括两个或更多个晶体管以及第三前侧电触点，所述第一前侧电触点电耦合到所述两个或更多个晶体管中的至少一者，所述第二前侧电触点电耦合到所述两个或更多个晶体管中的至少一者，所述第三前侧电触点电耦合到所述两个或更多个晶体管中的至少一者，并且所述后侧电触点电耦合到所述两个或更多个晶体管中的至少一者。
2.如权利要求1所述的集成电路封装，其中：
所述顶部半导体管芯是控制器管芯。
3.如权利要求1所述的集成电路封装，其中：
所述单个半导体管芯是功率半导体管芯。
4.如权利要求1所述的集成电路封装，还包括：
所述顶部半导体管芯的第一顶部半导体前侧电触点和所述顶部半导体管芯的第二顶部半导体前侧电触点，所述第一顶部半导体前侧电触点电耦合到第一组所述周边封装引线，并且所述第二顶部半导体前侧电触点电耦合到所述单个半导体管芯的所述第三前侧电触点。
5.如权利要求4所述的集成电路封装，其中：
所述两个或更多个晶体管包括高侧晶体管和低侧晶体管；
所述高侧晶体管包括高侧源极、高侧漏极和高侧栅极；
所述低侧晶体管包括低侧源极、低侧漏极和低侧栅极；并且
所述第三前侧电触点电耦合到所述高侧栅极或所述低侧栅极中的一者或两者。
6.如权利要求5所述的集成电路封装，其中：
所述高侧晶体管是p型晶体管；
所述低侧晶体管是n型晶体管；
所述高侧栅极电耦合到所述第三前侧电触点；
所述低侧栅极电耦合到所述第三前侧电触点；并且
使用所述第三前侧电触点同时开关所述高侧晶体管和所述低侧晶体管。
7.如权利要求1所述的集成电路封装，其中：
所述两个或更多个晶体管包括高侧晶体管和低侧晶体管；
所述高侧晶体管包括高侧源极、高侧漏极和高侧栅极；
所述低侧晶体管包括低侧源极、低侧漏极和低侧栅极；
所述第一前侧电触点电耦合到所述高侧漏极；
所述第二前侧电触点将所述高侧源极和所述低侧漏极电耦合在一起；并且
所述后侧电触点电耦合到所述低侧源极。
8.如权利要求7所述的集成电路封装，其中所述顶部半导体后侧电触点电耦合到所述导电夹。
9.如权利要求1所述的集成电路封装，其中：
所述引线框架包括第四电连接器；
所述单个半导体管芯包括电耦合并被物理安装到所述第四电连接器的第四前侧电触点；
所述两个或更多个晶体管包括高侧晶体管和低侧晶体管；
所述高侧晶体管包括高侧源极、高侧漏极和高侧栅极；
所述低侧晶体管包括低侧源极、低侧漏极和低侧栅极；
所述第一前侧电触点电耦合到所述高侧漏极；
所述第二前侧电触点将所述高侧源极和所述低侧漏极电耦合在一起；
所述后侧电触点电耦合到所述高侧源极；并且
所述第四前侧电触点电耦合到所述低侧源极。
10.如权利要求9所述的集成电路封装，其中所述顶部半导体后侧电触点与所述导电夹电隔离。
11.如权利要求1所述的集成电路封装，其中：
所述两个或更多个晶体管包括高侧晶体管和低侧晶体管；
所述高侧晶体管包括高侧源极、高侧漏极和高侧栅极；
所述低侧晶体管包括低侧源极、低侧漏极和低侧栅极；
所述第一前侧电触点电耦合到所述高侧漏极；
所述后侧电触点将所述高侧源极和所述低侧漏极电耦合在一起；并且
所述第二前侧电触点电耦合到所述低侧源极。
12.如权利要求11所述的集成电路封装，其中所述顶部半导体后侧电触点与所述导电夹电隔离。
13.如权利要求1所述的集成电路封装，其中：
所述两个或更多个晶体管包括高侧晶体管和低侧晶体管；
所述高侧晶体管包括高侧源极、高侧漏极和高侧栅极；
所述低侧晶体管包括低侧源极、低侧漏极和低侧栅极；
所述第一前侧电触点电耦合到所述高侧漏极；
所述第二前侧电触点将所述高侧源极和所述低侧漏极电耦合在一起；并且
所述低侧源极电耦合到所述后侧电触点。
14.如权利要求13所述的集成电路封装，其中所述顶部半导体后侧电触点电耦合到所述导电夹。
15.如权利要求1所述的集成电路封装，其中：
所述引线框架包括第四电连接器；
所述单个半导体管芯包括电耦合并被物理安装到所述第四电连接器的第四前侧电触点；
所述两个或更多个晶体管包括高侧晶体管、低侧晶体管和第二低侧晶体管；
所述高侧晶体管包括高侧源极、高侧漏极和高侧栅极；
所述低侧晶体管包括低侧源极、低侧漏极和低侧栅极；并且
所述第二低侧晶体管包括第二低侧源极、第二低侧漏极和第二低侧栅极；
其中：
所述第一前侧电触点将所述高侧源极和所述第二低侧漏极电耦合在一起；
所述第二前侧电触点电耦合到所述高侧漏极；
所述第四前侧电触点电耦合到所述低侧漏极；并且
所述后侧电触点将所述低侧源极和所述第二低侧源极电耦合在一起。
16.如权利要求15所述的集成电路封装，其中所述顶部半导体后侧电触点电耦合到所述导电夹。
17.如权利要求1所述的集成电路封装，其中所述顶部半导体后侧电触点电耦合到所述导电夹。
18.如权利要求1所述的集成电路封装，其中所述顶部半导体后侧电触点与所述导电夹电隔离。
19.一种用于在集成电路封装中封装半导体装置的方法，所述方法包括：
提供引线框架，所述引线框架具有周边封装引线、第一电连接器、第二电连接器和第三电连接器；
形成具有前侧和后侧的单个半导体管芯，所述后侧具有后侧电触点，所述前侧具有第一前侧电触点和第二前侧电触点；
将所述第一前侧电触点电耦合并物理安装到所述第一电连接器；
将所述第二前侧电触点电耦合并物理安装到所述第二电连接器；
提供具有第一电接触表面、第二电接触表面和第三电接触表面的导电夹，所述第二电接触表面和所述第三电接触表面处于所述导电夹的一部分的相对侧上；
将所述导电夹的所述第一电接触表面电耦合并物理安装到所述第三电连接器；
将所述导电夹的所述第二电接触表面电耦合并物理安装到所述单个半导体管芯的所述后侧电触点；
提供具有顶部半导体前侧、顶部半导体后侧和顶部半导体后侧电触点的顶部半导体管芯；以及
将所述顶部半导体后侧物理安装到所述导电夹的所述第三电接触表面，
其中：
所述单个半导体管芯包括两个或更多个晶体管以及第三前侧电触点，所述第一前侧电触点电耦合到所述两个或更多个晶体管中的至少一者，所述第二前侧电触点电耦合到所述两个或更多个晶体管中的至少一者，所述第三前侧电触点电耦合到所述两个或更多个晶体管中的至少一者，并且所述后侧电触点电耦合到所述两个或更多个晶体管中的至少一者。
20.如权利要求19所述的方法，其中：
所述顶部半导体管芯是控制器管芯。
21.如权利要求19所述的方法，其中：
所述单个半导体管芯是功率半导体管芯。
22.如权利要求19所述的方法，其中所述导电夹与所述顶部半导体后侧电触点电隔离。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6576580B2 (ja) * 2017-05-12 2019-09-18 三菱電機株式会社 半導体モジュールおよび電力変換装置
CN109671773B (zh) * 2017-10-16 2020-05-05 苏州能讯高能半导体有限公司 半导体器件及其制造方法
CN108172621A (zh) * 2018-01-19 2018-06-15 矽力杰半导体技术(杭州)有限公司 Ldmos晶体管及其制造方法
US11088046B2 (en) 2018-06-25 2021-08-10 Semiconductor Components Industries, Llc Semiconductor device package with clip interconnect and dual side cooling
TWI682540B (zh) * 2018-07-24 2020-01-11 新唐科技股份有限公司 半導體裝置及其形成方法
US20200194459A1 (en) * 2018-12-18 2020-06-18 Vanguard International Semiconductor Corporation Semiconductor devices and methods for fabricating the same
US11282955B2 (en) * 2020-05-20 2022-03-22 Silanna Asia Pte Ltd LDMOS architecture and method for forming
CN116169171B (zh) * 2021-11-25 2024-05-14 苏州华太电子技术股份有限公司 Soi-ldmos器件及其制作方法
US20240153876A1 (en) * 2022-11-03 2024-05-09 Globalfoundries Singapore Pte. Ltd. Transistors having backside contact structures

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203882995U (zh) * 2013-03-13 2014-10-15 半导体元件工业有限责任公司 半导体组件
CN104253122A (zh) * 2013-06-28 2014-12-31 美格纳半导体有限公司 半导体封装件

Family Cites Families (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4738936A (en) 1983-07-01 1988-04-19 Acrian, Inc. Method of fabrication lateral FET structure having a substrate to source contact
US5559044A (en) 1992-09-21 1996-09-24 Siliconix Incorporated BiCDMOS process technology
US5548150A (en) 1993-03-10 1996-08-20 Kabushiki Kaisha Toshiba Field effect transistor
EP0622849B1 (en) 1993-04-28 1999-09-22 Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno A monolithic integrated structure of an electronic device having a predetermined unidirectional conduction threshold
US5365102A (en) 1993-07-06 1994-11-15 North Carolina State University Schottky barrier rectifier with MOS trench
US5378912A (en) 1993-11-10 1995-01-03 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a lateral drift region
US5382818A (en) 1993-12-08 1995-01-17 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode
US6124179A (en) 1996-09-05 2000-09-26 Adamic, Jr.; Fred W. Inverted dielectric isolation process
US6049108A (en) 1995-06-02 2000-04-11 Siliconix Incorporated Trench-gated MOSFET with bidirectional voltage clamping
US6078090A (en) 1997-04-02 2000-06-20 Siliconix Incorporated Trench-gated Schottky diode with integral clamping diode
US6831331B2 (en) 1995-11-15 2004-12-14 Denso Corporation Power MOS transistor for absorbing surge current
DE19647324B4 (de) 1995-11-15 2013-06-27 Denso Corporation Halbleiterbauelement
KR100187635B1 (ko) 1996-03-20 1999-07-01 김충환 단락 애노우드 수평형 절연 게이트 바이폴라 트랜지스터
US5818084A (en) 1996-05-15 1998-10-06 Siliconix Incorporated Pseudo-Schottky diode
KR100225411B1 (ko) 1997-03-24 1999-10-15 김덕중 LDMOS(a lateral double-diffused MOS) 트랜지스터 소자 및 그의 제조 방법
US5889310A (en) 1997-04-21 1999-03-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with high breakdown voltage island region
US5869875A (en) 1997-06-10 1999-02-09 Spectrian Lateral diffused MOS transistor with trench source contact
US6294838B1 (en) 1997-09-24 2001-09-25 Utron Technology Inc. Multi-chip stacked package
US6355501B1 (en) * 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
US6692998B2 (en) 2000-11-30 2004-02-17 International Business Machines Corporation Integrated high quality diode
US6794719B2 (en) 2001-06-28 2004-09-21 Koninklijke Philips Electronics N.V. HV-SOI LDMOS device with integrated diode to improve reliability and avalanche ruggedness
AU2002337297A1 (en) 2001-10-23 2003-05-06 Cambridge Semiconductor Limited Lateral semiconductor-on-insulator structure and corresponding manufacturing methods
US6492244B1 (en) 2001-11-21 2002-12-10 International Business Machines Corporation Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices
KR100867574B1 (ko) 2002-05-09 2008-11-10 페어차일드코리아반도체 주식회사 고전압 디바이스 및 그 제조방법
US6855985B2 (en) 2002-09-29 2005-02-15 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
US7719054B2 (en) 2006-05-31 2010-05-18 Advanced Analogic Technologies, Inc. High-voltage lateral DMOS device
US7576388B1 (en) 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
KR100948139B1 (ko) 2003-04-09 2010-03-18 페어차일드코리아반도체 주식회사 높은 브레이크다운 전압 및 낮은 온 저항을 위한 다중전류 이동 경로를 갖는 수평형 이중-확산 모스 트랜지스터
US7652326B2 (en) 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US6900538B2 (en) 2003-06-03 2005-05-31 Micrel, Inc. Integrating chip scale packaging metallization into integrated circuit die structures
US7273771B2 (en) 2004-02-09 2007-09-25 International Rectifier Corporation Common MOSFET process for plural devices
JP2006019518A (ja) 2004-07-01 2006-01-19 Seiko Instruments Inc 横型トレンチｍｏｓｆｅｔ
TWI234261B (en) 2004-09-10 2005-06-11 Touch Micro System Tech Method of forming wafer backside interconnects
US7466006B2 (en) 2005-05-19 2008-12-16 Freescale Semiconductor, Inc. Structure and method for RESURF diodes with a current diverter
EP1742270A1 (en) 2005-07-06 2007-01-10 STMicroelectronics S.r.l. MOS transistor having a trench-gate and method of manufacturing the same
US7282765B2 (en) 2005-07-13 2007-10-16 Ciclon Semiconductor Device Corp. Power LDMOS transistor
US7589378B2 (en) 2005-07-13 2009-09-15 Texas Instruments Lehigh Valley Incorporated Power LDMOS transistor
US8692324B2 (en) 2005-07-13 2014-04-08 Ciclon Semiconductor Device Corp. Semiconductor devices having charge balanced structure
US7420247B2 (en) 2005-08-12 2008-09-02 Cicion Semiconductor Device Corp. Power LDMOS transistor
US7235845B2 (en) 2005-08-12 2007-06-26 Ciclon Semiconductor Device Corp. Power LDMOS transistor
TWI273718B (en) 2005-10-12 2007-02-11 Advanced Semiconductor Eng Lead frame base package structure with high-density of foot prints arrangement
US7560808B2 (en) 2005-10-19 2009-07-14 Texas Instruments Incorporated Chip scale power LDMOS device
DE102006053145B4 (de) 2005-11-14 2014-07-10 Denso Corporation Halbleitervorrichtung mit Trennungsbereich
US7285849B2 (en) * 2005-11-18 2007-10-23 Fairchild Semiconductor Corporation Semiconductor die package using leadframe and clip and method of manufacturing
US7375371B2 (en) 2006-02-01 2008-05-20 International Business Machines Corporation Structure and method for thermally stressing or testing a semiconductor device
US7446375B2 (en) 2006-03-14 2008-11-04 Ciclon Semiconductor Device Corp. Quasi-vertical LDMOS device having closed cell layout
US7842568B2 (en) 2006-06-28 2010-11-30 Great Wall Semiconductor Corporation Lateral power semiconductor device for high frequency power conversion system, has isolation layer formed over substrate for reducing minority carrier storage in substrate
US7605446B2 (en) 2006-07-14 2009-10-20 Cambridge Semiconductor Limited Bipolar high voltage/power semiconductor device having first and second insulated gated and method of operation
US7554154B2 (en) 2006-07-28 2009-06-30 Alpha Omega Semiconductor, Ltd. Bottom source LDMOSFET structure and method
US7550318B2 (en) 2006-08-11 2009-06-23 Freescale Semiconductor, Inc. Interconnect for improved die to substrate electrical coupling
US7622793B2 (en) 2006-12-21 2009-11-24 Anderson Richard A Flip chip shielded RF I/O land grid array package
US7952145B2 (en) * 2007-02-20 2011-05-31 Texas Instruments Lehigh Valley Incorporated MOS transistor device in common source configuration
JP2008251067A (ja) 2007-03-29 2008-10-16 Hitachi Ltd ディスクアレイ装置
US7598128B2 (en) 2007-05-22 2009-10-06 Sharp Laboratories Of America, Inc. Thin silicon-on-insulator double-diffused metal oxide semiconductor transistor
US7713821B2 (en) 2007-06-25 2010-05-11 Sharp Laboratories Of America, Inc. Thin silicon-on-insulator high voltage auxiliary gated transistor
US20090057869A1 (en) * 2007-08-31 2009-03-05 Alpha & Omega Semiconductor, Ltd. Co-packaged high-side and low-side nmosfets for efficient dc-dc power conversion
US7768123B2 (en) * 2007-09-26 2010-08-03 Fairchild Semiconductor Corporation Stacked dual-die packages, methods of making, and systems incorporating said packages
US7745846B2 (en) 2008-01-15 2010-06-29 Ciclon Semiconductor Device Corp. LDMOS integrated Schottky diode
US8174071B2 (en) 2008-05-02 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. High voltage LDMOS transistor
US7745920B2 (en) 2008-06-10 2010-06-29 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
WO2010014281A1 (en) 2008-07-30 2010-02-04 Maxpower Semiconductor Inc. Semiconductor on insulator devices containing permanent charge
US7994609B2 (en) 2008-11-21 2011-08-09 Xilinx, Inc. Shielding for integrated capacitors
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US20100171543A1 (en) 2009-01-08 2010-07-08 Ciclon Semiconductor Device Corp. Packaged power switching device
US8193559B2 (en) 2009-01-27 2012-06-05 Infineon Technologies Austria Ag Monolithic semiconductor switches and method for manufacturing
US7829947B2 (en) 2009-03-17 2010-11-09 Alpha & Omega Semiconductor Incorporated Bottom-drain LDMOS power MOSFET structure having a top drain strap
US8101993B2 (en) 2009-03-18 2012-01-24 Force Mos Technology Co., Ltd. MSD integrated circuits with shallow trench
US8395191B2 (en) 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US8138049B2 (en) 2009-05-29 2012-03-20 Silergy Technology Fabrication of lateral double-diffused metal oxide semiconductor (LDMOS) devices
US8288820B2 (en) * 2009-06-15 2012-10-16 Texas Instruments Incorporated High voltage power integrated circuit
JP5534298B2 (ja) 2009-06-16 2014-06-25 ルネサスエレクトロニクス株式会社 半導体装置
US9257375B2 (en) * 2009-07-31 2016-02-09 Alpha and Omega Semiconductor Inc. Multi-die semiconductor package
US8120105B2 (en) 2009-07-31 2012-02-21 Micrel, Inc. Lateral DMOS field effect transistor with reduced threshold voltage and self-aligned drift region
US20120326287A1 (en) * 2011-06-27 2012-12-27 National Semiconductor Corporation Dc/dc convertor power module package incorporating a stacked controller and construction methodology
US8174070B2 (en) 2009-12-02 2012-05-08 Alpha And Omega Semiconductor Incorporated Dual channel trench LDMOS transistors and BCD process with deep trench isolation
US20110148376A1 (en) 2009-12-23 2011-06-23 Texas Instruments Incorporated Mosfet with gate pull-down
US8547162B2 (en) 2009-12-23 2013-10-01 Texas Instruments Incorporated Integration of MOSFETs in a source-down configuration
US8582317B2 (en) 2010-05-26 2013-11-12 Semiconductor Components Industries, Llc Method for manufacturing a semiconductor component and structure therefor
US8294210B2 (en) 2010-06-15 2012-10-23 Texas Instruments Incorporated High voltage channel diode
JP5043990B2 (ja) 2010-06-18 2012-10-10 シャープ株式会社 半導体装置およびその製造方法
US8722503B2 (en) 2010-07-16 2014-05-13 Texas Instruments Incorporated Capacitors and methods of forming
US8217452B2 (en) 2010-08-05 2012-07-10 Atmel Rousset S.A.S. Enhanced HVPMOS
US9159825B2 (en) 2010-10-12 2015-10-13 Silanna Semiconductor U.S.A., Inc. Double-sided vertical semiconductor device with thinned substrate
CN105448998B (zh) 2010-10-12 2019-09-03 高通股份有限公司 集成电路芯片和垂直功率器件
US8674497B2 (en) 2011-01-14 2014-03-18 International Business Machines Corporation Stacked half-bridge package with a current carrying layer
US8426952B2 (en) 2011-01-14 2013-04-23 International Rectifier Corporation Stacked half-bridge package with a common conductive leadframe
US9842797B2 (en) 2011-03-07 2017-12-12 Texas Instruments Incorporated Stacked die power converter
US20120228696A1 (en) * 2011-03-07 2012-09-13 Texas Instruments Incorporated Stacked die power converter
CN203392175U (zh) * 2011-04-15 2014-01-15 韩国普利斯包装有限公司 可重复封口的泡罩包装容器
TWI469311B (zh) * 2011-04-29 2015-01-11 萬國半導體股份有限公司 聯合封裝的功率半導體元件
US8436429B2 (en) 2011-05-29 2013-05-07 Alpha & Omega Semiconductor, Inc. Stacked power semiconductor device using dual lead frame and manufacturing method
US8614480B2 (en) 2011-07-05 2013-12-24 Texas Instruments Incorporated Power MOSFET with integrated gate resistor and diode-connected MOSFET
US9524957B2 (en) 2011-08-17 2016-12-20 Intersil Americas LLC Back-to-back stacked dies
US9177308B2 (en) * 2012-06-27 2015-11-03 Bank Of America Corporation Readable indicia for fuel purchase
US9269653B2 (en) 2012-06-27 2016-02-23 Mediatek Inc. SGS or GSGSG pattern for signal transmitting channel, and PCB assembly, chip package using such SGS or GSGSG pattern
US9412881B2 (en) 2012-07-31 2016-08-09 Silanna Asia Pte Ltd Power device integration on a common substrate
US8847310B1 (en) 2012-07-31 2014-09-30 Azure Silicon LLC Power device integration on a common substrate
US8928116B2 (en) 2012-07-31 2015-01-06 Silanna Semiconductor U.S.A., Inc. Power device integration on a common substrate
US8674440B2 (en) 2012-07-31 2014-03-18 Io Semiconductor Inc. Power device integration on a common substrate
US8994105B2 (en) 2012-07-31 2015-03-31 Azure Silicon LLC Power device integration on a common substrate
US9064705B2 (en) 2012-12-13 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of packaging with interposers
US9324838B2 (en) 2013-01-11 2016-04-26 Stmicroelectronics S.R.L. LDMOS power semiconductor device and manufacturing method of the same
US9847284B2 (en) 2013-01-29 2017-12-19 Apple Inc. Stacked wafer DDR package
US9589929B2 (en) 2013-03-14 2017-03-07 Vishay-Siliconix Method for fabricating stack die package
US8748245B1 (en) 2013-03-27 2014-06-10 Io Semiconductor, Inc. Semiconductor-on-insulator integrated circuit with interconnect below the insulator
US9466536B2 (en) 2013-03-27 2016-10-11 Qualcomm Incorporated Semiconductor-on-insulator integrated circuit with back side gate
US9214415B2 (en) 2013-04-11 2015-12-15 Texas Instruments Incorporated Integrating multi-output power converters having vertically stacked semiconductor chips
US9412911B2 (en) 2013-07-09 2016-08-09 The Silanna Group Pty Ltd Optical tuning of light emitting semiconductor junctions
US9269699B2 (en) * 2014-05-09 2016-02-23 Alpha And Omega Semiconductor Incorporated Embedded package and method thereof
US20160005675A1 (en) * 2014-07-07 2016-01-07 Infineon Technologies Ag Double sided cooling chip package and method of manufacturing the same
US20160365334A1 (en) * 2015-06-09 2016-12-15 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same
DE102016101676B3 (de) * 2016-01-29 2017-07-13 Infineon Technologies Ag Elektrische schaltung, die eine halbleitervorrichtung mit einem ersten transistor und einem zweiten transistor und eine steuerschaltung enthält
US10083897B2 (en) 2017-02-20 2018-09-25 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203882995U (zh) * 2013-03-13 2014-10-15 半导体元件工业有限责任公司 半导体组件
CN104253122A (zh) * 2013-06-28 2014-12-31 美格纳半导体有限公司 半导体封装件

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