CN110620138A - 晶体管器件 - Google Patents

晶体管器件 Download PDF

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Publication number
CN110620138A
CN110620138A CN201910526459.8A CN201910526459A CN110620138A CN 110620138 A CN110620138 A CN 110620138A CN 201910526459 A CN201910526459 A CN 201910526459A CN 110620138 A CN110620138 A CN 110620138A
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CN
China
Prior art keywords
region
transistor
source
active device
type
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CN201910526459.8A
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English (en)
Inventor
C.M.博杨恰努
L.陈
S.索辛
A.C.G.伍德
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN110620138A publication Critical patent/CN110620138A/zh
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Abstract

公开了一种晶体管器件。晶体管器件包括：半导体主体（100）；源极导体（21），在半导体主体（100）顶部上；源极夹（31），在源极导体（21）顶部上并且电连接到源极导体（21）；第一有源器件区（110），布置在半导体主体（100）中，被源极导体（21）和源极夹（31）覆盖，并包括至少一个器件单元（10）；和第二有源器件区（120），布置在半导体主体（100）中，被源极夹（31）未覆盖的源极导体（21）的区域覆盖并且包括至少一个器件单元（10、10'）。第一有源器件区（110）具有第一面积特定导通电阻，并且第二有源器件区（120）具有第二面积特定导通电阻，其中第二面积特定导通电阻大于第一面积特定导通电阻。

Description

晶体管器件
技术领域
本公开一般涉及晶体管器件，特别是功率晶体管器件。
背景技术
诸如MOSFET（金属氧化物半导体场效应晶体管）的功率晶体管器件广泛用作各种类型的电子应用中的电子开关。通常，功率晶体管器件包括集成在半导体主体中的多个晶体管单元。一直有在努力减小这些晶体管单元的尺寸，以便在维持给定额定电流的同时减小整体晶体管器件的尺寸。
然而，减小功率晶体管的尺寸可能使晶体管器件的温度管理恶化。基本上，期望以热稳定状态操作晶体管器件。当晶体管器件的温度导致通过晶体管器件的减小电流时，晶体管器件是热稳定的。当升高温度导致增大电流时，晶体管器件是热不稳定的。在这种情况下，增大的电流可能进一步升高温度，这可能再次增大电流，等等。对于给定的晶体管器件，可能存在电流密度极限，其中器件在高于电流密度极限的电流密度处是热稳定的，并且在低于电流密度极限的电流密度处是热不稳定的。该电流密度极限可以称为温度补偿点（TCP）。已经观察到，减小功率晶体管的晶体管单元的尺寸经常导致电流密度极限的增大，这相当于其中晶体管器件热不稳定的电流范围的增大。
发明内容
一个示例涉及晶体管器件。晶体管器件包括半导体主体、在半导体主体顶部上的源极导体、在源极导体顶部上并且电连接到源极导体的源极夹（source clip）、布置在半导体主体中的第一有源器件区、以及布置在半导体主体中的第二有源器件区。第一有源器件区被源极导体和源极夹覆盖并且包括至少一个器件单元，并且第二有源器件区被源极夹未覆盖的源极导体的区域覆盖并且包括至少一个器件单元。此外，第一有源器件区具有第一面积特定导通电阻，并且第二有源器件区具有第二面积特定导通电阻，其中第二面积特定导通电阻大于第一面积特定导通电阻。
附图说明
下面参考附图解释示例。附图用于说明某些原理，因此仅说明了对于理解这些原理所必需的方面。附图不是按比例绘制的。在附图中，相同的附图标记表示相同的特征。
图1示出了包括在半导体主体顶部上的源极导体和安装在源极导体上的源极夹的晶体管器件的顶视图；
图2示意性地图示了晶体管器件的一个部分的垂直横截面视图；
图3示出了图示相对于图1和2中所示的类型的晶体管器件的电流密度的温度系数的曲线；
图4图示了集成在第一有源器件部分中的第一类型晶体管单元和第一有源器件区的垂直横截面视图；
图5图示了图4中所示的第一类型晶体管单元的修改；
图6图示了集成在第一有源器件部分中的第二类型晶体管单元和第一类型晶体管单元以及第二有源器件区的垂直横截面视图；
图7至图10图示了第二类型晶体管单元的不同示例；
图11图示了仅包括第二类型晶体管单元的第二有源器件区的垂直横截面视图；
图12示出了根据一个示例的第一器件区的部分的水平横截面视图；
图13示出了根据另一示例的第一器件区的部件的水平横截面视图；
图14示出了栅极浇道（gate runner）和源极导体的一个部分的顶部；
图15示出了其中栅极浇道连接到栅电极的晶体管器件的一个部分的垂直横截面视图；
图16示出了图15中所示的截面G-G的垂直横截面视图；
图17图示了其中栅极浇道嵌入在源极导体中的一个示例；
图18A和18B示出了其中栅极浇道连接到栅电极并且源极连接器连接到场电极的一个部分的顶视图和垂直横截面；
图19至21示出了根据其他示例的包括源极导体和源极夹的晶体管器件的顶视图；
图22图示了晶体管器件和封装晶体管器件的半导体主体的壳体的垂直横截面视图；
图23图示了图22中所示的晶体管器件的修改；和
图24图示了图22中所示的晶体管器件的另一修改。
具体实施方式
在以下详细描述中，参考所附附图。附图形成说明书的一部分，并且出于说明的目的，示出了可以如何使用和实现本发明的示例。应当理解，除非另有特别说明，否则本文描述的各种实施例的特征可以彼此组合。
图1示出了根据一个示例的晶体管器件的顶视图，并且图2示出了沿图1中所示的截面AB'的晶体管器件1的一个部分的垂直横截面视图。参考图1和图2，晶体管器件包括半导体主体100、在半导体主体100顶部上的源极导体21（其也可以称为源极金属化或源极焊盘（pad））、以及在源极导体21顶部上并且电连接到源极导体21的源极夹31。根据一个示例，半导体主体100是由硅（Si）、碳化硅（SiC）、氮化镓（GaN）、砷化镓（GaAs）等制成的单晶半导体主体。源极导体21包括诸如金属的导电材料。根据一个示例，源极导体21包括铜（Cu）和铝（Al）中的至少一种。根据一个示例，源极导体21是由诸如例如铜（Cu）、铝（Al）或铝-铜合金（AlCu）的一种导电材料制成的均质层。根据另一示例，源极导体21包括层堆叠，该层堆叠具有一个在另一之上形成的至少两层不同的导电材料。根据一个示例，这些层中的一个是Cu层，并且这些层中的另一个是AlCu层。根据一个示例，在源极导体21和半导体主体100之间形成至少一个界面层（图中未示出）。根据一个示例，至少一个界面层包括在半导体主体100的顶部上的钛（Ti）或氮化钛（TiN）的第一层和在第一层和源极导体之间的钨（W）的第二层。第一层可以具有10纳米至60纳米之间的厚度，并且第二层可以具有300纳米至700纳米之间的厚度。根据另一示例，源极导体21被保护涂层（未示出）覆盖，该保护涂层抑制氧化并且可以帮助将源极夹31焊接到源极导体21。
源极夹31由导电材料制成。根据一个示例，导电材料是铜（Cu）或铝（Al）。然而，也可以使用其他导电材料。
参考上文，源极夹31电连接到源极导体21。根据一个示例，导电连接层32形成在源极导体21和源极夹31之间并且将源极夹31电连接到源极导体21。该连接层32可以是焊料层或可以包括导电粘合剂。焊料层可以包括锡（Sn）、铅（Pb）和锌（Zn）中的至少一种。
参考图2，晶体管器件1还包括第一有源器件区（其也可以称为第一有源晶体管区）和第二有源器件区（其也可以称为第二有源晶体管区），其中这些第一和第二有源器件区110、120中的每个包括至少一个晶体管单元，其具有连接在形成于半导体主体100的第一表面101顶部上的源极导体21与形成在半导体主体100的第二表面102的顶部上的漏电极33之间的负载路径（漏极-源极路径）。在图2中，MOSFET T1的电路符号表示第一有源器件区110的至少一个晶体管单元，并且第二MOSFET T2的电路符号表示第二有源器件区120的至少一个晶体管单元。仅出于说明的目的，图2中所示的MOSFET T1、T2是n型增强型MOSFET，使得在该示例中晶体管器件1是n型增强型MOSFET。然而，这只是一个示例。晶体管器件1还可以被实现为n型耗尽型MOSFET、p型增强型MOSFET、p型耗尽型MOSFET或IGBT。
晶体管器件1取决于施加在晶体管器件1的栅极节点G和源极节点S之间的驱动电压（栅极-源极电压）VGS而导通或截止。源极节点S由源极夹31形成，并且栅极节点G由栅极焊盘41形成，根据一个示例，栅极焊盘41也形成在第一表面101的顶部上。当驱动电压VGS高于晶体管器件1的阈值电压时，晶体管器件1导通。在n型MOSFET中，阈值电压是正电压。在导通状态（接通状态）下，当大于零的负载路径电压（漏极-源极电压）VDS施加在漏极节点D和源极节点S之间时，晶体管器件1在由漏电极33形成的漏极节点D与源极节点S之间传导电流。在截止状态（断开状态）下，阻止漏极节点D和源极节点S之间的电流流动。
参考图2，第一有源器件区110形成在半导体主体100的被源极导体21和源极夹31两者覆盖的部分中。第二有源器件区120形成在半导体主体100的被源极导体21覆盖但未被源极夹31覆盖的部分中。第一有源器件区110中的至少一个晶体管单元（由图2中的MOSFETT1表示）和第二有源器件区120中的至少一个第二晶体管单元（由图2中的MOSFET T2表示）被实现为使得第二有源器件区120的面积特定导通电阻大于第一有源器件区110的面积特定导通电阻。第一有源器件区110的面积特定导通电阻在下文中也称为第一面积特定导通电阻，并且第二有源器件区120的面积特定导通电阻在下文中也称为第二面积特定导通电阻。
第一面积特定导通电阻由在晶体管器件的导通状态下的第一有源器件区110中实现的至少一个晶体管单元的电阻（其也可以称为导通电阻）RDS_ON1乘以第一有源器件区110的面积A1给出。如果第一有源器件区110包括并联连接的多个晶体管单元，则导通电阻由具有导通状态下的晶体管单元的并联电路的电阻给出。第一有源器件区110的面积A1在下文中也称为第一面积A1。参考上文，第一面积A1由半导体主体100的被源极导体21和源极夹31两者覆盖的面积给出。根据一个示例，该面积A1相当于将源极夹31连接到源极导体21的连接层32的面积。即，认为半导体主体100的仅那些部分被源极夹31覆盖，其被其中源极夹31通过连接层32电连接到源极导体21的区域覆盖。
等效地，第二有源器件区120的面积特定导通电阻由在晶体管器件的导通状态下的第二有源器件区120中的至少一个晶体管单元T2的电阻RDS_ON2乘以半导体主体100的被源极导体21覆盖但未被源极夹31覆盖的区域的面积A2（在下文中也称为第二面积A2）给出。不言而喻，第二面积特定导通电阻大于第一面积特定导通电阻适用于在相同驱动电压VGS下发生的第一和第二面积特定导通电阻。
根据一个示例，第二面积特定导通电阻A2·RDS_ON2与第一面积特定导通电阻A1·RDS_ON1之间的比率为至少1.2、至少1.5、至少2或至少5。
根据一个示例，第一面积A1大于第二面积A2。根据一个示例，第一面积A1和第二面积A2之间的比率A1/A2大于5或大于10。
在图2中，源极导体21被绘制成邻接半导体主体100的第一表面101。应当注意，图2仅是示意图示。参考在下文中解释的示例，存在连接到源极导体21的半导体主体100的第一表面101的区域。然而，也可以存在其中绝缘层布置在半导体主体100的第一表面101和源极导体21之间的区域。
源极夹31形成晶体管器件1的外部连接，并且可以用于将晶体管器件1连接到供电节点（supply node）或其中使用晶体管器件1的电子电路中的另一电子器件。将源极夹31连接到供电节点或另一电子器件可以包括将源极夹31连接到印刷电路板（PCB）的导电迹线等。
然而，源极夹31不仅具有电功能。已经发现，源极夹31（例如与接合线相比）改进半导体主体100的冷却。特别地，源极夹31改进第一有源器件区100即半导体主体100的位于源极夹31下方并经由源极导体21和连接层32热连接到源极夹31的区域的冷却。第二有源器件区120即半导体主体100的被源极导体21覆盖但未被源极夹31覆盖的区域与第一有源器件区110相比具有冷却不足。已经发现，晶体管器件1的稳健性例如能量耗散稳健性或能量耗散能力可以通过将第二有源器件区120实现为使得第二面积特定导通电阻大于第一有源器件区110的第一面积特定导通电阻来增加。将第二有源器件区120实现为使得第二面积特定导通电阻大于第一面积特定导通电阻具有如下效果，即：在晶体管器件1的导通状态下，与在第一有源器件区110中相比，在第二有源器件区120中平均耗散更少的每单位面积功率。然而，应当理解，第一有源器件区110和第二有源器件区120两者中的功率耗散在动态条件下可能是不均匀的，在这种情况下，可能存在具有更高的每单位面积功率耗散的第二有源器件区120的局部区域和具有更低的每单位面积功率耗散的第一有源器件区110的局部区域。也就是说，在晶体管器件的给定操作点处，可能存在具有比第一有源器件区的区域更高的每单位面积功率耗散的第二有源器件区120的区域。然而，每单位面积的平均功率耗散在第二有源器件区中比在第一有源器件区中更低。
图3示出了图示图1和2中所示的类型的晶体管器件的温度行为的曲线。更具体地，图3中所示的曲线a110表示第一有源器件区110的温度系数，并且曲线a120表示第二有源器件区120的温度系数。温度系数（其通常称为α（alpha））定义了取决于温度变化（dT）的电流变化（dI）。温度系数可以是正（>0）或负（<0）。当温度系数为正时，通过晶体管器件的电流I随着温度T的升高而增大，而当温度系数为负时，电流I随着温度T的升高而减小。参考图3，温度系数取决于由每单位面积的电流给出的电流密度。此外，如从图3中可以看出的，存在其中温度系数随着电流密度的减小而增大的范围。
通常，当在与负温度系数相关联的那些电流密度下操作时，晶体管器件是热稳定的。然而，当温度系数为正但低于预定义上限时，晶体管器件也可能是热稳定的。已经发现，该上限取决于热从晶体管器件传递离开得多好，其中热从晶体管器件传递离开得越好，上限就越高。
在图3中，a110LIM表示第一有源器件区110的温度系数的上限，并且a120LIM表示第二有源器件区120的温度系数的上限，其中a110LIM也被称为第一上限并且a120LIM在下文中也称为第二上限。如从图3中可以看出的，第二上限a120LIM低于第一上限a110LIM，这是由于第二有源器件区与第一有源器件区110相比具有冷却不足的事实。此外，如从图3中可以看出的，存在其处第一有源器件区110的温度系数a110高于第二上限a120LIM的电流密度。因此，如果整个器件即第一有源器件区110和第二有源器件区120以相同的方式实现，则晶体管器件将是热不稳定的。
然而，参考图3，第二有源器件区120的温度系数a120低于第一有源器件区110的温度系数a110并且低于第二上限a120LIM。因此，第一有源器件区110和第二有源器件区120两者以及因此整个晶体管器件是热稳定的。
第二有源器件区120的较低温度系数是通过实现具有比第一有源器件区110更高的面积特定导通电阻的第二有源器件区120来实现的。后者具有如下效果，即：在晶体管器件的给定操作点处，第二有源器件区120中的（平均）电流密度低于第一有源器件区110中，使得给定温度变化下的电流变化也在第二有源器件区120中比在第一有源器件区110中更小。
热稳定性的改进与导通电阻的（稍微）增大相关联。然而，在大多数情况下，这被认为是可接受的。
参考上文，至少一个晶体管单元集成在第一有源器件区110中。根据一个示例，多个晶体管单元集成在第一有源器件区110中。图4示出有源器件区110的一个部分的垂直横截面视图，并且示意性地图示了可以如何实现这些晶体管单元10的一个示例。图4示出了几个晶体管单元，其中这些晶体管单元之一的轮廓由用附图标记10标记的虚线矩形图示。参考图4，每个晶体管单元包括漂移区11、通过主体区13与漂移区11分开的源极区12、以及通过漂移区11与主体区13分开的漏极区14。此外，栅电极15与主体区13邻近地布置并且通过栅极电介质16与主体区13介电绝缘。在图4所示的示例中，栅电极15布置在从第一表面101延伸到半导体主体100中的沟槽中。
漂移区11是第一掺杂类型（导电类型）的掺杂半导体区，源极区12是第一掺杂类型的掺杂半导体区，并且主体区13是与第一掺杂类型互补的第二掺杂类型的掺杂半导体区。在MOSFET中，漏极区14是第一掺杂类型的掺杂半导体区，在IGBT中，漏极区14是第二掺杂类型的掺杂半导体区。漂移区11的掺杂浓度例如选自1E15cm-3和1E17cm-3之间的范围，源极区12的掺杂浓度例如选自1E19cm-3和1E21cm-3之间的范围，主体区13的掺杂浓度例如选自1E15cm-3和1E18cm-3之间的范围，并且漏极区14的掺杂浓度例如选自1E19cm-3和1E21cm-3之间的范围，其中范围包括相应的最大掺杂浓度。在n型晶体管器件中，第一掺杂类型是n型，并且第二掺杂类型是p型。在p型晶体管器件中，第一掺杂类型是p型，并且第二掺杂类型是n型。
参考图4，各个晶体管单元10的漂移区11可以由晶体管单元10所共同的一个掺杂半导体区形成，并且晶体管单元10的漏极区14可以由晶体管单元10所共同的另一掺杂半导体区形成。此外，两个（或更多个）相邻晶体管单元10的栅电极15可以一个掺杂半导体区所形成的两个（或更多个）其他相邻晶体管单元的主体区13和一个公共电极形成。
晶体管单元10并联连接，其中每个晶体管单元10的源极区12和主体区13连接到源极导体21，并且公共漏极区14连接到漏电极33。在图4所示的示例中，源极导体21包括接触插塞22，所述接触插塞22延伸通过在半导体主体100的第一表面101顶部上形成的绝缘层51，直到源极区12和主体区13。此外，各个晶体管单元10的栅电极15电连接到栅极节点G。然而，栅电极15和栅极节点G之间的连接仅在图4中示意性地图示。
可选地，每个晶体管单元10还包括场电极17，场电极17与漂移区11邻近布置并且通过场电极电介质18与漂移区11介电绝缘。该场电极17可以电连接到栅极节点G或者源极节点S。然而，这样的连接在图4中未图示。栅电极15和场电极17可以包括导电材料，诸如金属或高掺杂的晶体半导体材料（诸如多晶硅）。栅极电介质16和场电极电介质18包括诸如氧化物的电绝缘材料。
图4中所示的场电极17和场电极电介质18是可选的。根据图5中所示的另一示例，省略了场电极17和场电极电介质18。
图6示出了第二有源器件区120的一个部分的垂直横截面视图。在该示例中，多个晶体管单元集成在第二有源器件区120中，其中这些晶体管单元以与参考图4所述的相同的方式连接在源极导体21和漏电极33之间。此外，这些晶体管单元的栅电极连接到栅极节点G。在图6所示的示例中，集成在第二有源器件区120中的多个晶体管单元包括相同类型的一个或多个晶体管单元10，如参考图4所解释的。这些晶体管单元10在下文中也称为第一类型晶体管单元。根据一个示例，第一类型晶体管单元具有其相应的源极区12的相同掺杂浓度、其相应的主体区13的相同掺杂浓度、其相应的漂移区11的相同掺杂浓度、以及其相应的漏极区14的相同掺杂浓度。此外，根据一个示例，第一类型晶体管单元10具有相同的阈值电压，其尤其取决于栅电极15和主体区13之间的栅极电介质16的厚度并且取决于主体区13的掺杂浓度。此外，根据一个示例，第一类型晶体管单元具有相同的沟道长度，其是源极区12和漂移区11之间的沿栅极电介质16的主体区13的长度。
参考图6，第二有源器件区120包括至少一个第二类型晶体管单元10'。至少一个第二类型晶体管单元10'的至少一个特征与第一类型晶体管单元10不同。在下文中，仅解释了至少一个不同的特征，使得没有提到不同的第二类型晶体管单元10'的特征等于第一类型晶体管单元10的对应特征。
在图6所示的示例中，第二类型晶体管单元10'与第一类型晶体管单元10的不同之处在于省略了源极区12。也就是说，第二类型晶体管单元10'包括连接到源极导体21的主体区13，但不包括源极区。图7中示出了该第二类型晶体管单元10'的放大视图。与第一类型晶体管单元10不同，当驱动电压VGS高于在栅极节点G和源极节点S之间施加的阈值电压时并且当施加将晶体管器件偏置在正向状态下的负载路径电压VDS时，图6和7中所示的第二类型晶体管单元10'不传导电流。将晶体管器件1偏置在正向状态下的负载路径电压VDS是具有反向偏置第一和第二类型晶体管单元10、10'的主体区13和漂移区11之间的pn结的极性的负载路径电压VDS。在n型MOSFET中，例如，反向偏置该pn结（并且正向偏置晶体管器件1）的负载路径电压VDS是漏极节点D和源极节点S之间的正电压。当在漏极节点D和源极节点S之间施加正向偏置主体区13和漂移区11之间的该pn结（并因此反向偏置晶体管器件1）的负载路径电压VDS时，晶体管器件1独立于驱动电压VGS传导。在该操作模式中，图6和7中所示的第二类型晶体管单元10'传导电流。上面解释的第一和第二有源器件区110、120的导通电阻RDS_ON1、RDS_ON2是在晶体管器件1的导通状态和正向偏置状态下的源极导体21和漏电极33之间的电阻。
与其中第二有源器件区120仅包括第一类型晶体管单元10的场景相比，第二有源器件区120中的至少一个第二类型晶体管单元10'的存在增大了具有第二有源器件区120中的多个晶体管单元10、10'的布置的导通电阻。因此，通过适当地选择在第二有源器件区120中实现的第二类型晶体管单元10'的数量，与根据一个示例仅包括第一类型晶体管单元10的第一有源器件区110的面积特定导通电阻A1·RDS_ON1相比，可以增大第二有源器件区120的面积特定导通电阻A2·RDS_ON2。
第二有源器件区120可以包括多个第一类型晶体管单元10和多个第二类型晶体管单元10'。根据一个示例，第二有源器件区120中的第一类型晶体管单元10的数量与第二类型晶体管单元的数量之间的比率选自20：1和1：20或10：1和1：10之间。通过适当地调整该比率，可以调整第二有源器件区120的面积特定导通电阻。
图8示出了可以如何实现第二类型晶体管单元10'的另一示例，其中在图8中示出了两个第二类型晶体管单元10'。图8中示出的第二类型晶体管单元10'与第一类型晶体管单元10的不同之处在于，栅电极15连接到源极导体21。这些第二类型晶体管单元10'可以被实现为具有源极区（以图8中的虚线所示）或不具有源极区。将栅电极15连接到源电极21具有与省略源极区相同的效果。也就是说，当晶体管器件1处于导通状态和正向偏置时，图8中所示的第二类型晶体管单元10'对电流传导没有贡献。然而，当晶体管器件处于反向偏置时，第二类型晶体管单元10'有助于电流传导。
图9示出了两个第二类型晶体管单元10'的一个示例，其与第一类型晶体管单元10的不同之处在于这些第二类型晶体管单元10'具有比第一类型晶体管单元10更高的阈值电压。因此，这些第二类型晶体管单元10'在给定的驱动电压VGS下具有比第一类型晶体管单元10更高的导通电阻。因此，通过适当地选择第二有源器件区120中的第二类型晶体管单元10'的数量，与第一面积特定导通电阻相比，可以增大第二有源器件区120的面积特定导通电阻。在图9所示的第二类型晶体管单元10'中，更高的阈值电压通过以比第一类型晶体管单元10的主体区13更高的掺杂浓度实现这些晶体管单元10'的主体区13'来实现。
替代地，如图10所示，更高的阈值电压可以通过实现比第一类型晶体管单元10的电介质16更厚的第二类型晶体管单元10'的栅极电介质16'来实现。更厚的栅极电介质可能导致更窄的栅电极15'。当然，在一个第二类型晶体管单元10'中，可以将如图9所示的具有更高的掺杂浓度的主体区13'与如图10所示的更厚的栅极电介质16'组合。
第一有源器件区110和第二有源器件区120中的第一类型晶体管单元10和第二类型晶体管单元10'中的每个的漂移区11可以由一个掺杂半导体区形成，并且第一有源器件区110和第二有源器件区120中的第一类型晶体管单元10和第二类型晶体管单元10'的漏极区14可以由一个掺杂半导体区形成。
在图6所示的示例中，第二有源器件区120包括至少一个第一类型晶体管单元10和至少一个第二类型晶体管单元10'。根据一个示例，在第二有源器件区120中实现多个第一类型晶体管单元10和多个第二类型晶体管单元10'。第二类型晶体管单元10'可以是相同类型的。根据另一示例，不同类型的第二类型晶体管单元集成在第二有源器件区120中。
根据图11中所示的另一示例，第二有源器件区120仅包括第二类型晶体管单元10'，其中这些第二类型晶体管单元10'中的至少一些使得它们在晶体管器件1处于导通状态且正向偏置时传导电流。例如，在该操作状态下传导电流的第二类型晶体管单元10'是比如图9和10中所示的那些的第二类型晶体管单元。当晶体管器件1处于导通状态并且正向偏置时传导电流的这些第二类型晶体管单元可以与仅在晶体管器件被反向偏置时传导电流的第二类型晶体管单元10'组合。这在图11中图示，其示出了根据图9的一个第二类型晶体管单元10'和根据图7的一个第二类型晶体管单元10'。根据另一示例（未示出），在第二有源器件区120中仅实现了当晶体管器件1处于导通状态并且正向偏置时传导电流的第二类型晶体管单元10'。
以上参考这些晶体管单元10、10'的垂直横截面视图解释了第一类型晶体管单元10和第二类型晶体管单元10'的示例。在作为与第一表面101和第二表面102平行的平面的半导体主体100的水平面D-D中，晶体管单元可以以各种方式实现。在下文中参考图12和13解释两个示例。这些图示出了第一类型晶体管单元10的示例。然而，这些示例也等效地适用于第二类型晶体管单元10'。
在图12所示的示例中，晶体管单元10是细长的晶体管单元。在该示例中，栅电极15是在水平面D-D中基本上平行的细长电极。源极区12和主体区13（图12中的视图外）是与栅电极15平行延伸的细长区域。将源极区和主体区连接到源极导体的接触插塞22可以是细长的，如图12中所示的一个示例中所示。可选地，接触插塞22可以包括在源极区12的纵向方向上彼此间隔开的几个插塞部分，如图12中所示的另一示例中所示。
图13示出了根据另一示例的晶体管器件1的一个部分的水平横截面视图。在该示例中，一个网格状电极形成每个晶体管单元10的栅电极15，其中源极区12和主体区（图13中的视图外）形成在网格状电极的“开口”中。仅出于说明的目的，图13中所示的示例中的网格状电极被实现为使得其包括矩形开口。然而，这只是一个示例。也可以实现形成其他类型的开口的网格状电极，诸如例如六边形开口。
第一类型晶体管单元10的栅电极15和至少一些类型的第二类型晶体管单元（图7、9和10中所示的第二类型晶体管单元）的栅电极电连接到栅极焊盘41。在图14中图示了晶体管单元可以如何连接到栅极焊盘41的一个示例，图14示出了晶体管器件1的一个部分的顶视图。在该示例中，晶体管器件1包括栅极连接器42，其连接到晶体管单元的栅电极。在该示例中，栅极连接器42在半导体主体100的水平方向上与源极导体21间隔开。位于源极导体21下方的晶体管单元的源极区12、主体区13、栅电极15和栅极电介质16在图14中以虚线图示。在该示例中，这些晶体管单元是第一类型晶体管单元。然而，这只是一个示例。第二类型晶体管单元的栅电极可以以相同的方式连接到栅极连接器。此外，在该示例中，晶体管单元是细长的晶体管单元。栅极连接器42是与栅电极15交叉的细长导体。根据一个示例，栅极连接器42基本上垂直于栅电极15。
图15示出了图14中所示的截面FF中的半导体主体100和栅极连接器42的垂直横截面视图。参考图15，栅极连接器42布置在半导体主体100的第一表面101的顶部上，并且通过绝缘层52与半导体主体100绝缘。该绝缘层52和上述的绝缘层51可以由相同层形成。此外，栅极连接器42包括接触插塞43，其延伸通过绝缘层52直到栅电极15。根据一个示例，如图14所示，栅电极15在水平方向上延伸超过源极导体21，而源极区12和主体区13终止于源极导体21下方。根据一个示例，栅极电介质16在其中栅电极15连接到栅极连接器42的区域中比其中其邻接源极区12的那些区域中更厚。在图14和15中，附图标记16''表示具有更大厚度的栅极电介质16的部分。根据一个示例，栅极沟槽的宽度在源电极21下方和在栅极连接器42下方基本上相同。在这种情况下，栅电极15包括具有减小的厚度的部分15''，其邻接更厚的栅极电介质部分16''。根据另一示例（未示出），栅极沟槽可以在栅极连接器42下方更宽，使得栅电极15可以在栅极连接器和源电极21下方具有基本上相同的宽度，并且栅极电介质16可以在栅极连接器42下方比在源电极21下方更厚。
图16示出了图14和15中所示的晶体管器件在垂直截面G-G中的垂直横截面视图，该垂直截面G-G平行于栅电极15并切穿源极区12和主体区13。在图16中，除了源极导体21和栅极连接器42之外，还图示了源极夹32。在他的示例中，源极夹32的边缘与源极导体21的边缘间隔开。然而，这仅是示例。根据另一示例，源极夹32在横向方向上延伸到源极导体21的边缘。源极导体21的“边缘”在横向方向上终止源极导体21。等效地，源极夹32的“边缘”也在横向方向上终止源极夹32。“横向”是与半导体主体100的第一表面101和第二表面102平行的方向。
图17示出了图14至16所示的布置的修改。在图17所示的示例中，栅极连接器42嵌入在源极导体21中。即，源极导体21的部分覆盖栅极连接器42，其中，源极导体21通过绝缘层53与栅极连接器42电绝缘。根据一个示例，源极导体21包括两个导电层：第一层211和形成在第一层211之上的第二层212。根据一个示例，第一层211是AlCu层，并且第二层212是Cu层。栅极连接器42可以由与源极导体21的第一层211相同的材料形成。根据一个示例，源极导体21的第一层211和栅极连接器42通过相同的制造过程来形成。图17示出了晶体管器件1在等效于图16中所示的截面G-G的截面中的垂直横截面视图，使得在图17中示出了栅极连接器42，而没有栅电极15和接触插塞43。
图17示出了第一有源器件区110、源极导体21和接触夹31的垂直横截面视图。然而，第二有源器件区120中的晶体管单元可以以相同的方式连接到栅极连接器。
参考图17，可以在栅极连接器42下方省略源极区12。也就是说，晶体管单元不延伸到栅极连接器42下方。因此，有源器件区110可以包括在栅极连接器42下方的无源区域。与不包括无源区域的有源器件区110相比，这些无源区域增加了图17中所示的第一有源器件区110的面积特定导通电阻。根据一个示例，第一有源器件区110和第二有源器件区120中的栅电极以相同的方式连接到栅极连接器。晶体管器件包括至少一个栅极连接器。根据一个示例，仅存在一个栅极连接器，并且第一有源器件区110和第二有源器件区120中的栅电极连接到该一个栅极连接器。根据另一示例，存在几个栅极连接器。这几个栅极连接器中的每个可以连接到第一有源器件区110和第二有源器件区120中的栅电极。根据另一示例，至少一个栅极连接器仅连接到第一有源器件区110中的栅电极，并且另一栅极连接器仅连接到第二有源器件区120中的栅电极。
此外，根据一个示例，第一有源器件区110中的无源区域的总面积相对于第一有源器件区110的总面积之间的比率可以基本上与第二有源器件区120中的无源区域相对于第二有源器件区120的总面积之间的比率相同。在这种情况下，第二有源器件区120的面积特定导通电阻将与第一有源器件区110的面积特定导通电阻相同，如果这些第一和第二有源器件区都仅用第一类型晶体管单元实现的话。然而，取决于如何实现栅极连接器42，第一有源器件区110可以按与其总面积的比例比第二有源区120包括更大部分的无源区域，或者第二有源器件区120可以按与其总面积的比例比第一有源区110包括更大部分的无源区域。根据一个示例，第一有源区110和第二有源区120中的每个中的无源部分按与相应的总面积的比例小于10％或甚至小于5％。在任何情况下，通过在第二有源器件区120中实现至少一些第二类型晶体管单元10'，可以相对于第一有源器件区110的面积特定导通电阻增大第二有源器件区120的面积特定导通电阻。
图18A和18B分别示出了参考图17解释的晶体管器件的修改的水平横截面视图和垂直横截面视图。在该示例中，每个晶体管单元10包括在半导体主体100中的栅电极15下方布置的场电极17。这些场电极17中的每个包括至少一个部分19，其中场电极17延伸到半导体主体100的第一表面101并且通过延伸通过绝缘层51的接触插塞25电连接到源极导体21。接触插塞25可以是细长插塞（如以图18A中的虚线所示），其连接到场电极17和主体区13。也可以称为源极连接器的该细长接触插塞25与具有栅电极15和场电极17的沟槽交叉。根据一个示例，接触插塞25的纵向方向基本上垂直于这些沟槽。根据另一示例，存在多个接触插塞25，其中这些接触插塞中的每个仅连接到相应的场电极部分19。其中源极导体21经由至少一个接触插塞25连接到场电极17的区域在下文中被称为场电极接触区域，其中在图18A和18B中示出了仅一个场电极接触区域。
如从图18B可以看出的，延伸到第一表面101的场电极部分19中断栅电极15并且与栅电极15电绝缘。因此，根据一个示例，由场电极部分19分开的每个栅电极部分15连接到栅极连接器42。然而，在图18A中，示出了这些栅极连接器42中的仅一个。根据一个示例，晶体管器件包括多个栅极连接器42和场电极接触区域，其中栅极连接器42和场电极接触区域交替布置。
参考图18A，可以在源极连接器25下方省略源极区12，使得在源极连接器25下方，晶体管器件以与在栅极连接器42下方相同的方式包括无源区域。根据一个示例，第一有源器件区110中的源极连接器25下方形成的无源区域的总面积相对于第一有源器件区110的面积之间的比率可以基本上等于第二有源器件区120中的源极连接器下方的无源区域的总面积相对于第二有源器件区120的面积之间的比率。然而，取决于如何实现源极连接器25，第一有源器件区110可以按与其总面积的比例比第二有源区120包括更大部分的无源区域，或者第二有源器件区120可以按与其总面积的比例比第一有源区110包括更大部分的无源区域。根据一个示例，第一有源区110和第二有源区120中的每个中的无源部分按与相应的总面积的比例小于10％或甚至小于5％，其中该无源部分可以包括在栅极连接器42和/或源极连接器25下方的无源区域。在任何情况下，通过在第二有源器件区120中实现至少一些第二类型晶体管单元10'，可以相对于第一有源器件区110的面积特定导通电阻增大第二有源器件区120的面积特定导通电阻。
应当注意，在参考图14至18B解释的每个示例中，一个栅极连接器可以连接到第一有源器件区100中的第一类型晶体管单元10的栅电极15和第二有源器件区120中的第一类型晶体管单元10和/或第二类型晶体管单元10'的栅电极。
在图1所示的示例中，栅极焊盘41靠近半导体主体100的边缘布置在半导体主体100的第一表面101的顶部上，并且在三个侧上与源极导体21邻近。根据图19所示的另一示例，栅极焊盘41在半导体主体100的角部中布置在第一表面101的顶部上，使得栅极焊盘41仅在其两侧上与源极导体21邻近。根据一个示例，这些示例中的每个中的栅极焊盘41通过上述的绝缘层51、52中的一个与半导体主体100绝缘，并且电连接到至少一个栅极连接器42。
图20示出了图1中所示的晶体管器件的另一修改。在该示例中，源极夹31包括彼此间隔开的两个源极夹部分311、312。根据图21中所示的另一示例，源极夹31是U形的，其中具有两个腿部31I、31II。在这些示例中的每个中，第一有源器件区由被源极导体21和源极夹31两者覆盖的那些区域形成，也就是说，由图20中所示的部分311、312中的一个形成或者由图21中所示的腿部31I、31II中的一个形成。
参考图22，晶体管器件1可以包括封装半导体主体100的壳体20。壳体200可以包括模塑料，诸如环氧基模塑料。源极夹31的部分可以从壳体200突出并且可以连接到诸如PCB的载体300。参考图22，漏电极33可以安装在导电载体35上，其中将漏电极33安装到载体35上可以包括焊接或胶合中的一种，使得在漏电极33和载体35之间形成焊料或胶合剂/粘合剂层34。导电载体35可以被实现为引线框架并且可以包括从壳体20突出的腿部。晶体管器件可以包括从壳体200突出并且电连接到栅极焊盘41的另一腿部（图22中未示出）。该腿部可以通过接合线、扁平导体等连接到栅极焊盘41。
根据图23中所示的另一示例，源极夹31连接到壳体200内的另一导体36，并且另一导体36从壳体突出。根据一个示例，另一导体36是引线框架的部分，其未连接到在其上安装漏电极33的部分35。
图24示出了图23中所示的晶体管器件的修改。在该示例中，漏电极33直接安装到载体300。在这种情况下，壳体200是可选的。
虽然本公开不限于此，但以下编号的示例展示了本公开的一个或多个方面。
示例1.一种晶体管器件，包括：半导体主体；源极导体，在半导体主体顶部上；源极夹，在源极导体顶部上并且电连接到源极导体；第一有源器件区，布置在半导体主体中，被源极导体和源极夹覆盖，并包括至少一个器件单元；和第二有源器件区，布置在半导体主体中，被源极夹未覆盖的源极导体的区域覆盖并且包括至少一个器件单元，其中第一有源器件区具有第一面积特定导通电阻，其中第二有源器件区具有第二面积特定导通电阻，并且其中第二面积特定导通电阻大于第一面积特定导通电阻。
示例2.根据示例1的晶体管器件，其中第二面积特定导通电阻与第一面积特定导通电阻之间的比率为至少1.2、至少1.5、至少2或至少5。
示例3.根据示例1至2的任何组合的晶体管器件，其中，第一有源器件区的至少一个器件单元包括至少一个第一类型晶体管单元，其中至少一个第一类型晶体管单元包括：漂移区；源极区，连接到源极导体；主体区，布置在源极区和漂移区之间；和栅电极，与主体区邻近，通过栅极电介质与主体区介电绝缘，并连接到栅极节点。
示例4.根据示例1至3的任何组合的晶体管器件，其中，至少一个第一类型晶体管单元还包括：场电极，与漂移区邻近，并通过场电极电介质与漂移区介电绝缘。
示例5.根据示例1至4的任何组合的晶体管器件，其中，第二有源器件区的至少一个器件单元包括与第一类型晶体管单元不同的至少一个第二类型晶体管单元。
示例6.根据示例1至5的任何组合的晶体管器件，其中，第二有源器件区的至少一个器件单元还包括至少一个第一类型晶体管单元。
示例7.根据示例1至6的任何组合的晶体管器件，其中，第二类型晶体管单元与第一类型晶体管单元的不同之处在于从包括以下各项的组中选择的至少一个特征：第二类型晶体管单元的主体区的掺杂浓度比第一类型晶体管单元的主体区的掺杂浓度高；或第二类型晶体管单元的栅极电介质比第一类型晶体管单元的栅极电介质厚。
示例8.根据示例1至7的任何组合的晶体管器件，其中，第二类型晶体管单元与第一类型晶体管单元的不同之处在于从包括以下各项的组中选择的至少一个特征：第二类型晶体管单元的栅电极连接到源极导体；或第二类型晶体管单元不包括源极区。
示例9.根据示例1至8的任何组合的晶体管器件，其中，第一有源器件区仅包括至少一个第一类型晶体管单元。
示例10.根据示例1至9的任何组合的晶体管器件，其中，第二有源器件区包括多个第一类型晶体管单元和多个第二类型晶体管单元，其中，第二有源器件区中的第一类型晶体管单元的数量和第二类型晶体管单元的数量之间的比率在20：1和1：20之间。
示例11.根据示例1至10的任何组合的晶体管器件，其中，第一有源器件区的尺寸与第二有源器件区的尺寸之间的比率大于5或大于10。
示例12.根据示例1至11的任何组合的晶体管器件，还包括：栅极焊盘，布置在半导体主体的顶部上并与源极导体间隔开；和至少一个栅极连接器，电连接到至少一个第一类型晶体管单元的栅电极和栅极焊盘。
示例13.根据示例1至12的任何组合的晶体管器件，其中，栅极连接器在半导体主体的水平方向上与源极导体间隔开。
示例14.根据示例1至13的任何组合的晶体管器件，其中，栅极连接器嵌入在源极导体中并与源极导体21电绝缘。
示例15.根据示例1至14的任何组合的晶体管器件，其中，第一面积特定导通电阻由在晶体管器件的导通状态下的第一有源器件区中实现的至少一个器件单元的电阻乘以第一有源器件区的面积给出，并且其中，第二面积特定导通电阻由在晶体管器件的导通状态下的第二有源器件区中实现的至少一个器件单元的电阻乘以第二有源器件区的面积给出。
虽然已经参考说明性实施例描述了本发明，但是描述并不旨在以限制意义来解释。当参考描述时，说明性实施例的各种修改和组合以及本发明的其他实施例对于本领域技术人员将是显而易见的。

Claims (15)

1.一种晶体管器件，包括：
半导体主体（100）；
源极导体（21），在半导体主体（100）顶部上；
源极夹（31），在源极导体（21）顶部上并且电连接到源极导体（21）；
第一有源器件区（110），布置在半导体主体（100）中，被源极导体（21）和源极夹（31）覆盖，并包括至少一个器件单元（10）；和
第二有源器件区（120），布置在半导体主体（100）中，被源极夹（31）未覆盖的源极导体（21）的区域覆盖并且包括至少一个器件单元（10、10'），
其中第一有源器件区（110）具有第一面积特定导通电阻，
其中第二有源器件区（120）具有第二面积特定导通电阻，并且
其中第二面积特定导通电阻大于第一面积特定导通电阻。
2.根据权利要求1所述的晶体管器件，
其中第二面积特定导通电阻与第一面积特定导通电阻之间的比率为至少1.2、至少1.5、至少2或至少5。
3.根据权利要求1或2所述的晶体管器件，
其中，第一有源器件区（110）的至少一个器件单元包括至少一个第一类型晶体管单元（10），
其中，至少一个第一类型晶体管单元（10）包括：
漂移区（11）；
源极区（12），连接到源极导体（21）；
主体区（13），布置在源极区（12）和漂移区（11）之间；和
栅电极（15），与主体区（13）邻近，通过栅极电介质（16）与主体区（13）介电绝缘，并连接到栅极节点（G）。
4.根据权利要求3所述的晶体管器件，其中，至少一个第一类型晶体管单元（10）还包括：
场电极（17），与漂移区邻近，并通过场电极电介质与漂移区（11）介电绝缘。
5.根据权利要求3或4所述的晶体管器件，
其中，第二有源器件区（120）的至少一个器件单元包括与第一类型晶体管单元（10）不同的至少一个第二类型晶体管单元（10'）。
6.根据权利要求5所述的晶体管器件，其中，第二有源器件区（120）的至少一个器件单元还包括至少一个第一类型晶体管单元。
7.根据权利要求5或6所述的晶体管器件，其中，第二类型晶体管单元（10'）与第一类型晶体管单元（10）的不同之处在于从包括以下各项的组中选择的至少一个特征：
第二类型晶体管单元（10'）的主体区（13'）的掺杂浓度比第一类型晶体管单元（10）的主体区（13）的掺杂浓度高；或
第二类型晶体管单元（10'）的栅极电介质（16'）比第一类型晶体管单元的栅极电介质厚。
8.根据权利要求6所述的晶体管器件，其中，第二类型晶体管单元（10'）与第一类型晶体管单元（10）的不同之处在于从包括以下各项的组中选择的至少一个特征：
第二类型晶体管单元（10'）的栅电极（15）连接到源极导体（21）；或
第二类型晶体管单元（10'）不包括源极区。
9.根据权利要求3至8中任一项所述的晶体管器件，其中，第一有源器件区仅包括至少一个第一类型晶体管单元（10）。
10.根据权利要求6至9中任一项所述的晶体管器件，
其中，第二有源器件区（120）包括多个第一类型晶体管单元（10）和多个第二类型晶体管单元（10'），
其中，第二有源器件区中的第一类型晶体管单元的数量和第二类型晶体管单元的数量之间的比率在20：1和1：20之间。
11.根据前述权利要求中任一项所述的晶体管器件，其中，第一有源器件区（110）的尺寸与第二有源器件区（120）的尺寸之间的比率大于5或大于10。
12.根据权利要求3至11中任一项所述的晶体管器件，还包括：
栅极焊盘（41），布置在半导体主体（100）的顶部上并与源极导体间隔开；和
至少一个栅极连接器（42），电连接到至少一个第一类型晶体管单元（10）的栅电极（15）和栅极焊盘（41）。
13.根据权利要求12所述的晶体管器件，
其中，栅极连接器（42）在半导体主体（100）的水平方向上与源极导体（21）间隔开。
14.根据权利要求12所述的晶体管器件，
其中，栅极连接器（42）嵌入在源极导体（21）中并与源极导体21电绝缘。
15.根据前述权利要求中任一项所述的晶体管器件，
其中，第一面积特定导通电阻由在晶体管器件的导通状态下的第一有源器件区（110）中实现的至少一个器件单元的电阻乘以第一有源器件区（110）的面积给出，并且
其中，第二面积特定导通电阻由在晶体管器件的导通状态下的第二有源器件区（120）中实现的至少一个器件单元的电阻乘以第二有源器件区（120）的面积给出。
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