CN200969352Y - 横向dmos结构 - Google Patents

横向dmos结构 Download PDF

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CN200969352Y
CN200969352Y CNU2006201148365U CN200620114836U CN200969352Y CN 200969352 Y CN200969352 Y CN 200969352Y CN U2006201148365 U CNU2006201148365 U CN U2006201148365U CN 200620114836 U CN200620114836 U CN 200620114836U CN 200969352 Y CN200969352 Y CN 200969352Y
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dmos
diffusion region
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刘先锋
任冲
黄海涛
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BCD Semiconductor Manufacturing Ltd
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Abstract

本实用新型揭示了一种横向DMOS结构，在栅极靠近漏极的一侧具有低浓度掺杂的P区。该横向DMOS结构在靠近栅极的表面电场强度被削弱。采用本实用新型的技术方案，能有效降低栅极附近的电场大小，从而增加DMOS器件的安全工作区域的大小并提高器件长期工作的可靠性。并且不需要增加制造的成本。

Description

横向DMOS结构
技术领域
本实用新型涉及电子器件及其半导体制造工艺领域，更具体地说，涉及一种横向DMOS结构。
背景技术
在DMOS器件，特别是通过半导体制造工艺制造的DMOS器件中，器件的安全工作区域的大小以及器件的长期工作的可靠性是两个重要的性能指标。对于DMOS器件来说，栅极附近的电场强度直接影响了上述两个性能指标，栅极附近的电场会引起表面电子碰撞电离，从而影响安全工作区域的大小以及器件长期工作的可靠性，
因此，如何有效降低并控制栅极附近的电场大小，将直接影响到DMOS器件的安全工作区域的大小以及器件的长期工作的可靠性。
实用新型内容
本实用新型的目的是提供一种新型的横向DMOS结构，其能够有效降低栅极附近的电场大小，增加DMOS器件的安全工作区域的大小并提高器件长期工作的可靠性。
根据本实用新型，提供一种横向DMOS结构，在栅极靠近漏极的一例具有低浓度掺杂的P区。
根据本实用新型的横向DMOS结构，靠近栅极的表面电场强度被削弱。靠近栅极的表面电子碰撞电离强度被削弱至没有低浓度掺杂的P区时的1/6。
其中，该横向DMOS的源极形成在下述结构上：P型衬底上定义一N型埋层，在该N型埋层上形成N阱，在N阱中形成P型本体，在P型本体中形成N+扩散区并在N+扩散区的侧方形成N型LDD结构，在该N+扩散区中形成P+扩散区并通过通孔引出金属触点作为横向DMOS的源极。
该横向DMOS的漏极形成在下述结构上：P型衬底上定义一N型埋层，在该N型埋层上形成N阱，在N阱中形成N+扩散区，该N+扩散区通过通孔引出金属触点作为横向DMOS的漏极。
该横向DMOS的栅极形成在下述结构上：P型衬底上定义一N型埋层，在该N型埋层上形成N阱，在该N阱上形成由隔离层包裹的多晶硅层作为横向DMOS的栅极；其中栅极区域要覆盖到所述DMOS源极的P型本体、并且需要覆盖到在P型本体中形成的N+扩散区以及N型LDD结构，栅极区域还要覆盖到所述DMOS漏极的N+扩散区，其中所述低浓度掺杂的P区在所述N阱中形成，相邻于横向DMOS的漏极的N+扩散区。
并且，该横向DMOS采用下述结构与其他器件隔离：P型衬底上定义一P型埋层，在该P型埋层上形成P阱，在P阱上形成隔离层。
根据一实施例，数个横向DMOS形成组合器件，所述组合器件的两侧具有隔离结构；其中，相邻的两个横向DMOS结构共用源极，其中所述源极在N+扩散区的两侧都形成N型LDD结构；或者相邻的两个横向DMOS结构共用漏极，其中所述漏极在N+扩散区的两侧都形成低浓度掺杂的P区。
根据本发明的一实施例，该低浓度掺杂的P区可通过硼离子注入形成。
采用本实用新型的技术方案，能有效降低栅极附近的电场大小，从而增加DMOS器件的安全工作区域的大小并提高器件长期工作的可靠性。
附图说明
本实用新型的上述的以及其他的特征、性质和优势将通过下面结合附图和实施例的描述而变得更加明显，附图中相同的附图标记始终表示相同的特征，其中，
图1是根据本实用新型的一实施例的横向DMOS结构的截面图；
图2是采用本实用新型的结构的横向DMOS在Vgs＝8V，Vds＝16V时，栅极附近的表面电子碰撞电离强度与传统结构的DMOS在栅极附近的电子碰撞电离强度的比较；
图3-图6是形成本实用新型的横向DMOS结构的工艺流程。
具体实施方式
下面结合附图和实施例进一步说明本实用新型的技术方案。
本实用新型的目的是提供一种横向DMOS结构，在栅极靠近漏极的一侧具有低浓度掺杂的P区。参考图1所示，图1是根据本实用新型的一实施例的横向DMOS结构的截面图。其在栅极靠近漏极的一侧具有低浓度掺杂的P区(P-)。
由于该低浓度掺杂的P区(P-)的存在，可以使得靠近栅极的表面电场强度被削弱。参考图2所示，图2是采用本实用新型的结构的横向DMOS在栅极附近的表面电子碰撞电离强度与传统结构的DMOS在栅极附近的表面电子碰撞电离强度的比较。图2中菱形点划线是表示传统结构的横向DMOS的表面电子碰撞电离强度分布，而正方形点划线是表示根据本发明的横向DMOS的表面电子碰撞电离强度分布，在3微米左右的区域就是对应栅极的区域，可见，在图2所示的实施例中，传统结构的横向DMOS在栅极附近的表面电子碰撞电离强度为1.8E+25，而采用本实用新型的结构的横向DMOS的栅极附近的表面电子碰撞电离为3.0E+24。基本只有传统结构的1/6。这样，可以很好地降低由于表面电场而引起的表面电子电离，从而增大该横向DMOS的安全工作区域(SOA)并提高该横向DMOS长期工作的可靠性。同时，其他区域的表面电场强度基本没有变化，以确保该横向DMOS器件的其他性能与传统结构的横向DMOS保持一致。
继续参考图1，根据本实用新型，该横向DMOS结构的源极形成在下述结构上：P型衬底(P-Substrate)上定义一N型埋层(BN)，在该N型埋层上形成N阱(N-well)，在N阱(N-well)中形成P型本体(Pbody)，在P型本体(Pbody)中形成N+扩散区(N+)并在N+扩散区(N+)的侧方形成N型LDD结构(NLDD)，该N+扩散区(N+)中形成P+扩散区(P+)并通过通孔引出金属触点(M1)作为横向DMOS的源极。
该横向DMOS的漏极形成在下述结构上：P型衬底(P-Substrate)上定义一N型埋层(BN)，在该N型埋层(BN)上形成N阱(N-well)，在N阱(N-well)中形成N+扩散区(N+)，该N+扩散区(N+)通过通孔引出金属触点(M1)作为横向DMOS的漏极。
该横向DMOS的栅极形成在下述结构上：P型衬底(P-Substrate)上定义一N型埋层(BN)，在该N型埋层(BN)上形成N阱(N-well)，在该N阱(N-well)上形成由隔离层包裹的多晶硅层(Poly)作为横向DMOS的栅极；其中栅极区域要覆盖到DMOS源极的P型本体(Pbody)、并且需要覆盖到在P型本体(Pbody)中形成的N+扩散区(N+)以及N型LDD结构(NLDD)，栅极区域还要覆盖到DMOS漏极的N+扩散区(N+)，其中低浓度掺杂的P区(P-)在N阱(N-well)中形成，相邻于横向DMOS的漏极的N+扩散区(N+)。
该横向DMOS采用下述结构与其他器件隔离：P型衬底(P-Substrate)上定义一P型埋层(BP)，在该P型埋层(BP)上形成P阱(P-well)，在P阱(P-well)上形成隔离层。
继续参考图1，根据本实用新型，该横向DMOS结构可用于数个横向DMOS形成组合器件，组合器件的两侧具有隔离结构；其中，相邻的两个横向DMOS结构共用源极，此时源极在N+扩散区的两侧都形成N型LDD结构；或者相邻的两个横向DMOS结构共用漏极，此时漏极在N+扩散区的两侧都形成低浓度掺杂的P区。
同样根据本实用新型，该横向DMOS结构中的低浓度掺杂的P区(P-)可通过硼离子注入形成，也可以通过注入硼离子形成P型LDD结构而得到。
图3-图6是形成本实用新型的横向DMOS结构的工艺流程。其基本工艺流程如下：
首先在P型衬底(P-Substrate)上需要制作器件的区域定义一N型埋层(BN)，而在该区域的周围定义隔离用的P型埋层(BP)。之后在N型埋层(BN)上形成N阱(N-well)，N阱(N-well)用来形成器件，并在P型埋层(BP)上形成P阱(P-well)，P阱(P-well)起到隔离器件的作用。之后在N阱(N-well)中准备作为源极的区域形成P型本体(Pbody)，在准备形成栅极的区域铺设多晶硅(Poly)，多晶硅与P型本体(Pbody)以及N阱(N-well)之间采用氧化层隔开。同时，还需要在必要的区域形成氧化层。上述步骤参考图3，需要注意，图3-图5所示的是形成一组合器件，即两个相邻并且共用源极的横向DMOS的实施例。因此，在P型本体(Pbody)的两侧各铺设了多晶硅(Poly)作为两个横向DMOS的栅极。
之后，参考图4，进行氧化、光刻等步骤，由于这些步骤与常用的半导体制造工艺流程相同，这里不详细描述。此处需要在对应横向DMOS漏极的区域注入形成N+扩散区(N+)。
之后参考图5，在将要作为源极的P型本体(Pbody)中也形成N+扩散区(N+)，在该N扩散区(N+)中形成P+扩散区(P+)，还在N+扩散区(N+)的侧方形成N型LDD结构(NLDD)，需要注意，该N型LDD结构(NLDD)紧靠N+扩散区(N+)，并且也要为于P型本体(Pbody)中，由于该实施例是形成一组合器件，即两个相邻并且共用源极的横向DMOS，在N+扩散区(N+)的两侧都需要形成N型LDD结构(NLDD)。此外，还需要形成低浓度掺杂的P区(P-)，该低浓度掺杂的P区(P-)形成在栅极对应的区域，并且靠近准备形成漏极的N+扩散区(N+)。根据本实用新型，该低浓度掺杂的P区(P-)可通过硼离子注入形成，也可以通过注入硼离子形成P型LDD结构而得到。根据图5，使隔离层包裹的多晶硅层(Poly)就形成横向DMOS的栅极；其中栅极区域要覆盖到DMOS源极的P型本体(Pbody)、并且需要覆盖到在P型本体(Pbody)中形成的N+扩散区(N+)以及N型LDD结构(NLDD)，栅极区域还要覆盖到DMOS漏极的N+扩散区(N+)，而上述的低浓度掺杂的P区(P-)在N阱(N-well)中形成，相邻于横向DMOS的漏极的N+扩散区(N+)。
最后，参考图6，在经过通孔、金属注入，光刻、氧化、隔离层铺设等一系列的步骤之后，形成一双DMOS器件，其中两个DMOS共用一个源极，它们的源极和漏极分别由通过通孔的金属触点(M1)引出。图6所示的步骤与现有的半导体制造工艺流程相同，因此不再详细说明。
采用本实用新型的技术方案，能有效降低栅极附近的电场大小，从而增加DMOS器件的安全工作区域的大小并提高器件长期工作的可靠性。并且，本实用新型的制造工艺流程基本和现有技术中制造CMOS或者DMOS的工艺流程相似，仅仅增加了形成低浓度掺杂的P区(P-)的步骤，而该低浓度掺杂的P区(P-)可通过硼离子注入形成，也可以通过注入硼离子形成P型LDD结构而得到(两者都是常规的工艺步骤)，因此采用本实用新型的横向DMOS结构并不需要增加制造的成本。
上述实施例是提供给熟悉本领域内的人员来实现或使用本实用新型的，熟悉本领域的人员可在不脱离本实用新型的发明思想的情况下，对上述实施例做出种种修改或变化，因而本实用新型的保护范围并不被上述实施例所限，而应该是符合权利要求书提到的创新性特征的最大范围。

Claims (7)

1.一种横向DMOS结构，其特征在于，在栅极靠近漏极的一侧具有低浓度掺杂的P区。
2.如权利要求1所述的横向DMOS结构，其特征在于，所述横向DMOS的源极形成在下述结构上：
P型衬底上定义一N型埋层，在该N型埋层上形成N阱，在N阱中形成P型本体，在P型本体中形成N+扩散区并在N+扩散区的侧方形成N型LDD结构，在该N+扩散区中形成P+扩散区并通过通孔引出金属触点作为横向DMOS的源极。
3.如权利要求2所述的横向DMOS结构，其特征在于，所述横向DMOS的漏极形成在下述结构上：
P型衬底上定义一N型埋层，在该N型埋层上形成N阱，在N阱中形成N+扩散区，该N+扩散区通过通孔引出金属触点作为横向DMOS的漏极。
4.如权利要求3所述的横向DMOS结构，其特征在于，所述横向DMOS的栅极形成在下述结构上：
P型衬底上定义一N型埋层，在该N型埋层上形成N阱，在该N阱上形成由隔离层包裹的多晶硅层作为横向DMOS的栅极；其中
所述栅极区域要覆盖到所述DMOS源极的P型本体、并且需要覆盖到在P型本体中形成的N+扩散区以及N型LDD结构，
所述栅极区域还要覆盖到所述DMOS漏极的N+扩散区，其中所述低浓度掺杂的P区在所述N阱中形成，相邻于横向DMOS的漏极的N+扩散区。
5.如权利要求4所述的横向DMOS结构，其特征在于，所述横向DMOS采用下述结构与其他器件隔离：
P型衬底上定义一P型埋层，在该P型埋层上形成P阱，在P阱上形成隔离层。
6.如权利要求5所述的横向DMOS结构，其特征在于，数个横向DMOS形成组合器件，所述组合器件的两侧具有隔离结构；其中，
相邻的两个横向DMOS结构共用源极，其中所述源极在N+扩散区的两侧都形成N型LDD结构；或者
相邻的两个横向DMOS结构共用漏极，其中所述漏极在N+扩散区的两侧都形成低浓度掺杂的P区。
7.如权利要求1至6中任一项所述的横向DMOS结构，其特征在于，所述低浓度掺杂的P区通过硼离子注入形成。
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Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242841A (en) * 1992-03-25 1993-09-07 Texas Instruments Incorporated Method of making LDMOS transistor with self-aligned source/backgate and photo-aligned gate
US5559044A (en) * 1992-09-21 1996-09-24 Siliconix Incorporated BiCDMOS process technology
US7365402B2 (en) * 2005-01-06 2008-04-29 Infineon Technologies Ag LDMOS transistor

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