CN1279620C - 性能改善的双扩散金属氧化物半导体的晶体管结构 - Google Patents

性能改善的双扩散金属氧化物半导体的晶体管结构 Download PDF

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CN1279620C
CN1279620C CNB018058078A CN01805807A CN1279620C CN 1279620 C CN1279620 C CN 1279620C CN B018058078 A CNB018058078 A CN B018058078A CN 01805807 A CN01805807 A CN 01805807A CN 1279620 C CN1279620 C CN 1279620C
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石甫渊
苏根政
崔炎曼
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General Semiconductor Inc
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Abstract

提供一种凹槽DMOS晶体管结构，其包括至少三个在第一导电型的衬底上形成的独立凹槽DMOS晶体管单元。多个独立DMOS晶体管单元被分为外围晶体管单元和内部晶体管单元。每个独立晶体管单元包含位于衬底上的第二导电型体区。至少有一条凹槽延伸穿过体区和衬底。绝缘层与凹槽对齐。凹槽中有一设在绝缘层上的导电电极。每个内部晶体管单元(不是外围晶体管单元)还包括第一导电型的源区，其位于与凹槽相邻的体区中。

Description

性能改善的双扩散金属氧化物半导体的晶体管结构
技术领域
本发明涉及具有在凹槽中生成的栅极的电流切换DMOS(金属氧化物半导体)晶体管，尤其是涉及在器件导通时具有低阻值的凹槽DMOS晶体管。
背景技术
DMOS功率晶体管被广泛用于众多领域，其中包括汽车电子设备、磁盘驱动器和电源。通常，这些器件的功能就像开关，被用于连接电源和负载。当开关闭合时，保证器件阻值尽可能低是非常重要的。否则，会浪费能源，同时产生过多的热量。
一个典型的分立DMOS电路包括至少两个并列制造的独立DMOS晶体管单元。当每个独立DMOS晶体管单元的源极被金属短接，同时其栅极被多晶硅短接时，它们共用漏极触点(衬底)。因此，尽管分立DMOS电路是由更小的晶体管阵列构成的，它的性能却像一个大的晶体管。当通过栅极将晶体管阵列接通时，对于分立DMOS电路，期望使单位面积导电率最大。
图1给出了这样一个器件，即DMOS晶体管100中一个独立单元的剖面图，图2为该单元的透视剖面图。栅极102和104各自生成于凹槽中，并被栅极氧化物层包围。凹槽栅极通常生成为栅格型图案，其栅格代表独立的相互连接的栅极，此外，凹槽栅极也常生成为为一连串独特的平行条纹。
DMOS晶体管100为在N-外延层111上生成的双扩散器件。在外延层111的表面生成一N+源区112，同样也在其上生成一P+接触区114。P型体(p-bodty)116位于N+源区112和P+接触区114的下面。一金属源触点118与N+源区112相接，并将N+源区112与P+接触区114、P型区116短接。
N-外延层111在N+衬底120上生成，同时，在N+衬底120的底部有一漏极触点(未示出)。图2给出了栅极102和104的触点121，其是通过延伸凹槽外的导电栅材料，并在远离独立单元处生成一金属接点制成的。图3同样给出了连接了栅极102和104的栅极金属触点121。栅极通常是由掺杂了磷或硼的多晶硅制成的。需要注意的是在生成一串晶体管单元时，栅极触点121只能通过扩展结构中的外围单元获得，而不是通过扩展内部单元获得。
N-外延层111位于N+衬底120和P+型体116之间的区110掺杂N-型杂质的程度通常比N+衬底120要轻。这提高了DMOS晶体管100的耐高电压的能力。区110有时被称为“轻掺杂”或“漂移”区(“漂移”指载流子在电磁场中的运动)。漂移区110和N+衬底120构成了DMOS晶体管100的漏极。
DMOS晶体管100为N-沟道晶体管。当在栅极102施加一正电压时，P型体(p-body)116中接近栅极氧化物层106的沟道区反转，并在N+源区112和N+衬底120之间产生电压差，将有一电子流从源区通过凹槽区流入漂移区110。在漂移区110中，部分电子流以一定角度倾斜地扩展，直至碰到N+衬底120，然后其垂直流向漏极。其它电子流竖直向下流过漂移区110，同时，部分电子流流到栅极102下面，然后向下穿过漂移区110。
栅极102和104用导电材料掺杂。因为DMOS晶体管100为N-沟道器件，所以栅极102和104可以是用磷掺杂的多晶硅。栅极102和104分别通过栅极氧化层106和108与DMOS晶体管100的其余部分绝缘。选择栅极绝缘层106和108的厚度以设定DMOS晶体管100的阈电压，所述厚度还可以影响DMOS晶体管100的击穿电压。
在图1-3中所示的DMOS晶体管中，P+接触区114在凹槽底的下面向下延伸，以在所述单元的中心形成深重度掺杂的P型体116。在其它已知的DMOS晶体管(未示出)中，P+触点区114非常浅，没有延伸到凹槽水平面以下。因此，在这些器件中P+型体116不予考虑。浅的P+接触区有助于保证P-型掺杂物不会进入到沟道区中，这将有益于增加器件的阈电压，同时导致器件导通特性从一次运行到另一次运行取决于P+接触区114的取向都不相同。然而，对于浅P+接触区114，不考虑P+部分116，器件当其被截止时只能承受相对较低的电压(例如10伏)。这是因为分布在P+接触区114和漂移区110之间的结的周围扩展的耗尽层不足以保护凹槽的端角处(例如，图1中所示的端角122)。其结果是在凹槽的周围地区可能发生雪崩击穿，导致产生过大的载流子产生速率，使得栅极氧化物层106被载流子充电或降低质量，在极端情况下，导致栅极氧化物层106损坏。因此，这种已知的DMOS晶体管至多是一种低电压器件。
如前面所述，在图1-3所示的已知DMOS晶体管中，通过将P+接触区114向下延伸到凹槽的底部以下，在单元中心形成一深度重掺杂P型体区116，可以提高其击穿电压。虽然这将在端角122处提供附加保护，但其主要优势是载流子最先在P+型体116的底端302开始产生。这种状况的产生是由于在顶端302下面的电场被增强了，从而导致载流子沿着结的弯曲部分或其顶端产生，而不是在靠近栅极氧化物层106的位置产生。这即使可能减少器件实际的结的击穿电压，但也降低栅极氧化物层106上受到的应力，并提高DMOS晶体管100在高电压条件下的可靠性。在例如美国专利号：5,072,266和5,688,725中能够找到关于向下延伸P接触区的另外的细节。
DMOS晶体管100中的深P+型体虽然能够极大地减小击穿造成的不利结果，但也具有一些不利的影响。首先，由于伴随着单元密度的增大，P离子将百能被引入到凹槽区，因此产生单元密度的上限。如上所述，这将有助于增加DMOS晶体管的阈电压。其次，当电子流离开凹槽进入漂移区110时，深P+型接触体的存在趋于夹断电子流。在已知的不含有深P+型体116的晶体管中，当电子流到达漂移区110时，电子流发生扩展。该电流扩展增加了漂移区110中单位面积上的平均电流，从而降低了DMOS晶体管的导通电阻。深P+型体的存在限制了这种电流扩展，并与高单元密度相一致，提高了导通电阻。
因此，所需的是综合了深P+型体击穿优点和低导通电阻的DMOS晶体管。
发明内容
按照本发明，提供了一种凹槽DMOS晶体管结构，该结构包括在具有第一导电型的衬底上形成的至少三个独立的凹槽晶体管单元。多个独立DMOS晶体管单元被分为外围晶体管单元和内部晶体管单元。每个独立晶体管单元包括位于所述衬底上的具有第二导电类型的体区。所述至少一条凹槽水平延伸穿过体区和衬底。绝缘层衬在所述凹槽内。凹槽中有一设在绝缘层上的导电电极。每个内部晶体管单元(而不是外围晶体管单元)，还包括具有第一导电型的源区，其位于与凹槽相邻的体区中。因此，当内部晶体管单元起作用时，外部晶体管单元不起作用。其结果是，获得低的阈电压，同时不需要深P+接触区。
依照本发明的一个方面，体区平直穿过各晶体管单元分别所处位置的宽度。换句话说，穿过晶体管单元分别所处位置的宽度时体区有双峰式分布。
依照本发明的另一个方面，凹槽延伸到在体区的下面的一个深度。
依照本发明的再一个方面，外围晶体管单元体区的掺杂要远轻于内部晶体管单元体区的掺杂。
依照本发明的另一个方面，提供一种凹槽DMOS晶体管结构，其至少包括在具有第一导电型的衬底上形成的三个独立凹槽晶体管单元。多个独立DMOS晶体管单元被分为外围晶体管单元和内部晶体管单元。每个独立晶体管单元包括位于所述衬底上的具有第二导电类型的体区。体区有穿过各晶体管单元分别所处位置的宽度的双峰式分布。至少一条水平凹槽延伸穿过体区和衬底。绝缘层衬在所述凹槽内。凹槽中有一设在绝缘层上的导电电极。每个内部晶体管还包括具有第一导电类型的源区。源区位于靠近凹槽的体区上。
附图说明
图1和2分别给出了具有相对深的中心p+接触区的常规垂直凹槽的N沟道DMOS晶体管的一个单元的剖面图和透视图。
图3给出了具有相对深的中心p+接触区的常规N沟道DMOS晶体管的另一个剖面图。
图4为依照本发明构造的外围和内部晶体管单元的剖面图。
图5为依照本发明构造晶体管结构的平面图。
图6为本发明可选择的实施方案图。
具体实施方式
图4为一剖面图，图5为凹槽DMOS结构200的一个实施例的平面图，其中，独立单元21在水平剖面图中的形状为矩形。该实施例中的结构包括：n+衬底220，其上生长了一轻n-掺杂的外延层211。在掺杂的外延层211中，提供了具有相反的导电性的接触区和体区214。设在部分体区214上的n-掺杂外延层240用作源极。在外延层上给出了矩形的凹槽202和204，其开口于该结构的上表面并限定了晶体管单元的周界。栅极氧化物层230衬在凹槽202和204的侧壁上。凹槽202和204内填充多晶硅。漏极连接到半导体衬底220的后表面，源极218连接两个源区240和接触区214，栅极221连接到凹槽202中填充的多晶硅上。填充在凹槽内的多晶硅在结构200的表面连续连通。另外，如图4和5所示，延伸在结构200的表面上方的多晶硅221，用于和外围晶体管单元，如单元211，212和213相互连接。内部晶体管单元，如单元214，215和216，相互连接，并通过凹槽本身连接到外围单元上。图4中，凹槽202与外围单元相连，而凹槽204与内部单元相连。
应该注意的是，对于基本的晶体管操作，并不要求晶体管单元21为矩形，通常情况下其为多边形。然而，规则的矩形形状，或规则的六边形形状对于设计是最方便的。换句话说，晶体管单元除了为图中描绘的封闭单元的形状(closed-cell geometry)外，还可能是开放(open)的或条形的几何形状。
如前面所提到的，现有技术的DMOS晶体管中采用的深P+接触区，随着单元密度的提高，也提高了阈电压。深中心P+区将导致器件接通电阻的增大。然而，没有深P+接触区，器件的击穿电压对于许多应用来说就会过低，不能接受。
根据本发明，通过提供晶体管不起作用的外围晶体管单元和晶体管起作用的内部晶体管单元，可以获得低的阈电压，而无需深P+接触区。如图4所示，凹槽202与外围晶体管单元相连，同时凹槽204与内部晶体管单元相连。不起作用的外围晶体管单元与起作用的内部晶体管单元的区别是，不起作用的晶体管的源区被切断了。例如，见图4，与凹槽202相连的外围半导体单元没有源区。另外，与外围晶体管单元相连的P+接触区214比与内部单元相接的P+接触区掺杂程度要轻的多。轻掺杂的结果是，在这些外围单元上不会发生击穿。而这种安排可以确保在内部单元中发生雪崩击穿。因此，本发明的DMOS晶体管阵列可以用于较高电压。另外，由于不需要使用深P+接触区，所以还可以避免阈电压和导通电阻的不适当的提高。
图6给出了本发明的一个特定的实施例，其中，P+接触区614为沿着晶体管单元的宽度的双峰分布，而不是基本上平直的分布。在本发明的这一实施例中，雪崩击穿通常发生在标号610附近。
尽管在这里给出各种实施例的具体图示和描述，但在不背离本发明精神和范围的情况下，在上述教导和附加权利要求范围内覆盖了对其进行形式上和细节上的改动。例如：本发明完全可以应用于不同于这里所描述的各种半导体区域导电性的凹槽DMOS。

Claims (21)

1.一种凹槽DMOS晶体管结构，该结构包括在具有第一导电型衬底上形成的至少三个独立凹槽DMOS晶体管单元，所述多个独立DMOS晶体管单元被分为位于所述结构的外围上的外围晶体管单元和位于所述结构的外围的内部的内部晶体管单元，每个所述独立晶体管单元包括：
位于衬底上的体区，所述体区具有第二种导电类型；
至少一条凹槽延伸到体区中；
衬在凹槽内的绝缘层；
导电电极，在凹槽中设在所述绝缘层上；以及
其中，每个所述内部晶体管单元而不是所述外围晶体管单元，还包括在接近所述凹槽的体区中的具有第一导电类型的源区，
且所述外围晶体管单元体区的掺杂程度要轻于所述内部晶体管单元体区的掺杂程度。
2.如权利要求1所述的凹槽DMOS晶体管结构，其中，所述体区平直穿过各晶体管单元分别所处的位置的宽度。
3.如权利要求1所述的凹槽DMOS晶体管结构，其中，所述至少一条凹槽延伸到低于体区深度的深度。
4.如权利要求1所述的凹槽DMOS晶体管结构，其中，每个所述体区具有穿过所述晶体管单元分别所处的位置的宽度的双峰分布。
5.如权利要求1所述的凹槽DMOS晶体管结构，还包括漏极，其位于与所述体区相对的衬底表面上。
6.如权利要求1所述的凹槽DMOS晶体管结构，其中，所述绝缘层为氧化物层。
7.如权利要求1所述的凹槽DMOS晶体管结构，其中，所述导电电极包括多晶硅。
8.如权利要求1所述的凹槽DMOS晶体管结构，其中，至少一个所述凹槽DMOS晶体管单元具有封闭单元的几何形状。
9.如权利要求8所述的凹槽DMOS晶体管结构，其中，所述封闭单元几何形状为矩形。
10.如权利要求1所述的凹槽DMOS晶体管结构，其中，至少一个所述凹槽DMOS晶体管单元具有开口单元几何形状。
11.如权利要求1所述的凹槽DMOS晶体管结构，还包括多个与外围晶体管单元每个导电电极分别相连的多晶硅触点。
12.如权利要求4所述的凹槽DMOS晶体管结构，还包括多个与所述外围晶体管单元每个导电电极分别相连的多晶硅触点。
13.如权利要求3所述的凹槽DMOS晶体管结构，还包括多个与所述外围晶体管单元每个导电电极分别相连的多晶硅触点。
14.如权利要求1所述的凹槽DMOS晶体管结构，其中，所述体区有穿过晶体管单元分别所处的位置的宽度的双峰式分布，所述至少一条凹槽延伸到低于所述体区的深度。
15.如权利要求14所述的凹槽DMOS晶体管结构，还包括漏极，其位于与所述体区相对的衬底表面上。
16.如权利要求14所述的凹槽DMOS晶体管结构，其中，所述绝缘层为氧化物层。
17.如权利要求14所述的凹槽DMOS晶体管结构，其中，所述导电电极包括多晶硅。
18.如权利要求14所述的凹槽DMOS晶体管结构，其中，至少一个所述DMOS晶体管单元具有封闭单元的几何形状。
19.如权利要求18所述的凹槽DMOS晶体管结构，其中，所述封闭单元的几何形状为矩形。
20.如权利要求14所述的凹槽DMOS晶体管结构，其中，至少所述一个凹槽DMOS晶体管具有开口单元几何形状。
21.如权利要求14所述的凹槽DMOS晶体管结构，还包括分别与每一个所述外围晶体管单元的导电电极连接的多个多晶硅触点。
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