WO2022218031A1 - 一种功率半导体器件的封装结构 - Google Patents

一种功率半导体器件的封装结构 Download PDF

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Publication number
WO2022218031A1
WO2022218031A1 PCT/CN2022/076935 CN2022076935W WO2022218031A1 WO 2022218031 A1 WO2022218031 A1 WO 2022218031A1 CN 2022076935 W CN2022076935 W CN 2022076935W WO 2022218031 A1 WO2022218031 A1 WO 2022218031A1
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WIPO (PCT)
Prior art keywords
lead
area
package structure
semiconductor chip
pin
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PCT/CN2022/076935
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English (en)
French (fr)
Inventor
李高显
王锁海
党晓波
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苏州汇川技术有限公司
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Publication of WO2022218031A1 publication Critical patent/WO2022218031A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present application relates to the technical field of packaging structures, and in particular, to a packaging structure of a power semiconductor device.
  • Power semiconductor devices are mainly used for the power supply and driving loads of various devices.
  • power electronic systems need both power supplies to provide energy for them, and also need to push loads (motors, relays, etc.) to perform processing results. Therefore, power semiconductor devices are very important to power electronic systems. are essential.
  • the application of power semiconductor devices is also in all walks of life. With the upgrading of power semiconductor devices, in addition to the ultra-high power application field still dominated by thyristors, power devices represented by IGBT (insulated gate bipolar transistor) have been dominated.
  • IGBT is a voltage-driven three-terminal device, including gate, emitter and collector, wherein the gate and emitter are usually located on the front side of the chip, and the collector is usually located on the back side of the chip.
  • the existing traditional packaging structure is still basically used.
  • the collector of the IGBT is welded on the base island of the lead frame by soft solder, and the gate is connected by aluminum wires and lead frames.
  • the first pin of the lead frame is connected, and the emitter is connected to the third pin of the lead frame through an aluminum wire.
  • a second pin connected to the base island is provided in the middle of the first pin and the third pin, that is, three pins are provided on the same side of the lead frame, resulting in adjacent
  • the spacing between the two pins is rather limited.
  • the package structure of TO-263 is only suitable for low-power drive systems with a voltage level of 220V, and it is difficult to apply to low-power drive systems with higher voltage levels, for example, power drive systems with voltage levels of 380V and 480V.
  • the purpose of this application is to improve the TO-263 package structure to obtain a package structure suitable for higher voltage levels of power semiconductors, while retaining the available surface mount technology (SMT) of the TO-263 package structure for automatic The advantages of placement.
  • the technical problem to be solved by the present application is to provide a packaging structure of a power semiconductor device, which is suitable for packaging of power semiconductors of higher voltage levels, and can be automatically mounted by a surface mount process.
  • the technical solution adopted in this application is to provide a package structure of a power semiconductor device, the package structure includes a lead frame, a plastic package and a first semiconductor chip, and the package structure further includes a first pin and a second pin, the first pin includes a connected first welding area and a first lead-out area, and the second pin includes a connected second welding area and a second lead-out area; the first The back side of the semiconductor chip is welded on the lead frame, and the front side of the first semiconductor chip is electrically connected to the first bonding area of the first pin and the second bonding area of the second pin respectively through bonding wires ; The first semiconductor chip, the bonding wire, the first bonding area and the second bonding area are packaged in the lead frame through the plastic package; the first lead-out area and the second The lead-out area is exposed on the first side of the plastic package, and only the first lead-out area and the second lead-out area protrude from the first side of the plastic package.
  • the number of the first semiconductor chips is multiple.
  • the package structure further includes a second semiconductor chip packaged in the lead frame through the plastic package, and the backside of the second semiconductor chip is welded to the lead
  • the upper and front surfaces of the frame are electrically connected with the first welding area of the first pins through bonding wires.
  • the number of the second semiconductor chips is multiple.
  • the width of the first bonding area is greater than the width of the second bonding area
  • the first lead-out area includes a distance from the first bonding area away from the first bonding area.
  • a first lead-out section extending from one side of the two pins and a second lead-out section extending from a side of the first bonding area close to the second lead.
  • the applicable package form of the package structure is TO-263, and the dimensions of the first lead-out region, the first lead-out section and the second lead-out section are respectively the same as those of the standard lead-out section.
  • the dimensions of the three pins in the TO-263 package structure are the same.
  • the package structure further includes a third lead directly connected to the lead frame, and the plastic package completely covers the third lead.
  • a side of the lead frame opposite to the first side of the plastic package is provided with a cut corner.
  • the first semiconductor chip is a three-terminal active device, the front side of the first semiconductor chip has an output terminal and a control terminal, and the back side of the first semiconductor chip has an output terminal and a control terminal.
  • the input end is welded with the lead frame, the output end is electrically connected to the first welding area of the first pin through a bonding wire, and the control end is electrically connected to the first pin through a bonding wire the second bonding area of the second pin;
  • the second semiconductor chip is a two-terminal active device, the front side of the second semiconductor chip has an output terminal, and the back side of the first semiconductor chip has an input terminal; The input end is welded with the lead frame, and the output end is electrically connected to the first welding area of the first pin through a bonding wire.
  • the plastic sealing body is made of epoxy plastic sealing material
  • the lead frame is made of copper alloy material
  • the bonding wire is made of copper wire, gold wire, aluminum wire or alloy wire.
  • the present application also relates to a power module comprising a substrate and a power semiconductor device having the above-described packaging structure of the power semiconductor device, the power semiconductor device being mounted on the substrate.
  • the packaging structure for implementing the power semiconductor device of the present application can at least achieve the following functions: the packaging structure includes a lead frame, a plastic package and a first semiconductor chip, the packaging structure further includes a first lead and a second lead, the The first lead includes a connected first welding area and a first lead-out area, and the second lead includes a connected second welding area and a second lead-out area; the backside of the first semiconductor chip is welded on the On the lead frame, the front surface of the first semiconductor chip is electrically connected to the first bonding area of the first pin and the second bonding area of the second pin respectively through bonding wires; the first semiconductor chip, The bonding wire, the first welding area and the second welding area are encapsulated in the lead frame by the plastic package; the first lead-out area and the second lead-out area are exposed to the plastic package The first side of the plastic package has and only the first lead-out area and the second lead-out area protrude from the first side.
  • the packaging structure can be applied to the packaging of power semiconductors with higher voltage levels, and can be automatically mounted by a surface mount process.
  • FIG. 1 is a schematic top view of a package structure provided in Embodiment 1 of the present application.
  • FIG. 2 is a cross-sectional view of a package structure provided in Embodiment 1 of the present application;
  • FIG. 3 is a schematic three-dimensional structural diagram of the packaging structure provided in Embodiment 1 of the present application.
  • FIG. 4 is a schematic top view of the packaging structure provided by the second embodiment of the present application.
  • FIG. 5 is a cross-sectional view of a package structure provided by Embodiment 2 of the present application.
  • FIG. 6 is a schematic three-dimensional structural diagram of the packaging structure provided by the second embodiment of the present application.
  • FIG. 7 is a schematic top view of the package structure provided in Embodiment 3 of the present application.
  • FIG. 8 is a cross-sectional view of a package structure provided in Embodiment 3 of the present application.
  • FIG. 9 is a schematic three-dimensional structural diagram of the packaging structure provided in Embodiment 3 of the present application.
  • FIG. 1 is a schematic top view of the package structure provided in Embodiment 1 of the present application, in which the plastic package 2 is subjected to perspective processing.
  • the package structure includes a lead frame 1 , a plastic package 2 , a first semiconductor chip 3 , a second semiconductor chip 4 , a first lead 6 and a second lead 5 .
  • the first lead 6 includes a connected first welding area 61 and a first lead area 62
  • the second lead 5 includes a connected second welding area 51 and a second lead area 52 .
  • the back of the first semiconductor chip 3 is welded on the lead frame 1 , and the front of the first semiconductor chip 3 is connected to the first bonding area 61 of the first lead 6 and the second bonding wire 8 respectively.
  • the second pad 51 of the pin 5 is electrically connected.
  • the first semiconductor chip 3 is a three-terminal active device, the front side of the first semiconductor chip 3 has an output terminal and a control terminal, and the back side of the first semiconductor chip 3 has an input terminal; the input terminal It is welded with the lead frame 1 , the output terminal is electrically connected to the first welding area 61 of the first pin 6 through the bonding wire 8 , and the control terminal is electrically connected to the The second bonding area 51 of the second pin 5 .
  • FIG. 2 is a cross-sectional view of the package structure provided in the first embodiment of the application. As shown in FIG.
  • FIG. 3 is a schematic three-dimensional structure diagram of the package structure provided in the first embodiment of the present application. As shown in FIG. 3 , the first lead-out area 62 and the second lead-out area 52 are exposed to the plastic sealing body 2 The most important thing is that the first side of the plastic package 2 has and only the first lead-out area 62 and the second lead-out area 52 protrude.
  • the package structure is in the form of TO-263 package.
  • a side of the lead frame 1 opposite to the first side of the plastic package 2 is provided with a cut corner 11 .
  • the molding body 2 is made of epoxy molding material
  • the lead frame 1 is made of copper alloy material
  • the bonding wire 8 is made of copper wire.
  • the first side of the plastic package 2 has and only the first lead-out area 62 and the second lead-out area 52 protrude, so the first lead-out area 62 and the second lead-out area A sufficiently wide spacing can be configured between the regions 52 , so that the phenomenon of breakdown and short circuit will not occur between the first lead-out region 62 and the second lead-out region 52 . Therefore, the packaging structure can be suitable for the packaging of power semiconductors of higher voltage ( ⁇ 1500V) level. Meanwhile, the package structure is in the form of TO-263 package, so the package structure can be automatically mounted by a surface mount process.
  • the number of the first semiconductor chip 3 and the second semiconductor chip 4 is not limited to 1, and may be more, such as 2, 3, 4 and so on.
  • the package structure may also not include the second semiconductor chip 4 .
  • the bonding wire 8 is made of gold wire, aluminum wire or alloy wire.
  • FIG. 4 is a schematic top view of the package structure provided by the second embodiment of the present application. In the figure, a perspective treatment is performed on the plastic package 2 .
  • FIG. 5 is a cross-sectional view of the package structure provided by the second embodiment of the present application. As shown in FIG. 4 and FIG. 5 , the first welding area 61 extends horizontally to one side of the second welding area 51 , so that the width of the first welding area 61 is greater than the width of the second welding area 51 . Referring to FIG. 4 and FIG. 6 , FIG.
  • the first lead-out area 62 includes a A first lead-out segment 621 extending from a side away from the second lead 5 and a second lead-out segment 622 extending from a side of the first bonding area 61 close to the second lead 5 .
  • the dimensions of the first lead-out region 62 , the first lead-out section 621 and the second lead-out section 622 are respectively consistent with the dimensions of the three pins in the standard TO-263 package structure.
  • the first lead-out region 62, the first lead-out region 62, the The dimensions of the first lead-out segment 621 and the second lead-out segment 622 are respectively the first pin connected to the gate, the second pin connected to the collector and the third pin connected to the emitter in the TO-263 package structure are the same size.
  • the package structure of this embodiment can be consistent with the TO-263 package structure in terms of external structure.
  • the overcurrent capability of power semiconductor devices is mainly determined by the overcurrent capability of the third pin connected to the emitter, and the overcurrent capability of the third pin It is determined by the width of the third pin and the bonding area between the chip and the third pin.
  • the first bonding area 61 of the first pin 6 corresponding to the third pin is widened by horizontally extending toward the side of the second bonding area 51, so that the first bonding area 61 is widened.
  • the number and wire diameter of the metal bonding wires 8 to which the region 61 can be bonded is increased, thereby improving the overcurrent capability of the entire package structure.
  • FIG. 7 is a schematic top view of the packaging structure provided in the third embodiment of the present application, in which the plastic packaging body 2 is subjected to perspective processing.
  • the package structure further includes a third lead 7 , and the third lead 7 is arranged between the first lead 6 and the second lead 5 .
  • FIG. 8 is a cross-sectional view of the package structure provided in Embodiment 3 of the present application.
  • the third pin 7 is directly connected to the lead frame 1 .
  • FIG. 9 is a schematic three-dimensional structural diagram of the package structure provided in the third embodiment of the present application.
  • the plastic package 2 completely covers the third lead 7 .

Abstract

一种功率半导体器件的封装结构，包括引线框架、塑封体和第一半导体芯片、第一引脚和第二引脚，所述第一引脚包括相连接的第一焊接区和第一引出区，所述第二引脚包括相连接的第二焊接区和第二引出区；所述第一半导体芯片的背面焊接在所述引线框架上，正面通过键合线分别与所述第一引脚的第一焊接区和所述第二引脚的第二焊接区电性连接；所述第一半导体芯片、所述键合线、所述第一焊接区和所述第二焊接区通过所述塑封体封装于所述引线框架；所述塑封体的第一侧有且仅有所述第一引出区与所述第二引出区伸出。

Description

一种功率半导体器件的封装结构
本申请要求于2021年4月14号申请的、申请号为202120763876.7的中国专利申请的优先权，其全部内容通过引用结合于此。
技术领域
本申请涉及封装结构技术领域，具体涉及一种功率半导体器件的封装结构。
 背景技术
功率半导体器件主要用于各种设备的电源和驱动负载，一般电力电子系统既需要电源为其提供能量，也需要推动负载(电机、继电器等)执行处理结果，所以，功率半导体器件对电力电子系统都是必不可少的。功率半导体器件的应用也遍及于各行各业，随着功率半导体器件的更新换代，除特大功率应用领域仍由晶闸管等统治之外，以IGBT(绝缘栅双极型晶体管)为代表的功率器件已经占据了主导地位。IGBT为电压驱动型的三端器件，包括栅极、发射极和集电极，其中栅极与发射极通常位于芯片的正面，集电极通常位于芯片的背面。
对于IGBT器件，目前基本仍沿用着现有传统的封装架构，以TO-263传统封装结构为例，IGBT的集电极通过软焊料焊接在引线框架的基岛上，栅极通过铝线和引线框架的第一管脚相连，发射极通过铝线和引线框架的第三管脚相连接。现有传统结构中，在第一管脚和第三管脚的中间设有与基岛连接的第二管脚，也就是说，在引线框架的同侧设置了三个管脚，导致相邻的两个管脚之间的间隔相当有限。针对IGBT这样的三端有源器件，第三管脚和第二管脚之间的电压越大，越容易引发第三管脚和第二管脚之间击穿短路。这就导致TO-263这类封装结构仅适用220V电压等级的小功率驱动系统，而难以应用于更高电压等级的小功率驱动系统，例如，380V和480V电压等级的功率驱动系统。本申请的目的就在于对TO-263封装结构进行改进，以得到一种适用于更高电压等级的功率半导体的封装结构，同时保留TO-263封装结构的可用表面贴装工艺(SMT)进行自动贴装的优点。
 技术问题
本申请所要解决的技术问题是提供一种功率半导体器件的封装结构，所述封装结构适用于更高电压等级的功率半导体的封装，同时可用表面贴装工艺进行自动贴装。
 技术解决方案
为解决上述技术问题，本申请所采用的技术方案是提供一种功率半导体器件的封装结构，所述封装结构包括引线框架、塑封体和第一半导体芯片，所述封装结构还包括第一引脚和第二引脚，所述第一引脚包括相连接的第一焊接区和第一引出区，所述第二引脚包括相连接的第二焊接区和第二引出区；所述第一半导体芯片的背面焊接在所述引线框架上，所述第一半导体芯片的正面通过键合线分别与第一引脚的第一焊接区和所述第二引脚的第二焊接区电性连接；所述第一半导体芯片、所述键合线、所述第一焊接区和所述第二焊接区通过所述塑封体封装于所述引线框架；所述第一引出区和所述第二引出区外露于所述塑封体的第一侧，所述塑封体的第一侧有且仅有所述第一引出区与所述第二引出区伸出。
在本申请提供的功率半导体器件的封装结构中，所述第一半导体芯片的数量为多个。
在本申请提供的功率半导体器件的封装结构中，所述封装结构还包括通过所述塑封体封装于所述引线框架内的第二半导体芯片，所述第二半导体芯片的背面焊接在所述引线框架上、正面通过键合线与所述第一引脚的第一焊接区电性连接。
在本申请提供的功率半导体器件的封装结构中，所述第二半导体芯片的数量为多个。
在本申请提供的功率半导体器件的封装结构中，所述第一焊接区的宽度大于所述第二焊接区的宽度，所述第一引出区包括自所述第一焊接区的远离所述第二引脚的一侧延伸出的第一引出段和自所述第一焊接区的靠近所述第二引脚的一侧延伸出的第二引出段。
在本申请提供的功率半导体器件的封装结构中，所述封装结构适用的封装形式为TO-263，所述第一引出区、所述第一引出段和第二引出段的尺寸分别与标准的TO-263封装结构中的三个管脚的尺寸一致。
在本申请提供的功率半导体器件的封装结构中，所述封装结构还包括直接与所述引线框架连接的第三引脚，所述塑封体完全包覆所述第三引脚。
在本申请提供的功率半导体器件的封装结构中，所述引线框架的与所述塑封体的第一侧相对的一侧设有豁角。
在本申请提供的功率半导体器件的封装结构中，所述第一半导体芯片为三端有源器件，所述第一半导体芯片的正面具有输出端和控制端，所述第一半导体芯片的背面具有输入端；所述输入端与所述引线框架焊接，所述输出端通过键合线电性连接至所述第一引脚的第一焊接区，所述控制端通过键合线电性连接至所述第二引脚的第二焊接区；所述第二半导体芯片为二端有源器件，所述第二半导体芯片的正面具有输出端，所述第一半导体芯片的背面具有输入端；所述输入端与所述引线框架焊接，所述输出端通过键合线电性连接至所述第一引脚的第一焊接区。
在本申请提供的功率半导体器件的封装结构中，所述塑封体由环氧塑封材料制成，所述引线框架由铜合金材质制成，所述键合线由铜线、金线、铝线或合金线制成。
本申请还涉及一种功率模块，其包括基板以及具有如上所述的功率半导体器件的封装结构的功率半导体器件，所述功率半导体器件贴装于所述基板上。
 有益效果
实施本申请的功率半导体器件的封装结构至少可以达到以下功能：所述封装结构包括引线框架、塑封体和第一半导体芯片，所述封装结构还包括第一引脚和第二引脚，所述第一引脚包括相连接的第一焊接区和第一引出区，所述第二引脚包括相连接的第二焊接区和第二引出区；所述第一半导体芯片的背面焊接在所述引线框架上，所述第一半导体芯片的正面通过键合线分别与第一引脚的第一焊接区和所述第二引脚的第二焊接区电性连接；所述第一半导体芯片、所述键合线、所述第一焊接区和所述第二焊接区通过所述塑封体封装于所述引线框架；所述第一引出区和所述第二引出区外露于所述塑封体的第一侧，所述塑封体的第一侧有且仅有所述第一引出区与所述第二引出区伸出。如此，位于所述塑封体同侧的第一引出区和第二引出区之间可以具有足够大的间隔，确保第一引出区和第二引出区之间不会出现击穿短路的现象。从而，所述封装结构可适用于更高电压等级的功率半导体的封装，同时可用表面贴装工艺进行自动贴装。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本申请实施例一提供的封装结构的俯视示意图；
图2为本申请实施例一提供的封装结构的剖视图；
图3为本申请实施例一提供的封装结构的立体结构示意图；
图4为本申请实施例二提供的封装结构的俯视示意图；
图5为本申请实施例二提供的封装结构的剖视图；
图6为本申请实施例二提供的封装结构的立体结构示意图；
图7为本申请实施例三提供的封装结构的俯视示意图；
图8为本申请实施例三提供的封装结构的剖视图；
图9为本申请实施例三提供的封装结构的立体结构示意图。
具体实施方式中的附图标号说明：
引线框架 1 塑封体 2
第一半导体芯片 3 第二半导体芯片 4
第一引脚 6 第二引脚 5
第一焊接区 61 第一引出区 62
第二焊接区 51 第二引出区 52
第三引脚 7 键合线 8
豁角 11 第一引出段 621
第二引出段 622    
本发明的实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的典型实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
实施例一
本实施例提供了一种功率半导体器件的封装结构。参见图1，图1为本申请实施例一提供的封装结构的俯视示意图，图中对塑封体2做了透视处理。如图1所示，所述封装结构包括引线框架1、塑封体2、第一半导体芯片3、第二半导体芯片4、第一引脚6和第二引脚5。所述第一引脚6包括相连接的第一焊接区61和第一引出区62，所述第二引脚5包括相连接的第二焊接区51和第二引出区52。所述第一半导体芯片3的背面焊接在所述引线框架1上，所述第一半导体芯片3的正面通过键合线8分别与第一引脚6的第一焊接区61和所述第二引脚5的第二焊接区51电性连接。在这里，所述第一半导体芯片3为三端有源器件，所述第一半导体芯片3的正面具有输出端和控制端，所述第一半导体芯片3的背面具有输入端；所述输入端与所述引线框架1焊接，所述输出端通过键合线8电性连接至所述第一引脚6的第一焊接区61，所述控制端通过键合线8电性连接至所述第二引脚5的第二焊接区51。所述第二半导体芯片4的背面焊接在所述引线框架1上、正面通过键合线8与所述第一引脚6的第一焊接区61电性连接。在这里，所述第二半导体芯片4为二端有源器件，所述第二半导体芯片4的正面具有输出端，所述第一半导体芯片3的背面具有输入端；所述输入端与所述引线框架1焊接，所述输出端通过键合线8电性连接至所述第一引脚6的第一焊接区61。参见图2，图2为本申请实施例一提供的封装结构的剖视图，如图 2所示，所述第一半导体芯片3、第二半导体芯片4、所述键合线8、所述第一焊接区61和所述第二焊接区51通过所述塑封体2封装于所述引线框架1。参见图3，图3为本申请实施例一提供的封装结构的立体结构示意图，如图3所示，所述第一引出区62和所述第二引出区52则外露于所述塑封体2的第一侧，最重要的是，所述塑封体2的第一侧有且仅有所述第一引出区62与所述第二引出区52伸出。
本实施例中，所述封装结构为TO-263封装形式。
本实施例中，参见图1，所述引线框架1的与所述塑封体2的第一侧相对的一侧设有豁角11。所述塑封体2由环氧塑封材料制成，所述引线框架1由铜合金材质制成，所述键合线8由铜线制成。
综上所示，所述塑封体2的第一侧有且仅有所述第一引出区62与所述第二引出区52伸出，因而所述第一引出区62和所述第二引出区52之间可配置出足够宽的间距，使得所述第一引出区62和所述第二引出区52之间不会出现击穿短路的现象。从而，所述封装结构可适用于更高电压（≤1500V）等级的功率半导体的封装。同时，所述封装结构为TO-263封装形式，因而所述封装结构可用表面贴装工艺进行自动贴装。
在一些其他的实施例中，所述第一半导体芯片3和所述第二半导体芯片4的数量不限于1个，可以是更多个，例如2、3、4个等。
在一些其他的实施例中，所述封装结构也可以不包括所述第二半导体芯片4。
在一些其他的实施例中，所述键合线8由金线、铝线或合金线制成。
实施例二
本实施例提供了一种功率半导体器件的封装结构。本实施例提供的封装结构与实施例一相比，其区别在于，所述第一引脚6的结构有所不同。请参见图4和图5，图4为本申请实施例二提供的封装结构的俯视示意图，图中对塑封体2做了透视处理，图5为本申请实施例二提供的封装结构的剖视图。如图4和图5所示，所述第一焊接区61向所述第二焊接区51的一侧水平延展，使得所述第一焊接区61的宽度大于所述第二焊接区51的宽度。参见图4和图6，图6为本申请实施例二提供的封装结构的立体结构示意图，如图4和图6所示，所述第一引出区62包括自所述第一焊接区61的远离所述第二引脚5的一侧延伸出的第一引出段621和自所述第一焊接区61的靠近所述第二引脚5的一侧延伸出的第二引出段622。在这里，所述第一引出区62、所述第一引出段621和第二引出段622的尺寸分别与标准的TO-263封装结构中的三个管脚的尺寸一致。举例而言，以对IGBT进行封装为例，将采用本实施例的封装结构与采用TO-263封装结构进行比较，那么，本实施例的封装结构中的所述第一引出区62、所述第一引出段621和第二引出段622的尺寸分别与TO-263封装结构中的栅极连接的第一管脚、与集电极连接的第二管脚和与发射极连接的第三管脚的尺寸一致。如此，本实施例的封装结构从外形结构来看可与TO-263封装结构保持一致。另外，功率半导体器件，特别是用背面散热片导电的表面贴装式器件的过电流能力主要由与发射极连接的第三管脚的过电流能力决定的，而第三管脚的过电流能力由第三管脚的宽度和芯片与第三管脚焊接面积决定的。本实施例中，与所述第三管脚对应的第一引脚6的第一焊接区61通过朝向所述第二焊接区51的一侧水平延展而得到了拓宽，使得所述第一焊接区61可键合的金属键合线8的数量和线径得到增大，从而提高了整个封装结构的过电流能力。
实施例三
本实施例提供了一种功率半导体器件的封装结构。本实施例提供的封装结构与实施例一相比，其区别在于，本实施例的封装结构还包括第三引脚7。请参见图7，图7为本申请实施例三提供的封装结构的俯视示意图，图中对塑封体2做了透视处理。如图7所示，所述封装结构还包括第三引脚7，所述第三引脚7设于所述第一引脚6和所述第二引脚5之间。参见图8，图8为本申请实施例三提供的封装结构的剖视图，如图8所示，所述第三引脚7直接与所述引线框架1连接。参见图9，图9为本申请实施例三提供的封装结构的立体结构示意图，所述塑封体2完全包覆所述第三引脚7。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本申请的保护之内。

Claims (11)

  1. 一种功率半导体器件的封装结构，所述封装结构包括引线框架、塑封体和第一半导体芯片，其中，所述封装结构还包括第一引脚和第二引脚，所述第一引脚包括相连接的第一焊接区和第一引出区，所述第二引脚包括相连接的第二焊接区和第二引出区；所述第一半导体芯片的背面焊接在所述引线框架上，所述第一半导体芯片的正面通过键合线分别与所述第一引脚的第一焊接区和所述第二引脚的第二焊接区电性连接；所述第一半导体芯片、所述键合线、所述第一焊接区和所述第二焊接区通过所述塑封体封装于所述引线框架；所述第一引出区和所述第二引出区外露于所述塑封体的第一侧，所述塑封体的第一侧有且仅有所述第一引出区与所述第二引出区伸出。
  2. 根据权利要求1所述的功率半导体器件的封装结构，其中，所述第一半导体芯片的数量为多个。
  3. 根据权利要求1所述的功率半导体器件的封装结构，其中，所述封装结构还包括通过所述塑封体封装于所述引线框架内的第二半导体芯片，所述第二半导体芯片的背面焊接在所述引线框架上、正面通过键合线与所述第一引脚的第一焊接区电性连接。
  4. 根据权利要求3所述的功率半导体器件的封装结构，其中，所述第二半导体芯片的数量为多个。
  5. 根据权利要求3所述的功率半导体器件的封装结构，其中，所述第一半导体芯片为三端有源器件，所述第一半导体芯片的正面具有输出端和控制端，所述第一半导体芯片的背面具有输入端；所述输入端与所述引线框架焊接，所述输出端通过键合线电性连接至所述第一引脚的第一焊接区，所述控制端通过键合线电性连接至所述第二引脚的第二焊接区；所述第二半导体芯片为二端有源器件，所述第二半导体芯片的正面具有输出端，所述第一半导体芯片的背面具有输入端；所述输入端与所述引线框架焊接，所述输出端通过键合线电性连接至所述第一引脚的第一焊接区。
  6. 根据权利要求1所述的功率半导体器件的封装结构，其中，所述第一焊接区的宽度大于所述第二焊接区的宽度，所述第一引出区包括自所述第一焊接区的远离所述第二引脚的一侧延伸出的第一引出段和自所述第一焊接区的靠近所述第二引脚的一侧延伸出的第二引出段。
  7. 根据权利要求6所述的功率半导体器件的封装结构，其中，所述封装结构适用的封装形式为TO-263，所述第一引出区、所述第一引出段和第二引出段的尺寸分别与标准的TO-263封装结构中的三个管脚的尺寸一致。
  8. 根据权利要求1所述的功率半导体器件的封装结构，其中，所述封装结构还包括直接与所述引线框架连接的第三引脚，所述塑封体完全包覆所述第三引脚。
  9. 根据权利要求1所述的功率半导体器件的封装结构，其中，所述引线框架的与所述塑封体的第一侧相对的一侧设有豁角。
  10. 根据权利要求1所述的功率半导体器件的封装结构，其中，所述塑封体由环氧塑封材料制成，所述引线框架由铜合金材质制成，所述键合线由铜线、金线、铝线或合金线制成。
  11. 一种功率模块，包括基板以及具有根据权利要求1-10中任一项所述的功率半导体器件的封装结构的功率半导体器件，所述功率半导体器件贴装于所述基板上。
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