CN105428343A - 一种多芯片单搭堆叠夹芯封装结构及其工艺方法 - Google Patents
一种多芯片单搭堆叠夹芯封装结构及其工艺方法 Download PDFInfo
- Publication number
- CN105428343A CN105428343A CN201510988904.4A CN201510988904A CN105428343A CN 105428343 A CN105428343 A CN 105428343A CN 201510988904 A CN201510988904 A CN 201510988904A CN 105428343 A CN105428343 A CN 105428343A
- Authority
- CN
- China
- Prior art keywords
- lead frame
- chip
- horizontal segment
- frame
- encapsulating structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/074—Stacked arrangements of non-apertured devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L21/603—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/37124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/38—Structure, shape, material or disposition of the strap connectors prior to the connecting process of a plurality of strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
本发明涉及一种多芯片单搭堆叠夹芯封装结构及其工艺方法,所述方法包括以下步骤:步骤一、提供第一引线框;步骤二、在第一引线框上涂覆锡膏;步骤三、在第一引线框锡膏上植入第一芯片;步骤四、提供第二引线框,在第二引线框上涂覆锡膏;步骤五、将第二引线框压合在第一芯片上;步骤六、进行回流焊;步骤七、在第二引线框上涂覆锡膏;步骤八、在第二引线框上植入第二芯片;步骤九、提供第三引线框,在第三引线框上涂覆锡膏;步骤十、将第三引线框压合在第二芯片上;步骤十一、进行回流焊;步骤十二、塑封料塑封;步骤十三、切割或冲切作业。本发明的有益效果是:增加产品热消散的能力,降低产品的封装电阻。且整条产品可一体成型,生产效率高。
Description
技术领域
本发明涉及一种多芯片单搭堆叠夹芯封装结构及其工艺方法,属于半导体封装技术领域。
背景技术
近年来,随着电子产品对功率密度不断的追求,无论是Diode(二级管)还是Transistor(三极管)的封装,尤其是Transistor中的MOS产品正朝着更大功率、更小尺寸、更快速、散热更好的趋势在发展。封装的一次性制造方式也由单颗封装技术慢慢朝向小区域甚至更大区域的高密度高难度低成本一次性封装技术冲刺与挑战。
因此,也对MOS产品的封装在寄生的电阻、电容、电感等的各种电性能、封装的结构、封装的热消散性能力、封装的信赖性方面以及高难度一次性封装技术方面有了更多的要求。
传统的Diode(二级管)以及Transistor(三极管)或是MOS产品的封装一般依据产品特性、功率的不同以及成本的考虑因素,利用了金线、银合金线、铜线、铝线以及铝带的焊线方式作为芯片与内引脚的主要的互联技术,从而实现电气连接。然而焊线的技术方式对产品的性能存在了以下几个方面的限制与缺陷:
一、封装与制造方面的限制与缺陷:
1)、焊接能力(Bondability)方面:常常会因为金属丝材料、金属引脚材料的变化以及设备与工具的参数片变化、性能与精度的变化以及保养与校正管理而造成的第一焊点以及第二焊点结合面的虚焊、脱落、断点、颈部裂缝、塌线以及短路等种种的困扰,导致了封装良率无法提升、成本无法下降、可靠性的不稳定;
2)、一次性高密度封装技术方面:传统的互联方式几乎都是在矩阵型金属引线框上采用单颗芯片一颗一颗芯片重复进行装片、金属丝采高温超声一根线一根线的焊接方式。而这样情况下无论是专业的装片机、球焊打线机、键合铝线/铝带机或是铜片搭接机等机器设备再高速的重复动作都无法提升生产效率、无法降低单位成本,也因为设备不断的提升生产速度同样的也提升了制造的不稳定性。
二、封装产品的特性能方面的限制与缺陷:
1)、热消散方面:传统的Diode(二级管)以及Transistor(三极管)或是MOS的封装产品,一般都是由塑封料包覆、只留外部引脚暴露在塑封体之外,由于塑封料本身不是一种热导的物质,所以传统的Diode(二级管)以及Transistor(三极管)或是MOS产品在工作时所产生的热量很难通过塑封料消散出塑封料物质的封装体,只能依靠细细的金属丝互联在金属引脚材料来帮助热能的消散,但是这种热消散的途径对热的消散能力是非常有限的,反而形成热消散的阻力;
2)、电阻率(Resistivity)方面:大家都知道电阻率(resistivity)是用来表示各种物质电阻特性的物理量。在温度一定的情况下,有公式R=ρl/s其中的ρ就是电阻率,l为材料的长度,s为面积。可以看出,材料的电阻大小正比于材料的长度,而反比于其面积。由上式可知电阻率的定义:ρ=Rs/l。传统的Diode(二级管)以及Transistor(三极管)或是MOS的封装产品,采用焊线形成互联,由此可清楚的知道用来执行电源或是信号的金属丝会因为,导体材料的长度与截面积的变化而影响到电阻率的大小以及接触电阻的损耗,尤其是应用在功率方面的产品影响更是明显。
为解决上述问题,业界对传统的Diode(二级管)以及Transistor(三极管)或是MOS的封装产品进行了改进,用金属带、金属夹板代替焊线,来降低封装电阻、电感与期望改善热消散的能力。
如图1所示,为一种现有的MOS堆叠封装结构,此结构中引线框11包含管芯焊盘和引脚,在引线框11的管芯焊盘上植入第一芯片12。第一芯片12的源极通过第一金属夹板14电耦合至引脚,第一芯片12的栅极通过第一金属焊线16电耦合至引脚。然后在第一金属夹板14上植入第二芯片13,第二芯片13的源极通过第二金属夹板15电耦合至引脚,第二芯片13的栅极通过第二金属焊线17电耦合至引脚。再进行包封、切割、测试等后续工序。此MOS封装结构用金属夹板取代了传统MOS封装中的焊线,降低了部分封装电阻,但是还是存在以下缺陷:首先,此MOS封装结构中芯片的漏极、源极和栅极与引线框形成互联分别要用到不同的设备,制程复杂,设备的购置成本较高;其次,此MOS封装结构在把金属夹板和金属焊线耦合至芯片和引脚上时,只能一颗颗芯片进行,无法整条一体成型,制造效率较低。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种多芯片单搭堆叠夹芯封装结构及其工艺方法,整条产品可一体成型,生产效率高,工艺简单,可降低成本,并且具有较好的散热性和较低的封装电阻和电感。
本发明解决上述问题所采用的技术方案为:一种多芯片单搭堆叠夹芯封装结构,它包括第一引线框、第二引线框、第三引线框、第一芯片和第二芯片,所述第二引线框和第三引线框呈Z形,所述Z形的第二引线框包括第一上水平段、第一中间连接段和第一下水平段,所述Z形的第三引线框包括第二上水平段、第二中间连接段和第二下水平段,所述第一芯片夹设在第一引线框与第一上水平段之间,所述第一芯片的正面和背面分别通过锡膏与第一上水平段和第一引线框电性连接,所述第二芯片夹设在第一上水平段与第二上水平段之间,所述第二芯片的正面和背面分别通过锡膏与第二上水平段和第一上水平段电性连接,所述第一引线框、第二引线框和第三引线框外包封有塑封料,所述第一引线框下表面和第一下水平段下表面齐平且均暴露于塑封料之外,所述第二下水平段下表面搭设在第一引线框上表面上。
所述第一引线框、第二引线框和第三引线框均为整体框架。
一种多芯片单搭堆叠夹芯封装结构的工艺方法,所述方法包括如下步骤:
步骤一、提供第一引线框;
步骤二、在第一引线框基岛区域通过网板印刷的方式涂覆锡膏;
步骤三、在步骤二中第一引线框基岛区域涂覆的锡膏上植入第一芯片;
步骤四、提供第二引线框,所述第二引线框为Z形,所述Z形的第二引线框包括第一上水平段、第一中间连接段和第一下水平段,在第二引线框的第一上水平段的下表面通过网板印刷的方式涂覆锡膏;
步骤五、将第二引线框的第一上水平段压合在第一引线框上表面的第一芯片上,压合后第一引线框和第二引线框形成整体框架,第一引线框下表面与第二引线框第一下水平段下表面齐平;
步骤六、将步骤五形成的整体框架上下表面用压板压住,进行回流焊;
步骤七、完成回流焊后,在第二引线框的第一上水平段的上表面通过网板印刷的方式涂覆锡膏;
步骤八、在步骤七中第二引线框的第一上水平段上表面涂覆的锡膏上植入第二芯片;
步骤九、提供第三引线框,所述第三引线框为Z形,所述Z形的第三引线框包括第二上水平段、第二中间连接段和第二下水平段,在第三引线框的第二上水平段下表面和第二下水平段下表面通过网板印刷的方式涂覆锡膏;
步骤十、将第三引线框的第二上水平段压合在第二引线框的第一上水平段上表面的第二芯片上,且第三引线框的第二下水平段下表面搭设在第一引线框上表面上,压合后第一引线框、第二引线框和第三引线框形成整体框架;
步骤十一、将步骤十形成的整体框架上下表面用压板压住,进行回流焊;
步骤十二、将步骤十一经过回流焊后的整体框架采用塑封料进行塑封;
步骤十三、将步骤十二完成塑封的半成品进行切割或是冲切作业,使原本阵列式塑封体,切割或是冲切独立开来,制得多芯片单搭堆叠夹芯封装结构。
所述第一引线框压合第二引线框形成整体框架,可以在第二引线框植入第二芯片后进行实施。
所述第一引线框、第二引线框和第三引线框的材质可以为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材,也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质。
所述第一芯片和第二芯片为可以与金属锡结合的二极芯片、三极芯片或多极芯片。
所述压板材质的热膨胀系数CTE与第一引线框、第二引线框和第三引线框材质的热膨胀系数CTE接近,其CTE范围是8*10^-6/℃~25*10^-6/℃。
所述步骤二、步骤四和步骤九可通过不同机台同时进行。
与现有技术相比,本发明的优点在于:
1、本发明一种多芯片单搭堆叠夹芯封装结构的第二引线框与第三引线框直接与MOS芯片的源极和栅极形成电性连接,取代了传统MOS芯片封装中利用金属焊线形成互联的工艺,充分减少了封装电阻,本发明的技术可以比传统封装设计的封装电阻降低至少30%以上;
2、本发明一种多芯片单搭堆叠夹芯封装结构的第二引线框与第三引线框直接通过锡膏与MOS芯片的源极和栅极形成电性连接,完全减免了金属焊线的互联工序,完全节省了金属焊线互联工序的设备购置、工序材料等成本。且本发明的第二引线框和第三引线框都为整条一体成型的,与芯片形成电性连接也是整条一步完成,与传统金属焊线、金属片互联一个个芯片形成互联的工艺相比,工艺较为简单,生产效率有了明显的提高;
3、本发明的一种多芯片单搭堆叠夹芯封装结构由于芯片上下两个表面都直接与引线框相接触,芯片工作时产生的热量可通过引线框散出,且本发明的第一引线框下表面直接暴露在塑封料之外,本发明的多芯片单搭堆叠夹芯封装结构具有较好的散热性能;而且本发明可再依据产品功率、导热或是散热的不同自由的在引线框上外加散热器,用以进一步增加产品热消散的能力;
4、本发明的一种多芯片单搭堆叠夹芯封装结构使用上下压板压住整体框架进行回流焊,使得框架在回流焊时不易被锡膏受热熔解后的冷却过程的凝聚所顶起,保证框架结构的总高度,防止芯片的移动或旋转,并且能确保框架暴露外脚的共面性。
附图说明
图1为一种已知的MOS堆叠封装结构示意图。
图2为本发明制造的一种多芯片单搭堆叠夹芯封装结构的侧面图。
图3为本发明制造的一种多芯片单搭堆叠夹芯封装结构的俯视图。
图4为本发明中第一引线框的立体视图。
图5为本发明中第二引线框的立体视图。
图6为本发明中第三引线框的立体视图。
图7(a)至图7(m)为本发明一种多芯片单搭堆叠夹芯封装结构工艺方法的流程图。
其中:
引线框11
第一芯片12
第二芯片13
第一金属夹板14
第二金属夹板15
第一金属焊线16
第二金属焊线17
第一引线框21
第二引线框22
第一上水平段221
第一中间连接段222
第一下水平段223
第三引线框23
第二上水平段231
第二中间连接段232
第二下水平段233
第一芯片24
第二芯片25
锡膏26
塑封料27。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
如图7(a)~图7(m)所示,本实施例中的一种多芯片单搭堆叠夹芯封装结构的工艺方法,其具体工艺步骤如下:
步骤一、参见图7(a),提供第一引线框,第一引线框的材质为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材,也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质;
步骤二、参见图7(b),在第一引线框基岛区域通过网板印刷的方式涂覆锡膏,目的是为实现后续第一芯片植入后与基岛接合,通过调整网板的厚度和开口的面积可以精确的控制锡膏的厚度、面积以及位置;
步骤三、参见图7(c),在步骤二中第一引线框基岛区域涂覆的锡膏上植入第一芯片;
步骤四、参见图7(d),提供第二引线框,所述第二引线框为Z形,所述Z形的第二引线框包括第一上水平段、第一中间连接段和第一下水平段,第二引线框的材质为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材,也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质。在第二引线框的第一上水平段的下表面通过网板印刷的方式涂覆锡膏,通过调整网板的厚度和开口的面积可以精确的控制锡膏的厚度、面积以及位置;
步骤五、参见图7(e),将第二引线框的第一上水平段压合在第一引线框上表面的第一芯片上,使第一芯片与第二引线框通过第一上水平段下表面的锡膏形成电性连接,压合后第一引线框和第二引线框形成整体框架,第一引线框下表面与第二引线框第一下水平段下表面齐平;
步骤六、参见图7(f),将步骤五形成的整体框架上下表面用压板压住,进行回流焊。压板的材质要求不容易发生形变且具有良好的热传导性能,其热膨胀系数CTE与第一引线框和第二引线框材质的热膨胀系数CTE接近,其CTE范围是8*10^-6/℃~25*10^-6/℃;
步骤七、参见图7(g),完成回流焊后,在第二引线框的第一上水平段的上表面通过网板印刷的方式涂覆锡膏;
步骤八、参见图7(h),在步骤七中第二引线框的第一上水平段上表面涂覆的锡膏上植入第二芯片;
步骤九、参见图7(i),提供第三引线框,所述第三引线框为Z形,所述Z形的第三引线框包括第二上水平段、第二中间连接段和第二下水平段,第三引线框的材质为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材,也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质。在第三引线框的第二上水平段下表面和第二下水平段下表面通过网板印刷的方式涂覆锡膏,目的是为实现后续第三引线框第二上水平段与第二芯片正面之间以及第三引线框第二下水平段与第一引线框上表面之间形成电性连接,通过调整网板的厚度和开口的面积可以精确的控制锡膏的厚度、面积以及位置;
步骤十、参见图7(j),将第三引线框的第二上水平段压合在第二引线框的第一上水平段上表面的第二芯片上,使第二芯片与第三引线框通过第二上水平段下表面的锡膏形成电性连接,且第三引线框的第二下水平段下表面搭设在第一引线框上表面上,压合后第一引线框、第二引线框和第三引线框形成整体框架;
步骤十一、参见图7(k),将步骤十形成的整体框架上下表面用压板压住,进行回流焊。压板的材质要求不容易发生形变且具有良好的热传导性能,其热膨胀系数CTE与第一引线框、第二引线框和第三引线框材质的热膨胀系数CTE接近,其CTE范围是8*10^-6/℃~25*10^-6/℃;
步骤十二、参见图7(l),将步骤十一经过回流焊后的整体框架采用塑封料进行塑封;
步骤十三、参见图7(m),将步骤十二完成塑封的半成品进行切割或是冲切作业,使原本阵列式塑封体,切割或是冲切独立开来,制得多芯片单搭堆叠夹芯封装结构。
上述步骤中,步骤五与步骤六第一引线框压合第二引线框形成整体框架并使用压板进行回流焊,可以在步骤八第二引线框植入第二芯片后进行实施。
上述步骤中,步骤二、步骤四和步骤九可通过不同机台同时进行。
参见图2~图6,本发明一种多芯片单搭堆叠夹芯封装结构,它包括第一引线框21、第二引线框22、第三引线框23、第一芯片24和第二芯片25,所述第二引线框22和第三引线框23呈Z形,所述Z形的第二引线框22包括第一上水平段221、第一中间连接段222和第一下水平段223,所述Z形的第三引线框23包括第二上水平段231、第二中间连接段232和第二下水平段233,所述第一芯片24夹设在第一引线框21与第一上水平段221之间,所述第一芯片24的正面和背面分别通过锡膏26与第一上水平段221和第一引线框21电性连接,所述第二芯片25夹设在第一上水平段221与第二上水平段231之间,所述第二芯片25的正面和背面分别通过锡膏26与第二上水平段231和第一上水平段221电性连接,所述第一引线框21、第二引线框22和第三引线框23外包封有塑封料27,所述第一引线框21下表面和第一下水平段223下表面齐平且均暴露于塑封料27之外,所述第二下水平段233下表面搭设在第一引线框21上表面上。
所述第一引线框21、第二引线框22和第三引线框23均为整体框架,其材质可以为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材,也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质。
所述第一芯片24和第二芯片25为可以与金属锡结合的二极芯片、三极芯片或多极芯片。
除上述实施例外,本发明还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本发明权利要求的保护范围之内。
Claims (8)
1.一种多芯片单搭堆叠夹芯封装结构,其特征在于:它包括第一引线框(21)、第二引线框(22)、第三引线框(23)、第一芯片(24)和第二芯片(25),所述第二引线框(22)和第三引线框(23)呈Z形,所述Z形的第二引线框(22)包括第一上水平段(221)、第一中间连接段(222)和第一下水平段(223),所述Z形的第三引线框(23)包括第二上水平段(231)、第二中间连接段(232)和第二下水平段(233),所述第一芯片(24)夹设在第一引线框(21)与第一上水平段(221)之间,所述第一芯片(24)的正面和背面分别通过锡膏(26)与第一上水平段(221)和第一引线框(21)电性连接,所述第二芯片(25)夹设在第一上水平段(221)与第二上水平段(231)之间,所述第二芯片(25)的正面和背面分别通过锡膏(26)与第二上水平段(231)和第一上水平段(221)电性连接,所述第一引线框(21)、第二引线框(22)和第三引线框(23)外包封有塑封料(27),所述第一引线框(21)下表面和第一下水平段(223)下表面齐平且均暴露于塑封料(27)之外,所述第二下水平段(233)下表面搭设在第一引线框(21)上表面上。
2.根据权利要求1所述的一种多芯片单搭堆叠夹芯封装结构,其特征在于:所述第一引线框(21)、第二引线框(22)和第三引线框(23)均为整体框架。
3.一种多芯片单搭堆叠夹芯封装结构的工艺方法,其特征在于所述方法包括如下步骤:
步骤一、提供第一引线框;
步骤二、在第一引线框基岛区域通过网板印刷的方式涂覆锡膏;
步骤三、在步骤二中第一引线框基岛区域涂覆的锡膏上植入第一芯片;
步骤四、提供第二引线框,所述第二引线框为Z形,所述Z形的第二引线框包括第一上水平段、第一中间连接段和第一下水平段,在第二引线框的第一上水平段的下表面通过网板印刷的方式涂覆锡膏;
步骤五、将第二引线框的第一上水平段压合在第一引线框上表面的第一芯片上,压合后第一引线框和第二引线框形成整体框架,第一引线框下表面与第二引线框第一下水平段下表面齐平;
步骤六、将步骤五形成的整体框架上下表面用压板压住,进行回流焊;
步骤七、完成回流焊后,在第二引线框的第一上水平段的上表面通过网板印刷的方式涂覆锡膏;
步骤八、在步骤七中第二引线框的第一上水平段上表面涂覆的锡膏上植入第二芯片;
步骤九、提供第三引线框,所述第三引线框为Z形,所述Z形的第三引线框包括第二上水平段、第二中间连接段和第二下水平段,在第三引线框的第二上水平段下表面和第二下水平段下表面通过网板印刷的方式涂覆锡膏;
步骤十、将第三引线框的第二上水平段压合在第二引线框的第一上水平段上表面的第二芯片上,且第三引线框的第二下水平段下表面搭设在第一引线框上表面上,压合后第一引线框、第二引线框和第三引线框形成整体框架;
步骤十一、将步骤十形成的整体框架上下表面用压板压住,进行回流焊;
步骤十二、将步骤十一经过回流焊后的整体框架采用塑封料进行塑封;
步骤十三、将步骤十二完成塑封的半成品进行切割或是冲切作业,使原本阵列式塑封体,切割或是冲切独立开来,制得多芯片单搭堆叠夹芯封装结构。
4.根据权利要求3所述的一种多芯片单搭堆叠夹芯封装结构的工艺方法,其特征在于:所述第一引线框、第二引线框和第三引线框的材质可以为合金铜材、纯铜材、铝镀铜材、锌镀铜材、镍铁合金材,也可以为其它CTE范围是8*10^-6/℃~25*10^-6/℃的导电材质。
5.根据权利要求3所述的一种多芯片单搭堆叠夹芯封装结构的工艺方法,其特征在于:所述第一芯片和第二芯片为可以与金属锡结合的二极芯片、三极芯片或多极芯片。
6.根据权利要求3所述的一种多芯片单搭堆叠夹芯封装结构的工艺方法,其特征在于:所述压板材质的热膨胀系数CTE与第一引线框、第二引线框和第三引线框材质的热膨胀系数CTE接近,其CTE范围是8*10^-6/℃~25*10^-6/℃。
7.根据权利要求3所述的一种多芯片单搭堆叠夹芯封装结构的工艺方法,其特征在于:所述步骤二、步骤四和步骤九可通过不同机台同时进行。
8.根据权利要求3所述的一种多芯片单搭堆叠夹芯封装结构的工艺方法,其特征在于:步骤五与步骤六第一引线框压合第二引线框形成整体框架并使用压板进行回流焊,可以在步骤八第二引线框植入第二芯片后进行实施。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510988904.4A CN105428343A (zh) | 2015-12-24 | 2015-12-24 | 一种多芯片单搭堆叠夹芯封装结构及其工艺方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510988904.4A CN105428343A (zh) | 2015-12-24 | 2015-12-24 | 一种多芯片单搭堆叠夹芯封装结构及其工艺方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN105428343A true CN105428343A (zh) | 2016-03-23 |
Family
ID=55506432
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510988904.4A Pending CN105428343A (zh) | 2015-12-24 | 2015-12-24 | 一种多芯片单搭堆叠夹芯封装结构及其工艺方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105428343A (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106229307A (zh) * | 2016-08-01 | 2016-12-14 | 长电科技(宿迁)有限公司 | 铝线焊点表面二次装片的焊接结构及其工艺方法 |
CN113257797A (zh) * | 2021-06-25 | 2021-08-13 | 瑞能半导体科技股份有限公司 | 一种共阳极二极管器件及其制备方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101515551A (zh) * | 2008-02-22 | 2009-08-26 | 株式会社瑞萨科技 | 半导体器件的制备方法 |
CN101859755A (zh) * | 2010-05-14 | 2010-10-13 | 上海凯虹科技电子有限公司 | 一种功率mosfet封装体及其封装方法 |
CN102903692A (zh) * | 2011-07-26 | 2013-01-30 | 万国半导体股份有限公司 | 应用双层引线框架的堆叠式功率半导体器件及其制备方法 |
-
2015
- 2015-12-24 CN CN201510988904.4A patent/CN105428343A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101515551A (zh) * | 2008-02-22 | 2009-08-26 | 株式会社瑞萨科技 | 半导体器件的制备方法 |
CN101859755A (zh) * | 2010-05-14 | 2010-10-13 | 上海凯虹科技电子有限公司 | 一种功率mosfet封装体及其封装方法 |
CN102903692A (zh) * | 2011-07-26 | 2013-01-30 | 万国半导体股份有限公司 | 应用双层引线框架的堆叠式功率半导体器件及其制备方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106229307A (zh) * | 2016-08-01 | 2016-12-14 | 长电科技(宿迁)有限公司 | 铝线焊点表面二次装片的焊接结构及其工艺方法 |
CN106229307B (zh) * | 2016-08-01 | 2019-05-17 | 长电科技(宿迁)有限公司 | 铝线焊点表面二次装片的焊接结构及其工艺方法 |
CN113257797A (zh) * | 2021-06-25 | 2021-08-13 | 瑞能半导体科技股份有限公司 | 一种共阳极二极管器件及其制备方法 |
CN113257797B (zh) * | 2021-06-25 | 2022-04-22 | 瑞能半导体科技股份有限公司 | 一种共阳极二极管器件及其制备方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10153230B2 (en) | Method of manufacturing a semiconductor device comprising a semiconductor chip mounted over a metal plate having an inclined surface | |
CN206116387U (zh) | 一种大电流功率半导体器件的封装结构 | |
CN107680951A (zh) | 一种多芯片叠层的封装结构及其封装方法 | |
CN105405834A (zh) | 一种框架外露多芯片多搭堆叠夹芯封装结构及其工艺方法 | |
CN105551982A (zh) | 一种多芯片正装平铺夹芯封装结构及其工艺方法 | |
CN105448881A (zh) | 一种框架外露多芯片多搭平铺夹芯封装结构及其工艺方法 | |
CN105428343A (zh) | 一种多芯片单搭堆叠夹芯封装结构及其工艺方法 | |
CN105609424A (zh) | 一种框架外露的夹芯封装工艺方法 | |
CN205582931U (zh) | 部分框架外露多芯片单搭倒装平铺夹芯封装结构 | |
CN105633051A (zh) | 部分框架外露多芯片多搭平铺夹芯封装结构及其工艺方法 | |
CN205582923U (zh) | 一种框架外露多芯片多搭倒装堆叠夹芯封装结构 | |
CN105489508A (zh) | 一种防止芯片偏移的夹芯封装工艺方法 | |
CN205355046U (zh) | 一种框架外露多芯片多搭混装平铺夹芯封装结构 | |
CN205355045U (zh) | 一种框架外露多芯片混装堆叠夹芯封装结构 | |
CN205582917U (zh) | 一种框架外露多芯片多搭倒装平铺夹芯封装结构 | |
CN105551983A (zh) | 一种框架外露多芯片正装堆叠夹芯封装结构及其工艺方法 | |
CN205582928U (zh) | 一种多芯片多搭倒装平铺夹芯封装结构 | |
CN105405833A (zh) | 一种多芯片多搭平铺夹芯封装结构及其工艺方法 | |
CN105609425A (zh) | 部分框架外露多芯片单搭平铺夹芯封装结构及其工艺方法 | |
CN105405831A (zh) | 一种框架外露多芯片正装平铺夹芯封装结构及其工艺方法 | |
CN105633050A (zh) | 一种多芯片多搭堆叠夹芯封装结构及其工艺方法 | |
CN205355032U (zh) | 一种框架外露多芯片单搭倒装堆叠夹芯封装结构 | |
CN205355044U (zh) | 一种框架外露多芯片多搭混装堆叠夹芯封装结构 | |
CN205582929U (zh) | 一种多芯片单搭倒装堆叠夹芯封装结构 | |
CN205376509U (zh) | 一种多芯片多搭倒装堆叠夹芯封装结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160323 |
|
RJ01 | Rejection of invention patent application after publication |