JP5903637B2 - 導電路の製造方法及び半導体装置の製造方法 - Google Patents
導電路の製造方法及び半導体装置の製造方法 Download PDFInfo
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- JP5903637B2 JP5903637B2 JP2012517021A JP2012517021A JP5903637B2 JP 5903637 B2 JP5903637 B2 JP 5903637B2 JP 2012517021 A JP2012517021 A JP 2012517021A JP 2012517021 A JP2012517021 A JP 2012517021A JP 5903637 B2 JP5903637 B2 JP 5903637B2
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- Prior art keywords
- conductive path
- forming plate
- path forming
- hole
- press
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- Expired - Fee Related
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- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 238000000034 method Methods 0.000 title claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 29
- 238000007747 plating Methods 0.000 claims description 27
- 239000010949 copper Substances 0.000 claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 239000004033 plastic Substances 0.000 description 7
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- 238000007796 conventional method Methods 0.000 description 2
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- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 2
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- 238000001878 scanning electron micrograph Methods 0.000 description 2
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- 229920001187 thermosetting polymer Polymers 0.000 description 1
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B21—MECHANICAL METAL-WORKING WITHOUT ESSENTIALLY REMOVING MATERIAL; PUNCHING METAL
- B21D—WORKING OR PROCESSING OF SHEET METAL OR METAL TUBES, RODS OR PROFILES WITHOUT ESSENTIALLY REMOVING MATERIAL; PUNCHING METAL
- B21D39/00—Application of procedures in order to connect objects or parts, e.g. coating with sheet metal otherwise than by plating; Tube expanders
- B21D39/03—Application of procedures in order to connect objects or parts, e.g. coating with sheet metal otherwise than by plating; Tube expanders of sheet metal otherwise than by folding
- B21D39/031—Joining superposed plates by locally deforming without slitting or piercing
- B21D39/032—Joining superposed plates by locally deforming without slitting or piercing by fitting a projecting part integral with one plate in a hole of the other plate
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- Condensed Matter Physics & Semiconductors (AREA)
- Mechanical Engineering (AREA)
- Geometry (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
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Description
本発明の一実施形態に係る樹脂封止型半導体装置及びそれを構成する導電路について図面を参照しながら説明する。
図1は一実施形態に係る樹脂封止型半導体装置の断面構成を示している。
図2は図1に示した接合部25を含む領域30を拡大した断面構成を表している。
以下、一実施形態に係る導電路の製造方法について図5(a)〜図5(d)を参照しながら説明する。
T2 制御素子
1 第1リードフレーム
1b 第1中継リード
1c 第1ダイパッド部
2 第2リードフレーム
2b 第2中継リード
2c 第2ダイパッド部
3 放熱板
4 外装体
5 絶縁性シート
6 ろう材
7 ワイヤ
8 ワイヤ
9 銀ペースト材
10 ワイヤ
11 第1導電路形成板
12 第1接続部
13 貫通孔
14 第2接続部
15 第2導電路形成板
16 めっき膜
16a 結晶粒
17 圧入部
17a 傾斜圧入面
17b 圧入痕
18 傾斜接合面
19 ポンチ
20 先端部
21 押圧面
25 接合部
30,31 領域
Claims (8)
- 第1金属から構成され、穴部を有する第1導電路形成板と、第2金属から構成された第2導電路形成板とを互いに重ね合わせた状態で、
前記第2導電路形成板において前記穴部と対向する部分を圧入工具により突出させると同時に、当該突出させた部分で前記穴部の開口を拡げつつ前記突出させた部分を前記穴部に圧入することで、
前記開口を拡げつつ前記穴部に圧入する際に形成される前記突出させた部分の新生面と前記穴部の新生面とを一体化することにより、前記第1導電路形成板と前記第2導電路形成板とを互いに接合させるに際し、
前記圧入工具の先端部の側面は、前記第2導電路形成板の上面の法線に対して、30°以上且つ60°以下の角度であり、
前記先端部の直径は、前記穴部の開口径の最小値の2分の1である導電路の製造方法。 - 請求項1において、
前記第2導電路形成板において前記穴部と対抗する部分を圧入工具により前記穴部に圧入することで、前記第1導電路形成板と前記第2導電路形成板とを擦り合わせ、前記第1導電路形成板と前記第2導電路形成板とを互いに接合させる導電路の製造方法。 - 請求項1又は2において、
前記第1導電路形成板に重ね合わされた前記第2導電路形成板に、硬度が前記第1金属及び第2金属の硬度よりも高い第3金属から構成された厚さ0.01μm以上且つ10μm以下のめっき膜が形成された導電路の製造方法。 - 請求項3において、
前記第1金属及び前記第2金属は、銅であり、
前記第3金属は、ニッケルである導電路の製造方法。 - 第1金属から構成され、穴部を有する第1導電路形成板、及び第2金属から構成され、第2導電路形成板の少なくとも一方の上に予め半導体チップを固着しておき、
前記第1導電路形成板において前記穴部を有する領域と前記第2導電路形成板の一部とを互いに重ね合わせた状態で、
前記第2導電路形成板において前記穴部と対向する部分を圧入工具により突出させると同時に、当該突出させた部分で前記穴部の開口を拡げつつ前記突出させた部分を前記穴部に圧入することで、
前記開口を拡げつつ前記穴部に圧入する際に形成される前記突出させた部分の新生面と前記穴部の新生面とを一体化することにより、前記第1導電路形成板と前記第2導電路形成板とを互いに接合させた後、
前記半導体チップと、前記第1導電路形成板及び前記第2導電路形成板の接合部とを樹脂材から構成された外装体により封止するに際し、
前記圧入工具の先端部の側面は、前記第2導電路形成板の上面の法線に対して、30°以上且つ60°以下の角度であり、
前記先端部の直径は、前記穴部の開口径の最小値の2分の1である半導体装置の製造方法。 - 請求項5において、
前記第2導電路形成板において前記穴部と対抗する部分を圧入工具により前記穴部に圧入することで、前記第1導電路形成板と前記第2導電路形成板とを擦り合わせ、前記第1導電路形成板と前記第2導電路形成板とを互いに接合させる半導体装置の製造方法。 - 請求項5又は6において、
前記第1導電路形成板に重ね合わされた前記第2導電路形成板に、硬度が前記第1金属及び第2金属の硬度よりも高い第3金属から構成された厚さ0.01μm以上且つ10μm以下のめっき膜が形成された半導体装置の製造方法。 - 請求項7において、
前記第1金属及び前記第2金属は、銅であり、
前記第3金属は、ニッケルである半導体装置の製造方法。
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US9470860B2 (en) * | 2015-02-12 | 2016-10-18 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Methods and systems for improving heat dissipation, signal integrity and electromagnetic interference (EMI) shielding in optical communications modules |
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