CN105336631B - 使用两个引线框架组装的半导体装置 - Google Patents

使用两个引线框架组装的半导体装置 Download PDF

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CN105336631B
CN105336631B CN201410357286.9A CN201410357286A CN105336631B CN 105336631 B CN105336631 B CN 105336631B CN 201410357286 A CN201410357286 A CN 201410357286A CN 105336631 B CN105336631 B CN 105336631B
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lead
lead frame
array
semiconductor device
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CN105336631A (zh
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王欢
刘赫津
孙维萍
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NXP USA Inc
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Abstract

使用其上安装和包封有片芯的第一引线框架和为装置提供弯曲引线的第二引线框架来装配封装的半导体装置。通过使用两个不同的引线框架,与相当尺寸的现有技术的引线框架阵列相比,第一引线框架的阵列可以被构造有用于更多装置的更多引线框架,因为第一引线框架阵列不需要为封装的装置提供引线。代之以,由第二引线框架阵列提供引线,可以在已将片芯安装和封装在第一引线框架阵列之后将第二引线框架阵列附接到第一引线框架阵列。

Description

使用两个引线框架组装的半导体装置
技术领域
本发明总的来说涉及半导体装置,以及更特别地,涉及使用两个引线框架组装的半导体装置。
背景技术
四方扁平封装(QFP)半导体装置是具有从半导体装置延伸的弯曲的“鸥翼”引线的半导体装置。该弯曲引线使得这种类型的装置易于焊接。制造带有弯曲引线的标准的QFP半导体装置的组装在附图1A-1F中示出,将在下面更详细说明。
附图1A示出了片芯104接合到具有引线110的引线框架102。片芯104也用接合线106电连接到引线框架102。附图1B示出了被包封在模制料108内的片芯104、接合线106、以及引线框架102的一部分,引线110延伸到模制料108的外面。
在被称为引线框架阵列的引线框架的一维或二维的组件上一起制造多个半导体装置。附图1C是具有被包封的片芯104的引线框架阵列120的简化俯视图。附图1C意图指示出在引线框架阵列120上的相邻的被包封片芯104之间相对的间隔。
在附图1D中,使用锯或激光切割穿过引线110来执行单颗化。单颗化是将组装在单个引线框架120上的各装置彼此分隔。单颗化之后,附图1E示出,引线110被压迫向下以形成附图1F的弯曲引线110。如附图1F所示,弯曲引线110从中间部分113向外延伸,中间部分113位于或接近于所形成的半导体装置100的装置厚度的中部。
概述
根据本公开的一个实施例,提供了一种制造封装的半导体装置的方法,所述方法包括:(a)形成包括安装在第一引线框架上的片芯的子组件;和(b)将第二引线框架附接到所述子组件,其中第二引线框架提供用于所述封装的半导体装置的引线。
根据本公开又一实施例,提供了一种封装的半导体装置,包括:第一引线框架;安装在所述第一引线框架上的片芯;和附接到所述第一引线框架的第二引线框架,其中所述第二引线框架提供用于所述封装的半导体装置的引线。
附图的简要说明
本发明的实施例通过示例进行描述,并且不受限于相应的附图,其中相似的参考标记代表相似的元件。附图中的元件出于简单和清晰的目的而示出,并且并不必然按比例绘制。例如,为了清楚,可以将层和区域的厚度放大。
附图1A-1B和1D-1F示出了常规QFP半导体装置组装的不同阶段的简化截面图,附图1C示出了在单颗化之前具有被包封的片芯的引线框架阵列的简化俯视图;
附图2A和2B示出了引线框架阵列的简化俯视图,附图2C示出了沿着附图2B中的2C-2C线的断面侧视图,以及附图2D-2G示出了根据本发明一个实施例的半导体装置组装中不同阶段的简化截面图;和
附图3示出了根据本发明一个实施例的具有被包封的片芯的引线框架阵列的简化俯视图。
具体实施方式
在此批露本发明的详细的说明性的实施例。但是,此处披露的具体结构和功能的细节仅仅是代表性的,目的在于描述本发明的示例性实施例。本发明的实施例可以以多种可替代的方式实施,并且不应被认为仅仅限于此处说明的实施例。此外,此处所使用的术语仅仅是为了描述特定实施例的目的,而并非是对本发明的示例性实施例进行限制。
如此处使用的,单数形式的“一”和“该”意图也包括复数形式,除非上下文明确指出相反。此外,将理解,词语“包括”、“具有”、和/或“包含”指明所声明的特征、步骤或组件的存在,但并不排除一个或多个其它特征、步骤或组件的添加或存在。还应该注意的是,在一些可替换的实现方式中,所提及的功能/动作可能不按照附图中所示的顺序进行。例如,两个连续示出的图可能实际上基本同时执行,或者,有时候可能以相反的顺序执行,取决于所涉及的功能/作用。
当半导体装置以上面就附图1A-1F描述的方式构造时,能够以引线框架阵列制造的半导体装置的数量是受限制的。如附图1C中所示,为了利用同一引线框架阵列既安装片芯又形成引线意味着,能够被组装在引线框架阵列上的片芯的数量是受限制的,因为还需要同一引线框架阵列来形成引线。
以附图1A-1F的方式组装半导体装置还加长了工序。在弯曲引线形成中需要执行另外的步骤。
如此处使用的,引线框架是金属引线和可能的其它元件(例如,片芯桨板(diepaddle)(也称作片芯垫或片芯旗板)、功率条,等等))的集合,其在半导体封装中用于组装单一的封装的半导体装置。在组装成封装的装置之前,引线框架可具有支撑结构(例如,形成矩形金属框架),该结构将那些元件保持在适当位置。在组装工序期间,支撑结构可以被移除。如此处使用的,术语“引线框架”可以用来指组装之前或组装之后的元件的集合,而不管存在或不存在那些支撑结构。
需要在保持由拥有诸如弯曲“鸥翼”引线的引线提供的改善的焊接性的同时改善半导体装置的装配工艺。可通过对每一个装置使用两个引线框架来改善装配工艺:一个用于安装片芯而另一个提供引线。以这种方式装配半导体装置增加了使用一维或两维引线框架阵列同时装配的半导体装置数量,同时减少了在制造半导体装置的工序中所涉及的步骤的数目。
在一个实施例中,本发明公开了一种半导体装置的制造方法。该方法包括形成包括安装在第一引线框架上的片芯的子组件。该方法还包括:将第二引线框架附接到所述子组件,其中所述第二引线框架提供用于所述封装的半导体的引线。
附图2A示出了根据本发明一个实施例制造的具有四个引线框架202的第一(2×2)引线框架阵列220简化的俯视图。引线框架阵列220形成片芯和接合线附接在其上的结构。引线框架阵列220可以使用蚀刻工艺进行制造。使用蚀刻工艺使得引线框架阵列薄并在单颗化时易于切割。在其它实施例中,可以使用其它工艺,例如冲压,来形成引线框架阵列。引线框架阵列可以具有比附图2A中所示的更多的引线框架,且为了易于解释,所示出的引线框架的数量简化了。
如附图2A所示,引线框架阵列220包括引线框架202和延伸进每一个引线框架202内部的支撑引线框架指222。支撑结构在后来装置单颗化期间最终被去除。在装配工序期间每一个引线框架202将具有附接到某些引线框架指222的顶表面201的片芯。
附图2B示出了根据本发明一个实施例的具有四个引线框架212的第二(2×2)引线框架阵列230的简化的俯视图。第二引线框架阵列230为最终的装配的半导体装置提供引线。引线框架阵列230使用冲压工艺形成,以形成平的引线框架阵列,其然后经受弯曲工艺形成弯曲的“鸥翼”引线210,其在附图2C的截面图中更清晰地示出。应理解,第二引线框架阵列可通过不同于冲压工艺的工艺形成。此外,尽管在此处披露的实施例中形成了弯曲引线,但是可以根据所构造的半导体装置而形成其它类型的引线。
如附图2B所示的,引线框架阵列230的引线框架212互连并支撑引线210。在后来的单颗化工序期间,支撑结构将被去除。
第二引线框架阵列可以具有比附图2B所示的更多的引线框架。如下面进一步讨论的,每一个第二引线框架212被连接到相应的第一引线框架。
附图2D示出了在片芯204被接合到第一引线框架202的顶表面201之后的第一引线框架202。片芯204可以用常规的电绝缘的片芯接合粘接剂进行片芯接合。本领域技术人员将理解,可以使用适当的替代手段(例如,片芯连接带),来附接这些片芯中的一些或所有。使用一个或多个接合线206将片芯204线接合至第一引线框架202。接合线206可以由不同的导电材料形成,例如铝、金或铜,且可被涂覆(例如,绝缘)或不被涂覆(例如,非绝缘)。注意,在替换的实施例中,除使用接合线外,或者代替使用接合线,还可以使用倒装片芯或其它相关技术将片芯电连接到第一引线框架。
附图2E示出了被包封在模制料208中的线接合和片芯接合的片芯204。模制料208包封接合线206、片芯204、引线框架202的部分底表面203、和顶表面201。模制料208为半导体装置的组件提供保护。模制料208可以作为液体聚合物施加,之后使用UV或加热将其固化以形成固体。替代地,模制料208可以是固体,其被加热形成液体以施用,然后再适当冷却以形成固体封装剂。随后,可以施加热量以使模制料208固化以完成聚合物的交联。模制料208可以是如本领域已知的塑料、环氧树脂、硅石填充的树脂、陶瓷、不含卤化物的材料等,或其组合。
在附图2F中,附图2E中的具有第一引线框架阵列220的组件已经被附接至附图2B和2C的第二引线框架阵列230。通过使用焊料膏将引线框架焊接在一起而将第一引线框架阵列220附接至第二引线框架230。第一和第二引线框架也可以使用带附接。尤其是,第二引线框架212的顶表面211电附连到第一引线框架202的暴露的底表面203,从而使得弯曲引线210向下延伸并然后从第一引线框架202的底表面203向外延伸。
在附接第一引线框架阵列220到第二引线框架阵列230之后,在附图2F中示出的所得到的子组件经受单颗化工艺,其结果在附图2G中示出,其中子组件被锯切,或经受激光切割,以形成单独的封装的半导体装置215。弯曲引线210保持在第一引线框架202的底面203下延伸,并且不延伸超出封装的装置215的周界217。注意,在单颗化期间,附图2A的引线框架202和附图2B的引线框架212被去除,在适当的位置留下了被包封的引线框架指222和附接的引线210。
上面描述的工艺通过不使引线形成自其上接合片芯的同一引线框架来改善装配工艺。通过使用第二引线框架提供引线,片芯可以被分开安装在第一引线框架上,并且所得到的子组件可以安装到第二引线框架,从而允许更多的工艺时间花在装配片芯上而不是在使用那些机械形成引线上。
此外,因为不需要为引线保留空间,与现有技术的需要为引线保留空间的引线框架相比,该第一引线框架阵列可被设计为每单位面积容纳更多片芯。附图3示出了根据本发明一个实施例制造的引线框架阵列320,其上安装有紧密间隔的片芯304。相比于附图1C示出的引线框架阵列120,更多的片芯304能够安装在相似尺寸的引线框架上。
在常规的装配工艺中,片芯被安装并包封在扁平的引线框架阵列上,并且该引线框架阵列的引线直到装配工艺的最后,例如单颗化之后,才弯曲。这样,使用给定长度和宽度的引线框架阵列能够装配的装置的数量要根据未弯曲的引线的长度。利用两个不同的引线框架阵列,即,第一引线框架容纳片芯而第二引线框架提供引线,使得能够将在容纳具有一定长度和宽度的引线框架阵列的装配机器内装配更多的装置,因为可以基于引线弯曲之后的装置的横向尺寸配置容纳片芯的第一引线框架阵列。以这种方式,可以使用具有与用于现有技术装配工艺的装配机器相同的尺寸的装配机器同时装配更多的装置。取决于特定的实现方式,可以使用相同的现有技术装配机器来利用本发明的方法同时装配更多的装置。
此外,上面描述的这种改善的装配半导体装置的工艺能够在不牺牲由具有引线所提供的改善的可焊接性的情况下实现。
至此,应当理解,提供了改善的半导体装置和改善的制造封装的半导体装置的方法。未讨论电路细节,是因为这些知识对于对本发明的完整理解是并不需要的。
尽管在说明书和权利要求书中使用相对词语,例如“下”、“外”、“顶”、“底”、“在......之上”、“上面”、“下面”等,来描述本发明,但是这些词语用于说明的目的,且并必然表面永久性的相对位置。可理解的是,如此使用的词语在恰当的情况下是可互换的,从而此处描述的本发明的实施例可以以此处所示出的或以其他方式描述的取向之外的其他取向操作。
除非另有说明,诸如“第一”和“第二”的术语用于任意地区分这些术语所描述的元素。因此,这些术语并不必然表示这些元素的时间上的或其它的优先顺序。此外,权利要求中引入性的短语诸如″至少一个”和″一个或更多个″的使用不应当被认为暗示了通过一(不定冠词“a”或“an”)而对另一权利要求要素的引入将含这样引入的权利要求要素的任何特定权利要求限制到仅包含一个这样的要素的发明,即使在同一权利要求包括引入性的短语“一个或多个”或“至少一个”以及“一”(不定冠词诸如“a”或“an”)时也是如此。对于“所述”(定冠词)的使用也是如此。
尽管此处参考特定实施例描述了本发明,但是也可以进行多种修改和改变而不偏离如下面的权利要求所提出的本发明的范围。因此,本申请文件和附图应被认为是说明性的而不是限制性的意思,并且意图将所有这样的修改包括在本发明的范围内。在此就特定实施例描述的任何益处、优点、或对问题的解决方案不应被认为是任何或全部权利要求的关键的、需要的、或实质性的特征或要素。
应当理解,这里所述的示例性方法的步骤并不是必须按照所描述的顺序执行,这些方法的步骤的顺序应当被理解为仅仅是示例性的。同样,在这样的方法中可以包括附加的步骤,并且在与本发明的不同实施例一致的方法中,某些步骤可以被省略或组合。
尽管下面的方法权利要求中的元素被用相应的标签以特定的顺序陈述(如果有的话),但是除非权利要求的引述以另外的方式暗示了执行这些元素中一些或全部的特定的顺序,否则这些元素并不限于按照这样的特定的顺序执行。
在说明书包括任何权利要求中,术语“每一个”可以用于指代多个先前引述的元素或步骤中的一个或多个指定的特征。当使用开放式的术语“包括”时,术语“每一个”的引述并不排除额外的、未引述的元素或步骤。因此,将理解,装置可以具有另外外的、未引述的元素,而方法可以具有另外的、未引述的步骤,其中该另外的、未引述的元素或步骤不具有所述一个或多个指定的特征。
此处对“一个实施例”或“一实施例”的引述意指结合该实施例描述的特定的特征、结构或特性可以被包括在本发明的至少一个实施例中。在说明书不同位置处出现的短语“在一个实施例中”,并不都引述是同一实施例,也不是必然引述与其它实施例互斥的单独的或替代的实施例。对于术语“实现方式”也是如此。
被本申请中的权利要求所覆盖的实施例限于这样的实施例:(1)由本公开使得能够实现的;和(2)与法定主题对应的。不能实现的实施例以及对应于非法定主题的实施例被明确放弃,即使他们落入权利要求的范围之内。

Claims (9)

1.一种制造封装的半导体装置的方法,所述方法包括:
(a)通过将片芯接合到第一引线框架的顶表面而形成包括安装在第一引线框架上的片芯的子组件;和
(b)通过将第二引线框架的顶表面电附连到第一引线框架的暴露的底表面而将第二引线框架附接到所述子组件,其中第二引线框架提供用于所述封装的半导体装置的引线。
2.如权利要求1所述的方法,其中步骤(a)包括:
使用接合线引线将所述片芯接合到第一引线框架;和
使用模制料包封所述片芯和接合线。
3.如权利要求1所述的方法,其中所述第二引线框架的所述引线在步骤(b)之前被弯曲。
4.如权利要求3所述的方法,其中所述被弯曲的引线是鸥翼引线,其延伸不超过所述封装的半导体装置的周界。
5.如权利要求1所述的方法,其中:
所述第一引线框架是第一引线框架阵列的一部分,所述第一引线框架阵列包括通过第一支撑结构互连的第一引线框架的多个实例;
所述第二引线框架是第二引线框架阵列的一部分,所述第二引线框架阵列包括通过第二支撑结构互连的第二引线框架的多个实例;
所述子组件包括在所述第一引线框架阵列的每一个第一引线框架上安装的片芯;
步骤(b)包括将所述第二引线框架阵列附接到所述子组件;和
所述方法进一步包括在步骤(b)之后执行单颗化工艺以形成多个分离的封装的半导体封装的实例。
6.一种封装的半导体装置,包括:
第一引线框架;
通过接合到第一引线框架的顶表面而安装在所述第一引线框架上的片芯;和
通过将第二引线框架的顶表面电附连到第一引线框架的暴露的底表面而附接到所述第一引线框架的第二引线框架,其中所述第二引线框架提供用于所述封装的半导体装置的引线。
7.如权利要求6所述的封装的半导体装置,其中:
所述片芯被用接合线电连接到所述第一引线框架;和
所述片芯和接合线被包封在模制料内。
8.如权利要求6所述的封装的半导体装置,其中所述第二引线框架的引线被弯曲。
9.如权利要求8所述的封装的半导体装置,其中所述被弯曲的引线是鸥翼引线,其延伸不超过所述封装的半导体装置的周界。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102725844A (zh) * 2010-12-10 2012-10-10 松下电器产业株式会社 导电通路、使用该导电通路的半导体装置以及它们的制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW432557B (en) 1999-12-14 2001-05-01 Siliconware Precision Industries Co Ltd Chip-scale package and its manufacturing method
US6459148B1 (en) 2000-11-13 2002-10-01 Walsin Advanced Electronics Ltd QFN semiconductor package
JP3740116B2 (ja) * 2002-11-11 2006-02-01 三菱電機株式会社 モールド樹脂封止型パワー半導体装置及びその製造方法
CN100490140C (zh) 2003-07-15 2009-05-20 飞思卡尔半导体公司 双规引线框
US7517733B2 (en) 2007-03-22 2009-04-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
KR101187903B1 (ko) * 2007-07-09 2012-10-05 삼성테크윈 주식회사 리드 프레임 및 이를 구비한 반도체 패키지
US8471373B2 (en) * 2010-06-11 2013-06-25 Panasonic Corporation Resin-sealed semiconductor device and method for fabricating the same
US20130015567A1 (en) * 2010-10-21 2013-01-17 Panasonic Corporation Semiconductor device and production method for same
WO2013027354A1 (ja) * 2011-08-25 2013-02-28 パナソニック株式会社 接合体、パワー半導体装置及びそれらの製造方法
CN102956509A (zh) 2011-08-31 2013-03-06 飞思卡尔半导体公司 功率器件和封装该功率器件的方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102725844A (zh) * 2010-12-10 2012-10-10 松下电器产业株式会社 导电通路、使用该导电通路的半导体装置以及它们的制造方法

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